Als Sda Fpga 01 3s500e

ALS-SDA-FPGA-01-XC3S500E
FPGA-XC3S500E-TRAINER
(USER MANUAL)
ADVANCED ELECTRONIC SYSTEMS

#143,9TH MAIN ROAD, NEAR LAGGERE CROSS,
3rd Phase Peenya Industrial Area, BANGALORE-560 058
KARNATAKA, INDIA.
PHONE: 080-41625285,41539484
Mobile: 9886493721
E-MAIL: sales@alsindia.net
URL: www.alsindia.net
Marketing: Phone: 080-23420880,23420883
ADVANCED ELECTRONIC SYSTEMS Page 1 of 30

CONTENTS
SL.No CHAPTER HEADING PAGE No
CHAPTER-1 INTRODUCTION 3
CHAPTER-2 SPECIFICATION 4
CHAPTER-3 HARDWARE DESCRIPTION 6
CHAPTER-4 DAUGHTER BOARD FPGA (XILINX) 12
CHAPTER-5 DOWNLOADING PROCEDURES 24
CHAPTER-6 PROGRAMMING PROCEDURES 26

CHAPTER-1
INTRODUCTION
The ALS-SDA-FPGA-01-TRAINER is a powerful tool that allows the user to understand

the capabilities of FPGA. With the help of the trainer and the guided instructions in the
manual, it is very easy to understand and make programs, implement, configure and test
them.
1. Field Programmable Gate Array (FPGA)

It consists of smaller function blocks in large number spread out evenly across the entire
chip along with programmable interconnects. FPGAs don't retain the configuration once
powered off.
2. HDL (Hardware Description language)

HDL is a software language, which is used to describe hardware for the purpose of
simulation, modeling, testing, design and documentation of the digital systems.
There are mainly two types of HDL
1. VHDL (Very high speed integrated circuit HDL)
2. Verilog
3. Configuration
Configuration is the process by which the bit streams of a design, as generated by the
development software are loaded into the internal configuration memory of the FPGA.

CHAPTER-2
SPECIFICATION
2.1 ALS-SDA-FPGA-01-TRAINER contains the following parts
1. Baseboard & Daughter Board
2. Programming tool & Power supply
2.1.1 Base board & Daughter Board
 32 inputs Toggle switches. Each input of these switches has an LED indication.
 32 outputs through output ports of FPGA connected to LEDs
 16x1 Alpha-numeric LCD display with the backlight.
 Four-digit 7-segment dsplays
 4x4 key matrix
 10 MHz clock and one of four different clocks(5MHz, 1MHz, 500KHz, 100KHz)
 On-board multiple DC supply voltage generator
 26-PIN FRC Cable for connecting to ALS standard interfaces like ADC, DAC,
Elevator etc
 Four sets of 20x2 female berg connector to plug the DAUGHTER BOARD.
 SPARTAN-3E XILINX FPGA Daughter
The appropriate program can be downloaded from the PC in to the FPGA on the
daughter board using ALS-DOWNLOADING tool.
2.1.2 Downloading tool:
There are two types of downloading tools from ALS. These tools are used to program the
FPGAs. These tools connect to JTAG port or Serial port of the daughter board on one end
and to PC parallel port on the other end. It derives power from the target - daughter
board.

DOWNLOADING TOOL CONNECTION DIAGRAM FOR XILINX/ALTERA
Power supply
 ALS power supply- PS7 (+5V, 1.5A)
 Onboard Regulated power supply +3.3V, +2.5V, +1.5V and +1.2V

CHAPTER-3
HARDWARE DESCRIPTION (BASEBOARD)
This chapter gives a detailed description of the hardware available in the Baseboard. It
facilitates the user to allot various I/Os of the FPGA to the hardware present on this
board.
CONNECTION DIAGRAM OF BASE BOARD
ALS interface board Downloading tool

pc
parallel
cable
26 PIN CONNECTOR JTAG

POWER
7 seg display CN10
CONNECTOR
CN1
CN13
CN12
CN11
PB1
LCD DISPLAY
CN2
O/P LED STATUS
I/P STATUS LED

5MHZ 1MHZ 500KHZ 100KHZ KEY MATRIX
16 INPUT SWITCHES
3.1 SEVEN SEGMENT DISPLAY
There are four seven-segment LED displays in the trainer. The I/Ps SEG-A to SEG-DP are
multiplexed O/Ps of the FPGA/CPLD. Any of the four digits can be selected using AN1 to
AN4 signals. These segments are active low ON i.e., they are common-anode type.
The connection details of the 7 segment LED display are as mentioned below.

PIN DETAILS
Signal CN14 Connector
AN1 PIN 2
AN2 PIN 3
AN3 PIN 4
AN4 PIN 5
SEG1 PIN 8
SEG2 PIN 9
SEG3 PIN 11
SEG4 PIN 12
SEG5 PIN 15
SEG6 PIN 16
SEG7 PIN 18
SEG8 PIN 19
NOTE: To enable the 7-segment display, ensure that the CN12 and CN13 connectors are
short through a 10-Pin FRC connector.
3.2 LEDs
There are totally 64 LEDs present in the trainer, 32 I/P LEDs indicate the 32 toggle switch
status (GREEN from 1 to 32) and 32 O/P LEDs (RED from 1 to 32) that can be assigned to
FPGA outputs for monitoring. These LEDs are active high type, i.e., they switch ON to
indicate a logical ‘1’ status.
PIN DETAILS
OPLED 1 PIN 19
OPLED 2 PIN 21
OPLED 3 PIN 23
OPLED 4 PIN 25
OPLED 5 PIN 27
OPLED 6 PIN 29
OPLED 7 PIN 31

OPLED 8 PIN 33
OPLED 9 PIN 35
OPLED 10 PIN 37
OPLED 11 PIN 5
OPLED 12 PIN 7
OPLED 13 PIN 9
OPLED 14 PIN 11
OPLED 15 PIN 13
OPLED 16 PIN 15
OPLED 17 PIN 23
OPLED 18 PIN 25
OPLED 19 PIN 27
OPLED 20 PIN 29
OPLED 21 PIN 31
OPLED 22 PIN 33
OPLED 23 PIN 35
OPLED 24 PIN 3
OPLED 25 PIN 5
OPLED 26 PIN 7
OPLED 27 PIN 9
OPLED 28 PIN 11
OPLED 29 PIN 13
OPLED 30 PIN 15
OPLED 31 PIN 17
OPLED 32 PIN 19
3.3 PUSH BUTTON SWITCH
There is a Push button switch, which is provided to generate mono pulses. It generates an active
low pulse.

The Push button that is provided on the Baseboard could be used as RESET, CLK etc depending
on the application.
PIN DETAILS
PSB1 PIN 38
3.4 TOGGLE SWITCH
There are 32 toggle switches provided on the baseboard, which are connected to 32 inputs LEDs
(GREEN from 1 to 32) and to the connectors connecting the Daughter Board. TOGGLE switches
are represented on baseboard from SW1 through SW32.
PIN DETAILS
TS1 PIN 20
TS2 PIN 22
TS3 PIN 24
TS4 PIN 26
TS5 PIN 28
TS6 PIN 30
TS7 PIN 32
TS8 PIN 34
TS9 PIN 36
TS10 PIN 38
TS11 PIN 6
TS12 PIN 8
TS13 PIN 10
TS14 PIN 12
TS15 PIN 14
TS16 PIN 16
TS17 PIN 24
TS19 PIN 28

TS20 PIN 30
TS21 PIN 32
TS22 PIN 34
TS23 PIN 36
TS18 PIN 37
TS24 PIN 4
TS25 PIN 6
TS26 PIN 8
TS27 PIN 10
TS28 PIN 12
TS29 PIN 14
TS30 PIN 16
TS31 PIN 18
TS32 PIN 20
3.5 4X4 MATRIX SWITCH
The baseboard consists of 4X4 matrix Pushbuttons, which could be used as the inputs to the
Daughter Boards.
PIN DETAILS
PB1 PIN 22
PB2 PIN 23
PB3 PIN 24
PB4 PIN 25
PB5 PIN 26
PB6 PIN 27
PB7 PIN 28
PB8 PIN 29

3.6 LCD Display
The ALS FPGA/CPLD trainer has a 16 X 1 Alphanumeric LCD display with backlight on the
Baseboard. The connection details is as shown in the table below.
PIN DETAILS
Signal CN14 Connection
RS PIN 9
RW PIN 10
EI PIN 11
DT0 PIN 12
DT1 PIN 13
DT2 PIN 14
DT3 PIN 15
NOTE:To enable the LCD display, ensure that the connector CN11 and CN12 are shorted
through a 10-Pin FRC connector.

CHAPTER-4
DAUGHTER BOARD (FPGA - XILINX)
INTRODUCTION
The Spartan™-3E family of Field-Programmable Gate Arrays is specifically designed to
meet the needs of high volume, Cost-sensitive consumer electronic applications. The eight-
member family offers densities ranging from 50,000 to five million-system gates. Because of their
exceptionally low cost, Spartan-3E FPGAs are ideally suited to a wide range of consumer
electronics applications, including broadband access, home networking, display/projection and
digital television equipment.
Features:
 Spartan –3E FPGA device XC3S500E-PQ208 of Xilinx.
 It has 500k System gates
 It consists of 10,476 logic cells
 And it employs 73k Distributed RAM
 It also has 360K Block RAM
 It is an FPGA IC in a PQFP208 pin package with 232 I/O lines
 Push button switch PROG to initiate FPGA during master serial

Mode.
 Four sets of 20x2 berg connector for plugging on to the baseboard
 Mode selection jumpers (JP1)
 Power supply +3.3V, 2.5V and 1.2V are provided from the Baseboard.
The SPARTAN-3E FPGA of XILINX uses SRAM technology. SPARTAN-3E devices support both
serial configurations, using the master/slave serial and JTAG modes, as well as byte-wide

configuration employing the Slave Parallel mode.
Spartan-3E devices support the following four configuration modes:
 Slave Serial mode

 Master Serial mode
 Slave Parallel mode
 Boundary-scan mode
The trainer allows the user to choose two configuration modes among the above four, the Master
serial mode and Boundary-scan mode.
NOTE:
Usage of PROM is optional, if the PROM is used, user has to go for Master serial mode,
which is, as given below otherwise user has to configure through Boundary-scan mode.
For master serial mode configuration, a serial PROM (17xx or 18xx family) has to be used.
Initially program is loaded to the serial PROM, and then by using the PROM the IC is configured.
Connectors are provided to mount a Daughter board containing serial PROM. In Master modes,
the FPGA addresses an external PROM or EPROM storage device, and reads data from it. No
additional timing or control signals are used.
For boundary-scan mode of programming, a 10-PIN FRC connector is provided. In this mode
PROM is not used and the program is directly loaded to the IC through a JTAG connector. The
programming board would be configured using a PC.
FPGA contains SRAM memory for configuration, thus the configuration is lost when the power is
switched OFF. The FPGA is configured after the power ON by various means like JTAG, serial
modes.

CONNECTION DIAGRAM OF FPGA:
10-Pin JTAG Connector details
The CN1 JTAG connector on the Daughter board is used to configure the FPGA or to program the
optional Xilinx PROM XCF04s-V020c. The JTAG cable is connected to the board through CN1 at
one end and other end to the 10-pin FRC connector of JTAG parallel adapter from the PC parallel
port.
NOTE: The JP1 jumper provided on the FPGA Daughter board for mode selection, which
is as tabulated below.
TABLE 1 - JUMPER JP1 details
Pin number Boundary scan Master serial Configuration

(JTAG) devices
Pin 1 & Pin 2 Closed Open FPGA and PROM
Pin 2 & Pin 3 Open Closed FPGA

PIN DETAILS OF JTAG

PIN NUMBER DESCRIPTION
1 +3.3V
2 GND
3 GND
4 TCK
5 TMS
6 TDO
7 TDI
8 NC
9 GND
10 NC
DEDICATED PINS FOR FPGA
XC3S500E DEDICATED PINS FUNCTION
10,17,27,37,52,53,70, GND
79,84,85,95,156,141,
131,121,105,208,198,188,182,
173
21,38,46,59,73,88,143,125,114, +3.3V
201,191,176
7,44,66,92,149,111,195,166 +2.5V
13,67,117,170 +1.2V
81,86 MODE
87 DIN
104 DONE

1 PROG
207 TDI
158 TCK
155 TMS
157 TD0
103 CCLK
 +3.3V, +2.5V and +1.2V

The +5V DC source from the Baseboard is used, then using DC-DC converter (regulator)
the required +3.3V, +1.2V and +2.5V are generated. LEDs are provided to show the presence of
+3.3, +2.5, +1.2V and +5V Supply.
PROG SWITCH
This Daughter Board provides a Push button switch for initiating the configuration of the FPGA if
only when the PROM is used. This switch is used to configure FPGA from the already programmed
ISP PROM. Upon activation of the PROG signal the ISP PROM initiates the configuration of the
FPGA.
DONE LED
This LED is used on the FPGA Daughter Board to indicate that the configuration of FPGA has
occurred.
PINOUTS OF INPUT AND OUTPUT
SIGNAL CN3 CONNECTION XC3S500E–SPARTAN –3E
AN1 PIN5 PIN2
AN2 PIN6 PIN3
AN3 PIN7 PIN4
AN4 PIN8 PIN5

SEG1/RS PIN9 PIN8
SEG2/RW PIN10 PIN9
SEG3/EI PIN11 PIN11
SEG4/DTO PIN12 PIN12
SEG5/DT1 PIN13 PIN15
SEG8 PIN16 PIN19
TS1 PIN20 PIN6
TS2 PIN22 PIN14
TS3 PIN24 PIN20
TS4 PIN26 PIN23
TS5 PIN28 PIN26
TS6 PIN30 PIN32
TS7 PIN32 PIN43
TS8 PIN34 PIN51
TS9 PIN36 PIN54
TS10 PIN38 PIN57
TS11 PIN6 PIN58
TS12 PIN8 PIN71
TS13 PIN10 PIN72
TS14 PIN12 PIN39
TS15 PIN14 PIN91

TS16 PIN16 PIN101
TS17 PIN24 PIN110
TS18 PIN37 PIN112
TS19 PIN28 PIN124
TS20 PIN30 PIN130
TS21 PIN32 PIN136
TS22 PIN34 PIN142
TS23 PIN36 PIN148
TS24 PIN4 PIN154
TS25 PIN6 PIN159
TS26 PIN8 PIN169
TS27 PIN10 PIN174
TS28 PIN12 PIN175
TS29 PIN14 PIN183
TS30 PIN16 PIN184
TS31 PIN18 PIN194
TS32 PIN20 PIN204
OPLED1 PIN19 PIN22
OPLED2 PIN21 PIN24
OPLED3 PIN23 PIN28
OPLED4 PIN25 PIN30
OPLED5 PIN27 PIN33

OPLED6 PIN29 PIN35
OPLED7 PIN31 PIN41
OPLED8 PIN33 PIN42
OPLED9 PIN35 PIN47
OPLED10 PIN37 PIN49
OPLED11 PIN5 PIN55
OPLED12 PIN7 PIN61
OPLED13 PIN9 PIN63
OPLED14 PIN11 PIN65
OPLED15 PIN13 PIN69
OPLED16 PIN15 PIN75
OPLED17 PIN23 PIN77
OPLED18 PIN25 PIN89
OPLED19 PIN27 PIN90
OPLED20 PIN29 PIN94
OPLED21 PIN31 PIN97
OPLED22 PIN33 PIN99
OPLED23 PIN35 PIN36
OPLED24 PIN3 PIN106
OPLED25 PIN5 PIN108
OPLED26 PIN7 PIN112
OPLED27 PIN9 PIN115

OPLED28 PIN11 PIN119
10MHz CLK PIN18 PIN80
CLK1 PIN19 PIN82
CLK2 PIN20 PIN83
PB1 PIN22 PIN135
PB2 PIN23 PIN137
PB3 PIN24 PIN138
PB4 PIN25 PIN139
PB5 PIN26 PIN140
PB6 PIN27 PIN144
PB7 PIN28 PIN145
PB8 PIN29 PIN146
PSB1 PIN38 PIN165
R PIN30 PIN147
G PIN31 PIN150
B PIN32 PIN151
HS PIN33 PIN152
VS PIN34 PIN153

TXD PIN35 PIN45
RXD PIN36 PIN161
PS2C PIN37 PIN167
PS2D PIN38 PIN168
IO1 PIN13 PIN160
IO2 PIN14 PIN162
IO3 PIN15 PIN163
IO4 PIN16 PIN164
IO5 PIN17 PIN171
IO6 PIN18 PIN172
IO7 PIN19 PIN177
IO8 PIN20 PIN178
IO9 PIN21 PIN179
IO10 PIN22 PIN180
IO11 PIN23 PIN181
IO12 PIN24 PIN185
IO13 PIN25 PIN186
IO14 PIN26 PIN187
IO15 PIN27 PIN189
IO16 PIN28 PIN190
IO17 PIN29 PIN192
IO18 PIN30 PIN193
IO19 PIN31 PIN196

IO20 PIN32 PIN197
IO21 PIN33 PIN199
IO22 PIN34 PIN200
IO23 PIN35 PIN202
IO24 PIN36 PIN203
SIGNAL CN2 CONNECTOR XC3S500E–SPARTAN –3E

(ON DAUGHTER
BOARD)
IO25 PIN1 PIN205
IO26 PIN2 PIN107
IO27 PIN3 PIN109
IO28 PIN4 PIN113
IO29 PIN5 PIN116
IO30 PIN6 PIN120
IO31 PIN7 PIN123
IO32 PIN8 PIN126
IO33 PIN9 PIN128
IO34 PIN10 PIN132
IO35 PIN11 PIN134
IO36 PIN16 PIN60
IO37 PIN17 PIN62
IO38 PIN18 PIN64
IO39 PIN12 PIN68
IO40 PIN13 PIN74

IO41 PIN14 PIN76
IO42 PIN15 PIN78
IO43 PIN20 PIN93
IO44 PIN19 PIN96
SIGNAL CN1 CONNECTOR XC3S500E–SPARTAN –3E

(ON DAUGHTER
BOARD)
IO45 PIN1 PIN98
IO46 PIN2 PIN100

PIN3
IO47 PIN102
PIN4
IO48 PIN50
PIN5
IO49 PIN48
PIN6
IO50 PIN40
PIN7
IO51 PIN34
PIN8
IO52 PIN31
PIN9
IO53 PIN29
PIN10
IO54 PIN25

CHAPTER 5
DOWNLOADING PROCEDURE FOR FPGA
For physical verification of the code, user has to follow VLSI design flow, which is as follows.
1 Design entry
2. Synthesis
3. Gate level simulation
4. Implementation
5. Programming
Design entry
In this, the user can write HDL code either in VHDL or verilog. There are mainly two types which
user has to specify.
 Entity
 Architecture
Entity: Entity is the specification of input and output signals / ports.
Architecture: Architecture is the functional description of the design

in HDL format.
Synthesis
Synthesis is a process of conversion of HDL code to Gate level net list of the design. Net list is the
connectivity description of gate level circuit. Synthesis is a target technology dependent issue,
hence user has to specify the target / device correctly including its package type and speed grade.
After synthesis EDA tool will generate EDIF/XNF file.
Simulation
In simulation the user can verify the functionality of design after synthesis. This simulation is also
called gate level simulation. In this user can select required input and output signals, and simulate

various input conditions and observe the output results.
Any wrong results obtained from the program have to be rectified by modifying HDL code, re-
synthesis and simulate till user gets desired results.
Implementation
This is also called place and route. Before implementation of design, user must write the UCF
(user constraint file) that describes the pin locking of input and output signals.
At the time of implementation set the UCF file to place and route tool to implement the design and
fix the Input/Output signals as per design requirement.
User can get the gate consumption and pin diagram details by referring the implementation
reports.
Programming
Programming is the process of downloading the final bit file generated by the tool into the target
device. Interface the target device to parallel port of computer through an ALS XILINX
downloading tool.
Tool will offer two options JTAG/ PROM formatter.
Select the cable type viz. parallel. Once the cable is sensed then, download the design by using
download option. If the device is configured properly the green LED (Done) given on the FPGA
board will glow indicating proper configuration of the device.

CHAPTER 6
PROGRAMMING PROCEDURE FOR FPGA
1.Click the PROJECT NAVIGATOR icon on the desktop.

 Main window is opened
2.Go to FILE, open a NEW PROJECT file.
FIRST WINDOW
21. In the first text box: Enter the name of the project
22. In the second text box: Enter the path of the program
23. In the third text box: Enter the TOP LEVEL MODULE TYPE as
‘HDL’
Click on ‘NEXT’ to proceed
SECOND WINDOW: Select the Device and Design flow for the project
In this window following texts are shown. Select the following options present on the right side of
the window.
 Device family: Ex: Spartan-3E

 Device: Ex: XC3S500E
 Package: Ex: PQ208
 Speed grade: Ex:-4
 Top level Module type: HDL
 Synthesis tool: Modelsim
 Generated simulation language: VHDL
Click on ‘NEXT’, successively for 3 times and then Press ‘FINISH’. After this, user will
automatically get in to Main window
In the Main window, go to PROJECT MENU, Select NEW SOURCE. A Third window is opened.

THIRD WINDOW: Create a new source

In the first text box: Select the VHDL module
In the second text box: Enter the file name
In the third text box: It will show the same PATH, whatever user has
entered in the FIRST WINDOW.
FOURTH WINDOW: Define VHDL source
 Entity name: Default

 Architecture name: Default
This window shows a table to enter inputs and outputs
Port name Direction MSB LSB
1. Port name: Enter the Input and Output names

2. Direction: Select In or out or In/out (Depending upon the application)
3. MSB: Select the number of bit
4. LSB: Select the number of bit
FIFTH WINDOW: New source information

New source information
 Source type: VHDL module
 Source name: <name>.vhd
 Entity name: <Default>
 Architecture name: <Default>
Click ‘FINISH ‘ to get into Main window.

 Enter the Program
 Do simulation (if any errors, remove the errors)

 Click on Assign package pins in process window (sub division of USER

CONSTRAINTS) and save the file
 After assigning package pins click on implement design in process window.
 Click on Generate programming in process window.
 After generating programming file click on configure device iMPACT
 Finally select a *.bit file for FPGA.
DESIGN DOWNLOADING
The ALS FPGA Trainer supports multiple methods of configuring the FPGA. The JTAG port
on the Daughter Board can be used to directly configure the FPGA. The slave serial port on this
Daughter Board can also be used to configure the FPGA.
JTAG interface
The JTAG connector present on the corresponding Daughter Board can be used to
configure the FPGA. The JTAG connector present on the DAUGHTER BOARD is connected to the
downloading tool XILINX. The other end of the downloading tool is connected to the PC parallel
port.
Configuring FPGA through JTAG interface

When the JTAG port is used to configure the FPGA, the following steps must be taken:
 Design entry: Write HDL code in VHDL for the model.
 Synthesis: Synthesize the HDL code.
 Simulation: User can verify the functionality of design using simulation.
 Implementation: Write the UCF (user constraint file), which describes the pin
locking of input and output signals.
 Implement the design file.
 Generate a bit file.
Note: while generating bit file and jed file make sure that Start up clock is
connected to the JTAG clock. (Xilinx Bit generation utility properties
startup clock)

 Connect one end of a 10-pin FRC cable to the DAUGHTER BOARD (JTAG for
FPGA) and other end to the 10 PIN FRC connector of JTAG parallel adapter,
the other end of which connects to the PC parallel port.
 Short the mode selection jumpers for boundary scan mode i.e. short pins 1
and 2 of JP1 for FPGA.
 Run Xilinx JTAG programmer (impact) utility to load the design bit file into
the SPARTAN-3E FPGA.
 Click Boundary scan mode.
 Clicks automatically connected to cable and identify boundary scan chain
 Select the *.bit file for FPGA.
 Right click on the device and click program to configure FPGA.
 Done LED lights up when programming is succeeded in FPGA.
Configuring FPGA through Master serial interface

To configure through PROM the following steps must be taken:
To generate mcs file
Design entry: Write HDL code in VHDL for the model.
Synthesis: Synthesis the HDL code.
1. Simulation: User can verify the functionality of design using simulation.
2. Implementation: Write the UCF (user constraint file), which describes the pin locking of
input and output signals. Implement the design file.
3. Generate a bit file.
4. Run Xilinx generate PROM, ACE or JTAG file (IMPACT)
5. Click PROM file
6. Click next
7. Click Xilinx serial PROM
8. Click mcs as a PROM file format
9. Enter PROM file name
10. Specify the location in which mcs file to be stored.
11. Click next
12. Select a PROM as XCF and beside of this textbox as xcfo1
13. Click on ADD
14. Click on next

15. File generation summary will open and then Click on next
16. Click on ADD file
17. Select the bit file to convert as mcs file.
18. Click finish to start generating file.
19. Connect one end of a 10-pin FRC cable to the DAUGHTER BOARD JTAG and other end to
the 10 PIN FRC connector of JTAG parallel adapter, the other end of which connects to the
PC parallel port.
20. Short the 1 and 2 pins of jumper JP1
21. Download the .mcs file into PROM.
22. Right click on the device and click program to configure FPGA-PROM.
23. After downloading short the pins 2 and 3 of JP1
24. Press PROG switch to configure the IC. A done LED will light UP When FPGA is configured
successfully.
NOTE: while generating bit file ensure that the Start up clock is connected to the CCLK clock.

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ALS-SDA-FPGA-01-XC3S500E

ADVANCED ELECTRONIC SYSTEMS

ADVANCED ELECTRONIC SYSTEMS Page 1 of 30

SL.No CHAPTER HEADING PAGE No

CHAPTER-3 HARDWARE DESCRIPTION 6

CHAPTER-4 DAUGHTER BOARD FPGA (XILINX) 12

CHAPTER-5 DOWNLOADING PROCEDURES 24

CHAPTER-6 PROGRAMMING PROCEDURES 26

ADVANCED ELECTRONIC SYSTEMS Page 2 of 30

The ALS-SDA-FPGA-01-TRAINER is a powerful tool that allows the user to understand

1. Field Programmable Gate Array (FPGA)

2. HDL (Hardware Description language)

ADVANCED ELECTRONIC SYSTEMS Page 3 of 30

2.1 ALS-SDA-FPGA-01-TRAINER contains the following parts

1. Baseboard & Daughter Board

2. Programming tool & Power supply

2.1.1 Base board & Daughter Board

2.1.2 Downloading tool:

ADVANCED ELECTRONIC SYSTEMS Page 4 of 30

DOWNLOADING TOOL CONNECTION DIAGRAM FOR XILINX/ALTERA

ADVANCED ELECTRONIC SYSTEMS Page 5 of 30

CONNECTION DIAGRAM OF BASE BOARD

ALS interface board Downloading tool

26 PIN CONNECTOR JTAG

I/P STATUS LED

3.1 SEVEN SEGMENT DISPLAY

ADVANCED ELECTRONIC SYSTEMS Page 6 of 30

ADVANCED ELECTRONIC SYSTEMS Page 7 of 30

3.3 PUSH BUTTON SWITCH

ADVANCED ELECTRONIC SYSTEMS Page 8 of 30

3.4 TOGGLE SWITCH

ADVANCED ELECTRONIC SYSTEMS Page 9 of 30

3.5 4X4 MATRIX SWITCH

ADVANCED ELECTRONIC SYSTEMS Page 10 of 30

3.6 LCD Display

ADVANCED ELECTRONIC SYSTEMS Page 11 of 30

 Spartan –3E FPGA device XC3S500E-PQ208 of Xilinx.

 It has 500k System gates

 It consists of 10,476 logic cells

 And it employs 73k Distributed RAM

 It also has 360K Block RAM

 It is an FPGA IC in a PQFP208 pin package with 232 I/O lines

 Push button switch PROG to initiate FPGA during master serial

 Mode selection jumpers (JP1)

ADVANCED ELECTRONIC SYSTEMS Page 12 of 30

configuration employing the Slave Parallel mode.

Spartan-3E devices support the following four configuration modes:

 Slave Serial mode

ADVANCED ELECTRONIC SYSTEMS Page 13 of 30

CONNECTION DIAGRAM OF FPGA:

10-Pin JTAG Connector details

TABLE 1 - JUMPER JP1 details

Pin number Boundary scan Master serial Configuration

Pin 1 & Pin 2 Closed Open FPGA and PROM

Pin 2 & Pin 3 Open Closed FPGA

ADVANCED ELECTRONIC SYSTEMS Page 14 of 30

PIN DETAILS OF JTAG

DEDICATED PINS FOR FPGA

XC3S500E DEDICATED PINS FUNCTION

ADVANCED ELECTRONIC SYSTEMS Page 15 of 30

 +3.3V, +2.5V and +1.2V

PINOUTS OF INPUT AND OUTPUT

SIGNAL CN3 CONNECTION XC3S500E–SPARTAN –3E

AN1 PIN5 PIN2