Events & Transactions

• In a signal assignment statement when the value of L.H.S. changes an

event is said to have occurred.

• When a value is scheduled to be assigned to target signal , a

transaction is placed on the driver of target signal.

• A transaction that does not changed value of a signal is still a

transaction, but it does not cause an event on the signal.

• In the simulation phase, creation of signals is called elaboration

& assigning initial values to them is called initialization.
• When simulation time progresses, a signal becomes active if a
transaction is placed on the driver of the signal.

• An event is generated for signal if value of signal is updated.

08/18/09 PHG 1
 Example- full adder

• Architecture behaviour of full adder is

• Signal sum1,sum2,c1,c2: bit;
• Begin
• Cout<= c1 or c2;
• Sum<= sum2;
• C2<= sum1 and c;
• C1<= a and b;
• Sum2<= sum1 xor c;
• Sum1<= a xor b;
• End behaviour;

08/18/09 PHG 2
 20 ns 20 ns+δ 20 ns+2δ 20 ns+3δ 20 ns+4δ

a 0 0 0 0 0
b 0 1 1 1 1
c 0 0 0 0 0
sum1 0 0 1 1 1
sum2 0 0 0 1 1
sum 0 0 0 0 1
c1 0 0 0 0 0
c2 0 0 0 0 0
cout 0 0 0 0 0
transactio b ->1 Sum1 ->1 Sum2 ->1 Sum ->1
n
queue C1 -> 0 C2 -> 0

event sum1 sum2 sum

08/18/09
b PHG 3
 Modeling Behavior
• Architecture body
– describes an implementation of an entity
– may be several per entity
• Behavioral architecture
– describes the algorithm performed by the module
– contains
• process statements, each containing
• sequential statements, including
• signal assignment statements and
• wait statements

08/18/09 PHG 4
 Process statement
• Contains sequentially executed statements
• Exist within an architecture, only
• Several processes run concurrently
• Execution is controlled either via
• sensitivity list (contains trigger signals), or
• wait-statements
• The process label is optional
• Because the statements within an architecture operate
concurrently another VHDL construct is necessary to
achieve sequential behaviour.
•
08/18/09 PHG 5
 continued
• A process, as a whole, is treated concurrently like any other
statement in an architecture.
• In fact it is possible to use the process statement as the only
concurrent VHDL statement.
The execution of a process is triggered by events.
• Either the possible event sources are listed in the sensitivity list or
explicit wait statements are used to control the flow of execution.
• These two options are mutually exclussive, i.e. no wait statements
are allowed in a process with sensitivity list.

08/18/09 PHG 6
 continued
• While the sensitivity list is usually ignored by synthesis tools, a
VHDL simulator will invoke the process code whenever the value
of at least one of the listed signals changes.

• Consequently, all signals that are read in a purely combinational

process, i.e. that influence the behaviour, have to be mentioned in
the sensitivity list if the simulation is to produce the same results
as the synthesized hardware.

• Of course the same is true for clocked processes, yet new register
values are to be calculated with every active clock edge, only.
Therefore the sensitivity list contains the clock signal and
asynchronous control signals (e.g. reset).

08/18/09 PHG 7
 continued
• A process with sensitivity list suspends automatically after the
last statement in the process is executed.
• When there is a subsequent event on a signal in its sensitivity
list ,the process resumes execution, starting with the first
statement and executes to it’s last statement.

08/18/09 PHG 8
 example
• entity AND_OR_XOR is
port (A,B : in bit;
Z_OR, Z_AND, Z_XOR : out bit);
end AND_OR_XOR;
architecture RTL of AND_OR_XOR is
begin
A_O_X: process (A, B)
begin
Z_OR <= A or B;
Z_AND <= A and B;
Z_XOR <= A xor B;
end process A_O_X ;
end RTL;

08/18/09 PHG 9
 Communicating processes

08/18/09 PHG 10
 continued
• All processes of a VHDL design run in parallel, no matter in
which entity or hierarchy level they are located.
• They communicate with each other via signals.
• These signals need to be ports of the entities if processes
from different architectures depend from another.

08/18/09 PHG 11
 Variable assignment
• Variables are available within processes, only
• named within process declarations
• known only in this process
• Variables and signals show a fundamentally different behaviour.
• In a process, the last signal assignment to a signal is carried out
when the process execution is suspended.
• Value assignments to variables, however, are carried out
immediately.
• To distinguish between a signal and a variable assignment
different symbols are used: ' <= ' indicates a signal assignment
and ' := ' indicates a variable assignment.

08/18/09 PHG 12
 continued
• architecture RTL of XYZ is
signal A, B, C : integer range 0 to 7;
signal Y, Z : integer range 0 to 15;
begin
process (A, B, C)
variable M, N : integer range 0 to 7;
begin
M := A;
N := B;
Z <= M + N;
M := C;
Y <= M + N;
end process;
end RTL;

08/18/09 PHG 13
 • Synthesis result of previous program is
Two 8 bit adders

08/18/09 PHG 14
 Variables vs. Signals
• library ieee;
• use ieee.std_logic_1164.all;
• use ieee.std_logic_arith.all;
• use ieee.std_logic_unsigned.all;
• entity sap is
• port(a,b,c: in signed(2 downto 0);
• y,z: out signed(2 downto 0));
• end sap;
• architecture arch of sap is
• begin
• process (A, B, C)
• variable M, N : signed(2 downto 0);
• begin
• M := A;
•08/18/09 PHG 15
 continued
• N := B;
• Z <= M + N;
• M := C;
• Y <= M + N;
• end process;
• end arch;
•

08/18/09 PHG 16
 continued

08/18/09 PHG 17
 Example 2
• entity sap1 is
• port(
• y,z: out integer );
• end sap1;
• architecture arch of sap1 is
• signal A,B,C ,M,N : integer;
• begin
• process (A, B, C,M,N)
• begin
• M <= A;
• N <= B;
• 08/18/09 PHG 18
 continued
• Z <= M + N;
• M <= C;
• y <= M + N;
• end process;
• end arch;

• Signal values are assigned after the process execution

• Only the last signal assignment is carried out

08/18/09 PHG 19
 continued

08/18/09 PHG 20
• Variables are especially suited for the implementation of algorithms.
• Usually, the signal values are copied into variables before the
algorithm is carried out.
• The result is assigned to a signal again afterwards.
• Variables keep their value from one process call to the next, i.e.if a
variable is read before a value has been assigned, the variable will
have to show storage behaviour.
• That means it will have to be synthesized to a latch or flip-flop
respectively.

08/18/09 PHG 21
 A two-process half-adder model
• entity halfadder is
• port (x, y : in std_logic;
• sum, carry: out std_logic);
• end entity halfadder;
• architecture behavior of halfadder is
• begin
• process(x,y) is -- this process computes the value of sum
• begin
• if (x = y) then
• sum <= '0' after 5ns;
• else
• sum <= (x or y) after 5 ns;
• end if;
• end process;

08/18/09 PHG 22
 continued
• process (x,y) is -- this process computes the value of carry
• begin
• Case x is
• when'O'=>
• carry <= x after 5 ns;
• when ‘1’ =>
• carry <= y after 5 ns;
• when others =>
• carry <= 'X' after 5 ns;
• end case;
• end process;
• end architecture behavior;

08/18/09 PHG 23
 Communicating process model for full adder

• library IEEE;
• use IEEE.std_logic_1164.all;
• entity full_adder is
• port (In1, c_in, In2 : in std_logic; sum, c_out : out std_logic);
• end entity full_adder;

• architecture behavioral of full_adder is

• signal s1, s2, s3: std_logic;
• constant delay :Time:= 5 ns;
• begin
• HA 1: process (In1, In2) --process describing the first half
• adder
• begin
• s1 <= (In1 xor In2) after delay;
• s3 <= (In1 and In2) after delay;
• end process HA 1 ;
08/18/09 PHG 24
 continued
• HA2: process(s1 ,c_in) --process
• describing the second half adder
• begin
• sum <= (s1 xor c_in) after delay;
• s2 <= (s1 and c_in) after delay;
• end process HA2;
• OR1: process (s2, s3) -- process
• describing the two-input OR gate
• begin
• c_out <= (s2 or s3) after delay;
• 'end process OR1;
• end architecture behavioral;

08/18/09 PHG 25
 FOR Loops

• entity FOR_LOOP is
port (A : in integer range 0 to 3;
Z : out bit_vector (3 downto 0));
end FOR_LOOP;
architecture EXAMPLE of FOR_LOOP is
begin
process (A)
begin
Z <= "0000";
for I in 0 to 3 loop
if (A = I) then
Z(I) <= `1`;
end if;
end loop;
end process;
end EXAMPLE;
•

08/18/09 PHG 26
 continued

08/18/09 PHG 27
 continued
• Loop parameter is implicitly declared
– can not be declared externally
– read only access
• The loop parameter adopts all values from the range definition
– integer ranges
– enumerated types

08/18/09 PHG 28
 Loop Syntax

• [LOOP_LABEL :]
for IDENTIFIER in DISCRETE_RANGE loop
-- sequential statements
end loop [LOOP_LABEL] ;

•
[LOOP_LABEL :]
while CONDITION loop
-- sequential statements
end loop [LOOP_LABEL] ;

08/18/09 PHG 29
 continued
• Optional label
• FOR loop identifier
– not declared
– read only
– not visible outside the loop
• Range attributes
– `low
– `high
– `range
•
Synthesis requirements:
- Loops must have a fixed range
- 'while' constructs usually cannot be synthesized

08/18/09 PHG 30
 Loop Example
• entity CONV_INT is
port (VECTOR: in bit_vector(7 downto 0);
RESULT: out integer);
end CONV_INT;
• architecture A of CONV_INT is
begin
process(VECTOR)
variable TMP: integer;
begin
TMP := 0;
for I in 7 downto 0 loop
if (VECTOR(I)='1') then
TMP := TMP + 2**I;
end if;
end loop;
RESULT <= TMP;
end process;
end A;

08/18/09 PHG 31
 continue

08/18/09 PHG 32
 Example 2
• architecture B of CONV_INT is
begin
process(VECTOR)
variable TMP: integer;
begin
TMP := 0;
for I in VECTOR'range loop
if (VECTOR(I)='1') then
TMP := TMP + 2**I;
end if;
end loop;
RESULT <= TMP;
end process;
end B;

08/18/09 PHG 33
 Example 3
• architecture C of CONV_INT is
begin
process(VECTOR)
variable TMP: integer;
variable I : integer;
begin
TMP := 0;
I := VECTOR'high;
while (I >= VECTOR'low) loop
if (VECTOR(I)='1') then
TMP := TMP + 2**I;
end if;
I := I - 1;
end loop;
RESULT <= TMP;
end process;
end C;

08/18/09 PHG 34