A Project Report

on

DESIGN OF EFFICIENT VLSI ARCHITECTURE OF

FM0/MANCHESTER ENCODING METHODS USING
SOLS TECHNIQUE FOR DSRC APPLICATIONS

Submitted for partial fulfillment of the requirements for the award of the degree
of

BACHELOR OF ENGINEERING

IN

ELECTRONICS AND COMMUNICATION ENGINEERING

BY

Mr. B. Ganesh Kumar (1602-14-735-010)

Mr. S . Lokesh (1602-14-735-019)
Mr. K. Mahesh Reddy (1602-14-735-020)

Under the guidance of

Mr.SK. KHAJAVALI
Asst. Professor
Department of ECE
VCE(A), Hyderabad.

Department of Electronics and Communication Engineering

Vasavi College of Engineering (Autonomous)
Ibrahimbagh,Hyderabad-500031

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

i
 VASAVI COLLEGE OF ENGINEERING
(AUTONOMOUS)

HYDERABAD

2017-18

CERTIFICATE

This is to certify that the project work entitled “DESIGN

OF EFFICIENT
VLSI ARCHITECTURE OF FM0/MANCHESTER
ENCODING METHODS USING SOLS TECHNIQUE FOR
DSRC APPLICATIONS” is a bona fide work carried out by B.Ganesh
(1602-14-735-010), S.Lokesh(1602-14-735-019), K.Mahesh Reddy (1602-14-735-
020) in partial fulfillment of the requirements for the award of degree of
BACHELOR OF ENGINEERING IN ELECTRONICS AND
COMMUNICATION ENGINEERING, VASAVI COLLEGE OF ENGINEERING
(Autonomous) by the OSMANIA UNIVERSITY, Hyderabad, under our guidance
and supervision.

The results embodied in this report have not been submitted to any other
university or institute for the award of any degree or diploma.

Internal Guide Head of the Department

Mr.Sk Khajavali Dr. K. Jaya Sankar
Asst. Professor Professor and Head
Department of ECE Department of ECE
VCE (A), Hyderabad. VCE(A), Hyderabad.

ii
 DECLARATION

This is to certify that the work reported in the present project entitled "

DESIGN OF EFFICIENT VLSI ARCHITECTURE OF

FM0/MANCHESTER ENCODING METHODS USING SOLS
TECHNIQUE FOR DSRC APPLICATIONS "is a record of work done
by us in the Department of Electronics and Communication Engineering, Vasavi
College of Engineering (A), Osmania University, Hyderabad. The reports are based
on the project work done entirely by us and not copied from any other source.

S.Lokesh

iii
 ACKNOWLEDGEMENTS

I would like to express my sincere gratitude and indebtedness to my project

supervisor Mr.Sk Khajavali for his valuable suggestions and interest throughout
the course of this project

I am also thankful to Head of the department Dr. K. Jaya Sankar for providing
excellent infrastructure and a nice atmosphere for completing this project successfully

I convey my heartfelt thanks to the lab staff for allowing me to use the required
equipment whenever needed

Finally, I would like to take this opportunity to thank my family for their support
through the work. I sincerely acknowledge and thank all those who gave directly or
indirectly their support in completion of this work

(S.Lokesh)

iv
 LIST OF FIGURES

FIG NO FIGURE NAME PAGE.NO

1.1 BLOCK DIAGRAM OF CS 5

1.2 BLOCK DIAGRAM OF ANALOG CS 7

1.3 BLOCK DIAGRAM OF DIGITAL CS 9

1.4 WAVE FORM OF UNIPOLAR NRZ 10

1.5 WAVE FORM OF BIPOLAR NRZ 10

1.6 WAVE FORM OF BIPOLAR RZ 11

1.7 WAVE FPRM OF AMI RZ SIGNALING 11

1.8 WAVE FORM OF MANCHESTER CODING 12

1.9 WAVEFORM OF CODING COMPARISIONS 12

2.0 EXAMPLE OF MC 15

2.1 XOR REPRESENTATION OF MC 16

2.2 OPERATION OF FMO 17

2.3 BLOCK DIAGRAM OF FMO 17

2.4 ILLUSTRATION OF FMO CODE 18

2.5 CMOS REALISATION OF EXOR GATE 18

2.6 CMOS REALISATION OF NOT GATE 19

4.1 FMO ENCODING 23

4.2 STATE DEFINITION OF FMO CODE 24

4.3 FSM OF FMO ENCODING 24

4.4 DIGITAL CIRCUTE FOR FMO AND MC 26

4.5 FMO ENCODING WITHOUT AND WITH AREA

COMPACT RETAINING 29

v
4.6 CONCEPT OF BALANCE LOGIC-OPERATION 29

4.7 BALANCE LOGIC OPERATION SHARING

OF A(t) AND X 30

4.8 BALANCE LOGIC OPERATION SHARING

OF B(t) AND X 30

4.9 VLSI ARCHETECTURE OF FMO AND

MANCHESTER ENCODING 31

6.1 SIMULATION OUTPUT OF D-FLIPFLOP 40

6.2 SIMULATION OUTPUT OF MUX 2X1 40

6.3 SIMULATION OUTPUT OF NOT GATE 40

6.4 SIMULATION OUTPUT OF XOR 41

6.5 SIMULATION OUTPUT OF XNOR 41

6.6 SIMULATION OUTPUT FM0/MANCHESTER

ENCODING WITHOUTSOLS 41

6.7 SIMULATION OUTPUT FM0/MANCHESTER

ENCODING WITHSOLS 42

6.8 SIMULATION OUTPUT FM0/MANCHESTER

ENCODING WITHOUTSOLS (TEST BENCH) 42

6.9 SIMULATION OUTPUT FM0/MANCHESTER

ENCODING WITHSOLS (TEST BENCH) 42

6.10 RTL SCHEMATIC FM0/MANCHESTER

ENCODING WITHOUT SOLS TECHNIQUE 43

6. 11 RTL SCHEMATIC FM0/MANCHESTER

ENCODING WITHOUT SOLS TECHNIQUE 43

6.12 TECHNOLOGY SCHEMATIC FM0/MANCHESTER

ENCODING WITHOUT SOLS TECHNIQUE 43

6.13 TECHNOLOGY SCHEMATIC FM0/MANCHESTER

ENCODING WITH SOLS TECHNIQUE 43

vi
S.NO Name of the Table Pg.no
2.1 Logic table of manchester
15
4.1 State table for FM0 encoding
25
4.2 Hardware Utilization Rate
27
4.3 HUR after SOLS
32
6.3 Comparison Table
45
LIST OF TABLES

vii
 ABSTRACT

The dedicated short-range communication (DSRC) is an emerging technique

to push the intelligent transportation system into our daily life. The DSRC standards
generally adopt FM0 and Manchester codes to reach dc-balance, enhancing the signal
reliability. Nevertheless, the coding-diversity between the FM0 and Manchester codes
seriously limits the potential to design a fully reused VLSI architecture for both.

In this paper, the similarity-oriented logic simplification (SOLS) technique is

proposed to overcome this limitation. The SOLS technique improves the hardware
utilization rate from 57.14% to 100% for both FM0 and Manchester encodings.

The encoding capability of this paper can fully support the DSRC standards of
America, Europe, and Japan. This experiment not only develops a fully reused VLSI
architecture, but also exhibits an efficient performance compared with the existing
works.

Index Terms—Dedicated short-range communication (DSRC), Similarity

oriented logic simplification (SOLS), FM0, Manchester, VLSI.

viii
 TABLE OF CONTENTS
Certificate .......................................................................................................... i
Declaration .................................................................................................... ii
Acknowledgements ........................................................................................... iv
List of Figures ................................................................................................. v
List of Tables ..................................................................................................... vi
Abstract............................................................................................................. vii

1.INTRODUCTION.......................................................................................................4

1.1 Communication....................................................................................................5
1.2 Communication System........................................................................................5
1.3 Types of Communication System.........................................................................6
1.4 Analog Communication System...........................................................................7
1.5 Digital Communication System............................................................................9
1.6 Line Coding........................................................................................................10
1.7 Digital Signalling Formats..................................................................................11
1.8 Coding Comparisons..........................................................................................13
2. LITERATURE SURVEY.........................................................................................14

2.1 Manchester code.................................................................................................15

2.2 FM0....................................................................................................................18
2.3 CMOS Realization..............................................................................................19
3. PROBLEM STATEMENT.......................................................................................20

3.1 Dedicated Short Range Communication............................................................21

4. METHODOLOGY...................................................................................................22

4.1 FM0 Encoding....................................................................................................23

4.2 Manchester Encoding.........................................................................................25
4.3 SOLS Methodology.......................................................................................28
4.4 Area-Compact Retiming.....................................................................................28
4.5 Balance Logic-Operation Sharing......................................................................29
5. VERILOG................................................................................................................33

5.1 Introduction to Verilog........................................................................................34

5.2 Module Declaration...............................................................................................34
5.3 Levels of Abstraction.............................................................................................35
5.4 Very Large Scale Integration (VLSI)..................................................................37

ix
 5.5 Field Programmable Gate Array (FPGA)...........................................................37

6. SIMULATION AND RESULTS..............................................................................38

6.1 RTL Schematic...................................................................................................42

6.2 Technology Schematic........................................................................................42
7. CONCLUSION AND FUTURE SCOPE.................................................................45

7.1 Conclusion..........................................................................................................46
7.2 Future Scope.......................................................................................................46
REFERENCES.............................................................................................................47

Appendix.................................................................................................................48-54

x
 CHAPTER 1
INTRODUCTION

11
12
1.1 COMMUNICATION

“Communication is simply the act of transferring information from one

place to another”. Communication is the act of conveying intended meaning to
another entity through the use of mutually understood signs and semiotic rules. The
basic steps of communication are the forming of communicative intent, message
composition, message encoding, transmission of signals, reception of signals,
message decoding and finally interpretation of the message by the recipient.

1.2 COMMUNICATION SYSTEM

Communications system is a collection of individual communications

networks, transmission systems, relay stations, tributary stations, and data terminal
equipment (DTE ) usually capable of interconnection and interoperation to form an
integrated whole. The components of a communications system serve a common
purpose, are technically compatible, use common procedures, respond to controls, and
operate in union.

Fig 1.1: Block diagram of Communication system

The above figure shows the elements of a communication system. There are
three essential parts of any communication system, the transmitter, transmission
channel, and receiver. Each part plays a particular role in signal transmission, as
follows:

13
Transmitter

The transmitter processes the input signal to produce a suitable transmitted

signal by using Modulation techniques or Line codings.

Transmission Channel

The transmission channel is the electrical medium that transmits the

information from source to destination.

It may be a pair of wires, a coaxial cable, or a radio wave or laser beam.

Every channel introduces some amount of transmission loss or attenuation. So, the
signal power progressively decreases with increasing distance.

Receiver

The receiver operates the output signal from the transmission channel, delivers
to the transducer at the destination. Receiver operations include amplification to
compensate for transmission loss. These also include demodulation and decoding to
reverse the signal procession performed at the transmitter. Filtering is another
important function at the receiver.

1.3 Types of Communication System

Communication systems are classified into two types. They are

 Analog Communication System

 Digital Communication System

1.4 ANALOG COMMUNICATION SYSTEM

1.4.1 Analog signal

An analog signal is any continuous signal for which the time varying feature
(variable) of the signal is a representation of some other time varying quantity, i.e.,
analogous to another time varying signal.An analog signal uses some property of the
medium to convey the signal's information

14
Any information may be conveyed by an analog signal; often such a signal is a
measured response to changes in physical phenomena, such as sound, light,
temperature, position, or pressure .The physical variable is converted to an analog
signal by a transducer.

1.4.2 Analog Communication

Analog Communication is a data transmitting technique in a format that

utilizes continuous signals to transmit data including voice, image, video, electrons
etc. An analog signal is a variable signal continuous in both time and amplitude which
is generally carried by use of modulation.

The below fig shows the block diagram of analog communication system.

Fig 1.2: Block diagram of analog communication system

The transmitter transforms the message signal into the transmitted signal. The
channel distorts and adds noise into the transmitted signal.
The receiver extracts an estimate of the message signal from the received
signal arriving from the channel.Given the analog nature of both the message signal
and the communication medium, a natural design choice is to map the analog message
signal (e.g., an audio signal, translated from the acoustic to electrical domain using a
microphone) to an analog transmitted signal (e.g., a radio wave carrying the audio
signal) that is compatible with the physical medium over which we wish to
communicate (e.g., broadcasting audio over the air from an FM radio station).

15
1.5 DIGITAL COMMUNICATION SYSTEM
1.5.1 Digital Signal
A digital signal is a signal that represents a sequence of discrete values. A
logic signal is a digital signal with only two possible values, and describes an
arbitrary bit stream. A digital signal is a physical quantity that is alternating between a
discrete set of waveforms. Alternatively, a digital signal may be considered to be the
sequence of codes represented by such a physical quantity

The physical quantity may be the alternating current or voltage of an electrical

signal, the light intensity of an optical signal, the signal strength of a radio signal or
acoustic signal, the magnetization of a magnetic storage media, et cetera. Digital
signals are present in all digital electronics, notably computing equipment and data
transmission.

A received digital signal may be impaired by noise and distortions without

necessarily affecting the digits.

In communications:

In digital communications, a digital signal is a continuous-time physical

signal, alternating between a discrete numbers of waveforms, representing a bit
stream message. The shape of the waveform depends the transmission scheme, which
may be either:

1. A line coding scheme, which produces a pulse-modulated signal, allowing

baseband transmission; or
2. A digital modulation scheme, allowing pass band transmission over long wires
or over a limited radio frequency band. Such a carrier-modulated sine wave is
considered a digital signal in literature on digital communications and data
transmission, but considered as a bit-stream converted to an analog signal in
electronics and computer networking.

1.5.2 Digital Communication

16
 Digital communications mean transferring data from one place to another. It is
done by physical path or physical connection. In digital communication, digital values
are taken as the discrete set. It is bit complicated as compare to analog communication
and its also fast and appropriate in modern situations.

Fig 1.3 : Block diagram of Digital Communication System

1.6 LINE CODING

1.6.1 Requirements
Digital data can be transmitted by various pulse waveforms, also called line
codes. The following properties are desirable for a line code:
 It is important that the pulses stream to be transmitted does not have a DC
component. It can case baseline wander or Galvanic Corrosion.
 It should be relatively easy to recover the data clock.
 The line coding scheme should be bandwidth efficient.
 The line code should be robust in the presence of noise.
 It should be possible to recognize a line coding error, sometimes called a line
violation. (In some signaling protocols, a line violation is deliberately generated to
mark the start of a frame).

17
1.7 Digital Signalling Formats

1.7.1 Unipolar Non Return to Zero (NRZ)

Symbol 1 is represented by transmitting a pulse of constant amplitude for the
entire duration of the bit interval, and symbol 0 is represented by no pulse.
NRZ indicates that the assigned amplitude level is maintained throughout the
entire bit period. Unipolar also contains a strong DC component.

Fig 1.4 : Waveform of unipolar NRZ

In telecommunication, a non-return-to-zero (NRZ) line code is a binary code in which
"1's" are represented by one significant condition and "0's" are represented by the
other significant condition, with no other neutral or rest condition.
For a given data signaling rate, i.e., bit rate, the NRZ code requires only half the
bandwidth required by the Manchester code.

1.7.2 Bipolar NRZ

Pulses of equal positive and negative amplitudes represent symbols 1 and 0.
(e.g. ± 5 volts, ± 12 volts) In either case, the assigned pulse amplitude level is
maintained throughout the bit interval. Because of the positive and negative levels the
average voltage will tend towards zero and hence little DC component.
Again synchronization will be difficult.

Fig 1.5 : Waveform of Bipolar NRZ

1.7.3 Unipolar Return to Zero (RZ)

Symbol 1 is represented by a positive pulse that returns to zero before the end
of the bit interval and symbol 0 is represented by the absence of pulse.

18
1.7.4 Bipolar RZ
Positive and negative pulses of equal amplitude are used for symbol 1 and
symbol 0. In either case the pulse returns to 0 before the end of the bit interval.
Return-to-zero (RZ) describes a line code used in telecommunications signals in
which the signal drops (returns) to zero between each pulse. This takes place even if a
number of consecutive zeros or ones occur in the signal.
The signal is self-clocking. This means that a separate clock does not need to be with
the signal, but suffers from using twice the bandwidth to achieve the same data-rate as
compared to non-return-to-zero format.

Fig 1.6 : Waveform of Bipolar RZ

1.7.5 Alternate Mark Inversion (AMI) RZ Signalling

Positive and negative pulses (of equal amplitude) are used for alternative
symbols 1 .No pulse is used for symbol 0. In either case the pulse returns to 0 before
the end of the bit interval.

Fig 1.7: Waveform of AMI RZ signalling

A binary 0 is encoded as zero volts as in unipolar encoding. A binary 1 is encoded
alternately as a positive voltage and a negative voltage. This prevents a significant
build-up of DC, as the positive and negative pulses average to zero volts.
Little or no DC-component is considered an advantage because the cable may then be
used for longer distances and to carry power for intermediate equipment such as line

19
repeaters. The DC-component can be easily and cheaply removed before the signal
reaches the decoding circuitry.

1.7.6 Manchester Coding

Symbol 1 is represented by a positive pulse followed by a negative pulse -
with each pulse being of equal amplitude and duration of half a pulse. For symbol 0
the polarities of these pulses are reversed. An advantage of this coding is that it is easy
to recover the original data clock.
Manchester coding provides a simple way to encode arbitrary binary sequences
without ever having long periods without level transitions, thus preventing the loss of
clock synchronization, or bit errors from low-frequency drift on poorly-equalized
analog links (see ones-density).

Fig 1.8: Waveform of Manchester coding

 Time is divided into periods, and one bit is transmitted per period.
 A "0" is expressed by a low-to-high transition, a "1" by high-to-low transition.
 The transitions signifying 0 or 1 occur at the midpoint of a period.
1.8 Coding Comparisons
1 0 1 1 0 0 1 0

Unipolar NRZ

Bipolar NRZ

Unipolar RZ

Biplolar RZ

AMI

Manchester

Fig 1.9: Waveform of Coding comparision

20
 CHAPTER 2
LITERATURE REVIEW

21
2.1.Manchester code
Manchester coding is also known as phase coding .Manchester coding is a line
code in which the encoding of each data bit is either low then high, or high then low,
of equal time. It therefore has no DC component, and is self-clocking, which means
that it may be inductively or capacitively coupled, and that a clock signal can be
recovered from the encoded data.
Background of Manchester code:

The name comes from its development at the University of Manchester, where
the coding was used to store data on the magnetic drum of the Manchester Mark
1 computer.

Manchester coding is widely used (e.g., in 10BASE-T Ethernet (IEEE

802.3); consumer IR protocols; see also RFID or near field communication). There
are more complex codes, such as 8B/10B encoding, that use less bandwidth to achieve
the same data rate but may be less tolerant of frequency errors and jitter in the
transmitter and receiver reference clocks

Features of Manchester code:

Manchester code ensures frequent line voltage transitions, directly

proportional to the clock rate; this helps clock recovery.

The DC component of the encoded signal is not dependent on the data and therefore
carries no information, allowing the signal to be conveyed conveniently by media
(e.g., Ethernet) which usually do not convey a DC component.

22
Description:

Original data clock Manchester code

0 0 0

0 1 1

1 0 1

1 1 0

Table2.1 : Logic table of manchester

Fig 2.0: Example of Manchester code

Xor representation of Manchester code:

23
 Fig 2.1:E-XOR representation of manchester code

 Each bit is transmitted in a fixed time (the "period").

 A 0 is expressed by a low-to-high transition, a 1 by high-to-low transition
(according to G.E. Thomas' convention—in the IEEE 802.3 convention, the
reverse is true).
 The transitions which signify 0 or 1 occur at the midpoint of a period.
 Transitions at the start of a period are overhead and don't signify data.

Manchester code always has a transition at the middle of each bit period and
may (depending on the information to be transmitted) have a transition at the start of
the period also. The direction of the mid-bit transition indicates the data. Transitions
at the period boundaries do not carry information. They exist only to place the signal
in the correct state to allow the mid-bit transition. The existence of guaranteed
transitions allows the signal to be self-clocking, and also allows the receiver to align
correctly; the receiver can identify if it is misaligned by half a bit period, as there will
no longer always be a transition during each bit period. The price of these benefits is a
doubling of the bandwidth requirement compared to simpler NRZ coding schemes .

2.2.FM0

24
 FM0 is also known as Bi phase space encoding. A transition is present on
every bit and an additional transition may occur in the middle of the bit

fig2.2: operation of FM0

For each X , the FM0 code consists of two parts: one for former-half cycle of CLK,
A, and the other one for later-half cycle of CLK, B . The coding principle of FM0 is
listed as the following three rules. If X is the logic-0, the FM0 code must exhibit a
transition between A and B. If X is the logic-1, no transition is allowed between A
and B .The transition is allocated among each FM0 code no matter what the x is

FIG 2.3:-Block diagram of fm0

A FM0 coding example is shown in Fig. 3. At cycle 1, the X is logic-0; therefore, a

transition occurs on its FM0 code, according to rule 1.
For simplicity, this transition is initially set from logic-0 to -1. According to rule 3,

a transition is allocated   among each FM0 code, and thereby the logic­1 is changed to

logic­0 in the beginning of cycle 2. Then, according to rule 2, this logic­level is hold

25
without any transition in entire cycle 2 for the  X  of logic­1.Thus, the FM0 code of

each cycle can be derived with these three rules mentioned earlier.

fig 2.4: Illustration of fm0 code

2.3.CMOS REALIZATION OF COMPONENTS USED IN THE
CIRCUIT

XOR GATE

26
 FIG 2.5:CMOS Realization of E-xor gate

NOT GATE

27
FIG 2.6:CMOS Realization of not gate

28
 CHAPTER 3
PROBLEM STATEMENT

3.1 Dedicated Short Range Communication

DSRC means dedicated short-range communication. It is a one way or two-way
medium range communication especially for intelligent transportation systems. The
DSRC can be classified into two types. They are automobile-to-automobile and
automobile-to-roadside.
DSRC system architecture contains three modules. They are Broad processing,
RF-front end and micro processor. Broad processing is responsible for error
correction, modulation, clock synchronization and encoding. RF-front end transmits

29
and receives the data from antenna. Microprocessor performs the tasks of RF-front
end and broad processing.
Generally, the wave form of transmitted signal is expected to have a zero mean
for robustness issue and this is also referred as DC balance.The transmitted signal
consists of arbitrary binary sequence which is difficult to obtain DC-balance.
For the purpose we use FM0 and Manchester codes to provide DC-balance.
Both FM0 and Manchester codes are bi-phase encodings and they reduce noise and
power consumption.
Another problem in this application is hardware utilization of components.
Generally, the components are utilized only 57.14%. Among FM0 and Manchester
codes, any one logic is ON at a time. By using SOLS technique, we improve the
hardware utilization of the components from 57.14% to 100%.
SOLS means similarity oriented logic simplification.

30
 CHAPTER 4
METHODOLOGY

4.1 FM0 encoding

The coding principle of FM0 is listed as the following three rules.

1) If X is the logic-0, the FM0 code must exhibit a transition between A and B.
2) If X is the logic-1, no transition is allowed between A and B.
3) The transition is allocated among each FM0 code no matter what the X is.

31
 Fig 4.1:FM0 encoding
A FM0 coding example is shown in Fig. 4.1 . At cycle 1, the X is logic-0;
therefore, a transition occurs on its FM0 code, according to rule 1. For simplicity, this
transition is initially set from logic-0 to -1. According to rule 3, a transition is
allocated among each FM0 code, and thereby the logic-1 is changed to
logic-0 in the beginning of cycle 2. Then, according to rule 2, this
logic-level is hold without any transition in entire cycle 2 for the X of
logic-1. Thus, the FM0 code of each cycle can be derived with these
three rules mentioned earlier.

32
 Fig 4.2:state definition of FM0 code

Figure 4.3 FSM of FM0 encoder

According to the coding principle of FM0, the FSM of FM0 is shown in Fig.
4.3. Suppose the initial state is S1, and its state code is 11 for A and B, respectively. If
the X is logic-0, the state-transition must follow both rules 1 and 3. The only one
next-state that can satisfy both rules for the X of logic-0 is S3. If the X is logic-1, the
state-transition must follow both rules 2 and 3. The only one next-state that can satisfy
both rules for the X of logic-1 is S4. Thus, the state-transition of each state can be
completely constructed.

33
Table 4.1 State table for FM0 encoding
PREVIOUS STATE CURRENT STATE
A(t-1) B(t-1) X=0 X=1
A(t) B(t) A(t) B(t)
0 0 1 0 1 1
0 1 0 1 0 0
1 0 1 0 1 1
1 1 0 1 0 0

The FSM of FM0 can also conduct the transition table of each state, as shown
in Table 4.1. A(t) and B(t) represent the discrete-time state code of current-state at
time instant t. Their previous-states are denoted as the A(t − 1) and the B(t − 1),
respectively. With this transition table, the Boolean functions of A(t) and B(t) are
given as
A(t) = B(t − 1)------------------------------------------(1)
B(t) = X ⊕B(t – 1)------------------------------------(2)
With both A(t) and B(t), the Boolean function of FM0 code is denoted as
FM0=CLK A(t) + CLK B(t)-------------------------(3)
4.2 Manchester Encoding
The Manchester coding example is shown in Fig.3.4
The Manchester code is derived from
Manchester=X ⊕ CLK.
--------------------------------------------------- (4)

34
 Fig 4.4: Digital circuit for FM0 and Manchester encoding

The Manchester encoding is realized with a XOR operation for

CLK and X. The clock always has a transition within one cycle, and
so does the Manchester code no matter what the X is. With (3) and (4),
the hardware architectures of FM0 and Manchester encoders are shown in Fig. 6. The
top part is the hardware architecture of FM0 encoder, and the bottom part is the
hardware architecture of Manchester encoder. As listed in (4), the Manchester encoder
is as simple as a XOR operation for X and CLK. Nevertheless, the FM0 encoding
depends not only on the X but also on the previous-state of the FM0 code. The DFFA
and DFFB store the state code of the FM0 code. The MUX−1 is to switch A(t) and
B(t) through the selection of CLK signal. Both A(t) and B(t) are realized by (1) and
(2), respectively. The determination of which coding is adopted depends on the Mode
selection of the MUX−2, where the Mode = 0 is for FM0 code, and the Mode = 1 is
for Manchester code. To evaluate the hardware utilization, the hardware utilization
rate (HUR) is defined as
Activecomponents
HUR  X 100 -------------------------------------------(5)
totalcomponents

The component is defined as the hardware to perform a specific logic function,

such as AND, OR, NOT, and flipflop.The active components mean the components
that work for FM0 or Manchester encoding. The total components are the number of
components in the entire hardware architecture no matter what encoding method is
adopted. The HUR of FM0 and Manchester encodings is listed in Table 4.2. For both
encoding methods, the total components are 7, including MUX−2 to indicate which
coding method is activated. For FM0 encoding, the active components are 6, and its
HUR is 85.71%. For Manchester encoding, the active components are 2, comprising
XOR−2 and MUX−2, and its HUR is as low as 28.57%. On average, this hardware

35
architecture has a poor HUR of 57.14%, and almost half of total components are
wasted. The transistor count of the hardware architecture without SOLS technique is
98, where 86 transistors are for FM0 encoding and 26 transistors are for Manchester
coding. On average, only 56 transistors can be reused, and this is consistent with its
HUR. The coding-diversity between the FM0 and Manchester codes seriously limits
the potential to design a fully reused VLSI architecture.
Table 4.2: HUR

Coding Active/Total Components HUR

Fm0 6/7 85.71%

Manchester 2/7 28.57%
Average 4/7 57.14%

4.3 SOLS methodology

36
 The purpose of SOLS technique is to design a fully reused VLSI
architecture for FM0 and Manchester encodings. The SOLS
technique is classified into two parts: area-compact retiming and
balance logic-operation sharing. Each part is individually described
as follows. Finally, the performance evaluation of the SOLS
technique is given.

4.4 Area-Compact Retiming

The FM0 logic in Fig. 6 is simply shown in Fig. 4.4. The logic for A(t) and the
logic for B(t) are the Boolean functions to derive A(t) and B(t), where the X is
omitted for a concise representation. For FM0, the state code of each state is stored into
DFFA and DFFB. According to (2) and (3), the transition of state code only depends on
B(t − 1) instead of both A(t − 1) and B(t − 1). Thus, the FM0 encoding just requires a
single 1-bit flip-flop to store the B(t−1). If the DFFA is directly removed, a non-
synchronization between A(t) and B(t) causes the logic fault of FM0 code. To avoid
this logic-fault, the DFFB is relocated right after the MUX−1, as shown in Fig. 7(b),
where the DFFB is assumed to be positive-edge triggered. At each cycle, the FM0
code, comprising A and B, is derived from the logic of A(t) and the logic of B(t),
respectively.

The FM0 code is alternatively switched between A(t) and B(t) through the
MUX−1 by the control signal of the CLK. In Fig. 7(a), the Q of DFFB is directly
updated from the logic of B(t) with 1-cycle latency. In Fig. 7(b), when the CLK is
logic-0, the B(t) is passed through MUX−1 to the D of DFFB. Then, the upcoming
positive-edge of CLK updates it to the Q of DFFB. As shown in Fig. 8, the timing
diagram for the Q of DFFB is consistent whether the DFFB is relocated or not.
Suppose the logic components of FM0 encoder are realized with the logic-family of
static CMOS. The transistor count of the FM0 encoding architecture without area-
compact retiming is 72, and that with area-compact retiming is 50. The area-compact
retiming technique reduces 22 transistors.

37
 Fig 4.5: (a) FM0 encoding without area-compact retiming.
(b) FM0 encoding with area-compact retiming.
4.5 Balance Logic-Operation Sharing
As mentioned previously, the Manchester encoding can be derived from X ⊕CLK, and
it is also equivalent to
X⊕ CLK = X CLK + X CLK ----------------------------------(6)
This can be realized by the multiplexer, as shown in Fig. 3.6. It is quite similar to the
Boolean function of FM0 encoding (3). By comparing with (4) and (6), the FM0 and
Manchester logics have a common point of the multiplexer like logic with the
selection of CLK.

Fig. 4.6: Concept of balance logic-operation sharing for FM0 and Manchester
encodings.
(a) Manchester encoding in multiplexer.
(b) Combines the logic operations of Manchester and FM0 encodings.

As shown in Fig. 4.6(b), the concept of balance logic-operation sharing is to integrate

the X1 into A(t) and X into B(t), respectively.

38
 Fig. 4.7. Balance logic-operation sharing of A(t) and X1.
The logic for A(t)/X1 is shown in Fig. 4.7. The A(t) can be derived from an inverter of
B(t − 1), and X1 is obtained by an inverter of X. The logic for A(t)/X1 can share the
same inverter, and then a multiplexer is placed before the inverter to switch the
operands of B(t − 1) and X. The Mode indicates either FM0 or Manchester encoding is
adopted. The similar concept can be also applied to the logic for B(t)/X, as shown in
Fig. 11(a).

Fig. 4.8: Balance logic-operation sharing of B(t) and X.

(a) Without the XOR sharing.
(b) With XOR sharing.
(c) Sharing of the reused DFFB from area-compact retiming
technique.

Nevertheless, this architecture exhibits a drawback that the XOR is only

dedicated for FM0 encoding, and is not shared with Manchester encoding. Therefore,
the HUR of this architecture is certainly limited. The X can be also interpreted as the
X⊕0, and thereby the XOR operation can be shared with Manchester and FM0
encodings. As a result, the logic for B(t)/X is shown in Fig. 4.8(b), where the
multiplexer is responsible to switch the operands of B(t−1) and logic-0. This
architecture shares the XOR for both B(t) and X, and thereby increases the HUR.
Furthermore, the multiplexer in Fig. 4.8(b) can be functionally integrated into the

39
relocated DFFB from area-compact retiming technique, as shown in Fig. 4.8(c). The
CLR is the clear signal to reset the content of DFFB to logic-0. The DFFB can be set
to zero by activating CLR for Manchester encoding. When the FM0 code is adopted,
the CLR is disabled, and the B(t −1) can be derived from DFFB. Hence, the
multiplexer in Fig. 4.8(b) can be totally saved, and its function can be completely
integrated into the relocated DFFB.

Fig. 4.9: VLSI architecture of FM0 and Manchester encodings using SOLS
technique.
(a) Unbalance computation time between A(t)/X1 and B(t)/X.
(b) Balance computation time between A(t)/X1 and B(t)/X.

The proposed VLSI architecture of FM0/Manchester encoding using SOLS

technique is shown in Fig. 4.9(a). The logic for A(t)/X1 includes the MUX−2 and an
inverter. Instead, the logic for B(t)/X just incorporates a XOR gate. In the logic for
A(t)/X1, the computation time of MUX−2 is almost identical to that of XOR in the
logic for B(t)/X. However, the logic for A(t)/X1 further incorporates an inverter in the
series of MUX−2. This unbalance computation time between A(t)/X1 and B(t)/X

40
results in the glitch to MUX−1, possibly causing the logic-fault on coding. To
alleviate this unbalance computation time, the architecture of the balance computation
time between A(t)/X1 and B(t)/X is shown in Fig. 4.9(b).
The XOR in the logic for B(t)/X is translated into the XNOR with an inverter,
and then this inverter is shared with that of the logic for A(t)/X1. This shared inverter
is relocated backward to the output of MUX−1. Thus, the logic computation time
between A(t)/X1 and B(t)/X is more balance to each other. The adoption of FM0 or
Manchester code depends on Mode and CLR. In addition, the CLR further has
another individual function of a hardware initialization. If the CLR is simply derived
by inverting Mode without assigning an individual CLR control signal, this leads to a
conflict between the coding mode selection and the hardware
initialization. To avoid this conflict, both Mode and CLR are assumed
to be separately allocated to this design from a system controller.
Whether FM0 or Manchester code is adopted, no logic component of
the proposed VLSI architecture is wasted. Every component is active
in both FM0 and Manchester encodings. Therefore, the HUR of the
proposed VLSI architecture is greatly improved.

Table 4.3 HUR after SOLS

method Active/total HUR

components

FMO 5/5 100%

MANCHESTER 5/5 100%
AVERAGE 5/5 100%

41
 Chapter-5
VERILOG

5.1 Introduction to Verilog

VERILOG, standardized as IEEE 1364, is a hardware description
language (HDL) used to model electronic systems. It is most commonly used in
the design and verification of digital circuits at the register-transfer
level of abstraction. It is also used in the verification of analog circuits and mixed-

42
signal circuits, as well as in the design of genetic circuits.

Hardware description languages such as Verilog differ

from software programming languages because they include ways of describing the
propagation time and signal strengths (sensitivity). There are two types of assignment
operators; a blocking assignment (=), and a non-blocking (<=) assignment. The non-
blocking assignment allows designers to describe a state-machine update without
needing to declare and use temporary storage variables. Since these concepts are part
of Verilog's language semantics, designers could quickly write descriptions of large
circuits in a relatively compact and concise form. At the time of Verilog's introduction
(1984), Verilog represented a tremendous productivity improvement for circuit
designers who were already using graphical schematic capture software and specially
written software programs to document and simulate electronic circuits.

The designers of Verilog wanted a language with syntax similar to the C

programming language, which was already widely used in engineering software
development. Like C, Verilog is case-sensitive and has a basic preprocessor (though
less sophisticated than that of ANSI C/C++). Its control flow keywords (if/else, for,
while, case, etc.) are equivalent, and its operator precedence is compatible with C.
Syntactic differences include: required bit-widths for variable declarations,
demarcation of procedural blocks (Verilog uses begin/end instead of curly braces {}),
and many other minor differences. Verilog requires that variables be given a definite
size. In C these sizes are assumed from the 'type' of the variable (for instance an
integer type may be 8 bits).

5.2 Module Declaration

module | macromodule identifier (port_list) ;

ports_declaration ;

module_body ;

endmodule

43
5.3 Levels of Abstraction
5.3.1 Gate Level Modelling
Primitive logic gates are part of the Verilog language.Verilog supports basic
logic gates as predefined primitives. These primitives are instantiated like modules
except that they are predefined in verilog and do not need a module definition.

and/or – It has one scalar input and multiple scalar outputs.

Example: and a1(out,in1,in2);

Not- It has one scalar input and one scalar output.

Example: buff b1(out1,in);

5.3.2 Data Flow Modelling

Dataflow modelling is a higher level of abstraction. The designer no need to
have any knowledge of logic circuit. He should be aware of data flow of the design
Hence dataflow modelling became a very important way of implementing the design.
In dataflow modelling most of the design is implemented using continuous
assignments, which are used to drive a value onto a net. The continuous assignments
are made using the keyword assign.

The assign statement is used to make continuous assignment in the dataflow

modelling.

5.3.3 BEHAVIOUR MODELLING OR PROCEDURAL LEVEL

Behavioural models in Verilog contain procedural statements, which control

the simulation and manipulate variables of the data types. These all statements are
contained within the procedures. Each of the procedure has an activity flow associated
with it.

During simulation of behavioral model, all the flows defined by the ‘always’
and ‘initial’ statements start together at simulation time ‘zero’. All procedures in
Verilog are specified within one of the following four Blocks. 1) Initial blocks 2)
Always blocks 3) Task 4) Function

5.3.4 INITIAL, ALWAYS Statements

The initial and always statements are enabled at the beginning of simulation.

44
The initial blocks executes only once and its activity dies when the statement has
finished. In contrast, the always blocks executes repeatedly. Its activity dies only
when the simulation is terminated. There is no limit to the number of initial and
always blocks that can be defined in a module.

5.3.5 TASK
Tasks are used in all programming languages, generally known as procedures
or subroutines. The lines of code are enclosed in task....end task brackets. Data is
passed to the task, the processing done, and the result returned. They have to be
specifically called, with data ins and outs, rather than just wired in to the general
netlist. Included in the main body of code, they can be called many times, reducing
code repetition.

Task are defined in the module in which they are used. It is possible to define
task in separate file and use the compile directive ‘include to include the task in the
file which instantiates the task.Task can include timing delays, like posedge,
negedge, #delay and wait.Task can have any number of inputs and outputs

5.3.6 FUNCTION

A Verilog HDL function is the same as a task, with very little differences, like
function cannot drive more than one output, cannot contain delays.

Function are defined in the module in which they are used. It is possible to
define task in separate file and use the compile directive ‘include to include the task
in the file which instantiates the task.

Function cannot include timing delays, like posedge, negedge, #delay,which

means that function should be executed in zero time delay.Function can have any
number of inputs but only one output. Function can call other function but cannot call
task.

5.4 Very Large Scale Integration (VLSI)

Very-large-scale integration (VLSI) is the process of creating a integrated
circuit (IC) by combining hundreds of thousands of transistors or devices into a single

45
chip. VLSI began in the 1970’s when
complex semiconductor and communication technologies were being developed.
The microprocessor is a VLSI device. Before the introduction of VLSI technology
most ICs had a limited set of functions they could perform. An electronic
circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC
designers add all of these into one chip.

Structured VLSI design is a modular methodology originated by Carver

Mead and Lynn Conway for saving microchip area by minimizing the interconnect
fabrics area. This is obtained by repetitive arrangement of rectangular macro blocks
which can be interconnected using wiring by abutment. An example is partitioning
the layout of an adder into a row of equal bit slices cells. In complex designs this
structuring may be achieved by hierarchical nesting.

As microprocessors become more complex due to technology scaling,

microprocessor designers have encountered several challenges which force them to
think beyond the design plane, and look ahead to post-silicon:

5.5 Field Programmable Gate Array (FPGA)

A field-programmable gate array (FPGA) is an integrated circuit designed to
be configured by a customer or a designer after manufacturing – hence "field-
programmable". The FPGA configuration is generally specified using a hardware
description language (HDL), similar to that used for an application specific integrated
circuit (ASIC).

FPGAs contain an array of programmable logic blocks, and a hierarchy of

reconfigurable interconnects that allow the blocks to be "wired together", like many
logic gates that can be inter-wired in different configurations. Logic blocks can be
configured to perform complex combinational functions, or merely simple logic
gates like AND and XOR. In most FPGAs, logic blocks also include memory
elements, which may be simple flip-flops or more complete blocks of memory.

Contemporary field-programmable gate arrays (FPGAs) have large resources

of logic gates and RAM blocks to implement complex digital computations. As FPGA
designs employ very fast I/O rates and bidirectional data buses, it becomes a

46
challenge to verify correct timing of valid data within setup time and hold time. Floor
planning enables resource allocation within FPGAs to meet these time constraints.
FPGAs can be used to implement any logical function that an ASIC could perform.
The ability to update the functionality after shipping, partial re-configuration of a
portion of the design and the low non-recurring engineering costs relative to
an ASIC design (notwithstanding the generally higher unit cost), offer advantages for
many applications.

Some FPGAs have analog features in addition to digital functions. The most
common analog feature is a programmable slew rate on each output pin, allowing the
engineer to set low rates on lightly loaded pins that would
otherwise ring or couple unacceptably, and to set higher rates on heavily loaded pins
on high-speed channels that would otherwise run too slowly.

47
 CHAPTER – 6
Simulation and Results

6.1 Simulation Outputs

48
Fig 6.1 Simulation output of D-flipflop

Fig 6.2 Simulation output of Multiplexer 2X1

Fig 6.3 Simulation output of NOT Gate

Fig 6.4 Simulation output of Xor Gate

49
 Fig 6.5 Simulation output of Xnor Gate

Fig 6.6 Simulation output FM0/Manchester encoding without SOLS technique

Fig 6.7 Simulation output FM0/Manchester encoding with SOLS technique

50
Fig 6.8 Simulation output FM0/Manchester encoding without SOLS
technique(test bench)

Fig 6.9 Simulation output FM0/Manchester encoding with SOLS technique(test

bench)

6.1 RTL Schematic

The RTL SCHEMATIC gives the information about the user view of the
design. The internal blocks contains the basic gate representation of the logic. These
basic gate realization is purely depend upon the corresponding FPGA selection and
the internal database information.

51
Fig 6.10 RTL Schematic FM0/Manchester encoding without SOLS technique

Fig 6.11 RTL Schematic FM0/Manchester encoding with SOLS technique

6.2 Technology Schematic

The Technology Schematic gives the information about the chip view of the
design. This mainly consists of LUTs, input buffers, output buffers, D-Flipflop
components. Internally Look Up Tables (LUTs) contains the corresponding logic
boolean equations, its schematic representation, k-map representation and its truth
table representation.

52
Fig 6.12 Technology Schematic FM0/Manchester encoding without SOLS
technique

Fig 6.13 Technology Schematic FM0/Manchester encoding with SOLS technique

53
Table 6.3 Comparison

54
 CHAPTER 7
CONCLUSION & FUTURESCOPE

55
7.1 Conclusion

The project entitled, “DESIGN OF EFFICIENT VLSI ARCHITECTURE OF

FM0 / MANCHESTER ENCODING METHODS USING SOLS TECHNIQUE FOR
DSRC APPLICATIONS” has been successfully simulated and implemented on
FPGA.
The coding-diversity between FM0 and Manchester encodings causes the
limitation on hardware utilization of VLSI architecture design. A limitation analysis
on hardware utilization of FM0 and Manchester encodings is discussed in detail. In
this paper, the fully reused VLSI architecture using SOLS technique for both FM0 and
Manchester encodings is proposed. The SOLS technique eliminates the limitation on
hardware utilization by two core techniques: areacompact retiming and balance logic-
operation sharing. The area-compact retiming relocates the hardware resource and the
balance logic-operation sharing efficiently combines FM0 and Manchester encodings
with the identical logic components.

7.2 Future Scope

The prototype that was implemented in this project will further get fabricated
to an actual VLSI architecture by using industrial standard machinery. The
architecture will then be used in an actual DSRC system to communicate between
either automobile to automobile or automobile to roadside.

56
 REFERENCES

[1] A. Karagounis, A. Polyzos, B. Kotsos, and N. Assimakis, “A 90nm

Manchester code generator with CMOS switches running at 2.4 GHz and 5
GHz,” in Proc. 16th Int. Conf. Syst., Signals Image Process., Jun. 2009, pp.
1–4.
[2] F. Ahmed-Zaid, F. Bai, S. Bai, C. Basnayake, B. Bellur, S. Brovold, et al.,
“Vehicle safety communications—Applications (VSC-A) final report,” U.S.
Dept. Trans., Nat. Highway Traffic Safety Admin., Washington, DC, USA,
Rep. DOT HS 810 591, Sep. 2011.

[3] J. B. Kenney, “Dedicated short-range communications (DSRC) standards

in the United States,” Proc. IEEE, vol. 99, no. 7, pp. 1162–1182, Jul. 2011.

[4] J. Daniel, V. Taliwal, A. Meier, W. Holfelder, and R. Herrtwich, “Design

of 5.9 GHz DSRC-based vehicular safety communication,” IEEE Wireless
Commun. Mag., vol. 13, no. 5, pp. 36–43, Oct. 2006.

[5] P. Benabes, A. Gauthier, and J. Oksman, “A Manchester code generator

running at 1 GHz,” in Proc. IEEE, Int. Conf. Electron., Circuits Syst., vol. 3.
Dec. 2003, pp. 1156–1159.

[6] Y.-C. Hung, M.-M. Kuo, C.-K. Tung, and S.-H. Shieh, “High-speed
CMOS chip design for Manchester and Miller encoder,” in Proc. Intell. Inf.
Hiding Multimedia Signal Process., Sep. 2009, pp. 538–541.

57
 Appendix

APPENDIX A. PROJECT CODES

D-Flipflop
module dff(clk,clr,d,q);

58
 input clk,clr,d;

output q;

reg q;

always @(posedgeclk)

begin

if(clr==0)

q<=0;

else

q<=d;

end

endmodule

Multiplexer 2X1
module mux2_1(i0,i1,s,o);

input i0,i1,s;

output o;

assign o=(i0*(~s))+(i1*s);

endmodule

NOT Gate
module notgate(a,out);

input a;

output out;

assign out=~a;

endmodule

XOR Gate

module xorgate(a,b,out);

59
 input a,b;

output out;

assign out=(a*(~b))+((~a)*b);

endmodule

XNOR Gate
module xnorgate(a,b,out);

input a,b;

output out;

assign out=(a*b)+((~a)*(~b));

endmodule

Verilog Design for FM0/Manchester encoding without SOLS technique

module withoutsols(x,clk,clr,mode,out);

input x,clk,clr,mode;

output out;

wire w1,w2,w3,w4,w5,w6;

dff f3(clk,clr,w1,w2);

dff f4(clk,clr,w3,w4);

xorgate f1(x,w2,w1);

notgate f2(w2,w3);

mux2_1 f5(w2,w4,clk,w5);

xorgate f6(x,clk,w6);

mux2_1 f7(w5,w6,mode,out);

endmodule

Verilog Design for FM0/Manchester encoding with SOLS technique

module withsols(x,clk,clr,mode,out);

60
 input x,clk,clr,mode;

output out;

wire w1,w2,w3,w4;

dff f1(clk,clr,out,w1);

xnorgate f2(w1,x,w3);

mux2_1 f3(w1,x,mode,w2);

mux2_1 f4(w3,w2,clk,w4);

notgate f5(w4,out);

endmodule

Testbench for Verilog Design for FM0/Manchester encoding without SOLS

technique
module tb_withoutsols_prog;

regtb_x,tb_clk,tb_clr,tb_mode;

wire tb_out;

withoutsols f1(tb_x,tb_clk,tb_clr,tb_mode,tb_out);

always

#10 tb_clk=~tb_clk;

initial

begin

tb_clk=1'b1;

end

initial

begin

$monitor(tb_x,tb_clk,tb_clr,tb_mode,tb_out);

tb_clr=0;

61
 tb_mode=1;

tb_x=1'b0;

#20 tb_x=0;

#20 tb_x=1;

#20 tb_x=1;

#20 tb_x=0;

#20 tb_x=1;

#20 tb_clr=1;

tb_mode=0;

#20 tb_x=0;

#20 tb_x=1;

#20 tb_x=1;

#20 tb_x=0;

#20 tb_x=1;

end

endmodule

Testbench for Verilog Design for FM0/Manchester encoding with SOLS

technique
module tb_withsols_prog;

regtb_x,tb_clk,tb_clr,tb_mode;

wire tb_out;

withsols f1(tb_x,tb_clk,tb_clr,tb_mode,tb_out);

always

#10 tb_clk=~tb_clk;

initial

62
begin

tb_clk=1'b1;

end

initial

begin

$monitor(tb_x,tb_clk,tb_clr,tb_mode,tb_out);

tb_clr=0;

tb_mode=1;

tb_x=1'b0;

#20 tb_x=0;

#20 tb_x=1;

#20 tb_x=1;

#20 tb_x=0;

#20 tb_x=1;

#20 tb_clr=1;

tb_mode=0;

#20 tb_x=0;

#20 tb_x=1;

#20 tb_x=1;

#20 tb_x=0;

#20 tb_x=1;

end

endmodule

63
64