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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO.

10, OCTOBER 2017 7449

A Boost PFC Stage Utilized as Half-Bridge


Converter for High-Efficiency DC–DC Stage
in Power Supply Unit
Jae-Il Baek, Student Member, IEEE, Jae-Kuk Kim, Member, IEEE, Jae-Bum Lee, Student Member, IEEE,
Han-Shin Youn, Student Member, IEEE, and Gun-Woo Moon, Member, IEEE

Abstract—The half-bridge (HB) LLC converter is one of the most


attractive dc–dc converters for medium power supplies due to its
soft switching capability. However, its conversion efficiency is con-
siderably degraded in wide-link-voltage applications because of a
small magnetizing inductance and wide switching frequency vari-
ation for a high voltage gain. In this paper, a boost power factor
correction (PFC) stage, which can also play an important role dur-
ing the hold-up time, is proposed for a high-efficiency HB LLC
converter. In the proposed PFC stage, the boost PFC converter can
be effectively utilized as a HB converter by replacing a boost diode
and inductor with a synchronous switch and transformer, respec-
tively. After the ac line is lost, the proposed PFC stage can operate
as the HB converter and regulate the output voltage instead of the
HB LLC converter. Thus, it enables the HB LLC converter to be de-
signed with a large magnetizing inductance and narrow switching
frequency variation. As a result, the proposed PFC stage can en-
hance the overall efficiency of the PSU by improving the efficiency
of the HB LLC converter. To confirm the validity of this paper, a
prototype with 180–264-Vrms ac line, 250–400-V link voltage, and
48 V/480 W output is tested.
Fig. 1. General PSU over 100 W. (a) Two-stage structure. (b) Hold-up time
Index Terms—Half-bridge (HB) flyback converter, HB LLC con- requirement.
verter, hold-up time, wide input voltage range.

I. INTRODUCTION the shape of the input current to achieve a high-power quality.


ECENTLY, as information technology (IT) devices, such Moreover, it provides a constant nominal link voltage with low-
R as computer, server, and telecom, have rapidly grown, the
importance of power supply units (PSUs) has been increased.
frequency voltage ripple for the dc/dc stage as an input voltage
source. The dc/dc stage, following the boost PFC stage, offers
In general, PSUs need two requirements: 1) high efficiency galvanic isolation and precisely regulates the output voltage us-
for environmental conservation and energy saving [1]–[3], 2) ing the link voltage. For the dc/dc stage, a half-bridge (HB)
high-power quality to meet the harmonics regulations [4]. For LLC converter is one of the most popular topologies in medium
these reasons, PSUs typically adopt a two-stage structure that power (300–600 W) applications due to its wide zero-voltage-
consists of a boost power factor correction (PFC) stage and switching (ZVS) range, low-voltage stress on the primary and
dc/dc stage, as shown in Fig. 1(a). The boost PFC stage controls secondary devices, and no offset current in the transformer
[5]–[10].
Meanwhile, PSUs for IT devices should regulate the output
Manuscript received October 11, 2016; accepted November 10, 2016. Date
of publication November 22, 2016; date of current version May 9, 2017. This voltage after the ac line is lost to save data for several mil-
work was supported by the National Research Foundation of Korea (NRF) liseconds, which is called the hold-up time requirement. During
grant funded by the Korea government (MSIP) (2016R1A2B2010328). Recom- this interval, the boost PFC stage does not operate and the link
mended for publication by Associate Editor F. J. Azcondo.
J.-I. Baek, H.-S. Youn, and G.-W. Moon are with the Korea Advanced In- voltage VLink is decreased to transfer power to the load, as
stitute of Science and Technology, Daejeon 305-701, South Korea (e-mail: shown in Fig. 1(b). Thus, the HB LLC converter should be de-
dpi1067@kaist.ac.kr; poweryhs@kaist.ac.kr; gwmoon@kaist.ac.kr). signed to cover wide link voltage range, which leads to a small
J.-K. Kim is with the Department of Electrical Engineering, Inha University,
Incheon 402-751, South Korea (e-mail: jkkim99@inha.ac.kr). magnetizing inductance for a high voltage gain. However, a
J.-B. Lee is with Korea Railroad Research Institute (KRRI), Uiwang 437-757, small magnetizing inductance causes large primary conduction
South Korea (e-mail: leejb83@krri.re.kr). and switch turn-off losses. Furthermore, the HB LLC converter
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. has wide switching frequency variation to regulate the output
Digital Object Identifier 10.1109/TPEL.2016.2631626 voltage during the hold-up time, which increases the size of
0885-8993 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
7450 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 10, OCTOBER 2017

magnetic components. Therefore, it has also large core loss in


magnetic components at the normal state [9]–[10].
As aforementioned reasons, many approaches have been re-
searched and proposed to achieve a high-efficiency HB LLC
converter with a large magnetizing inductance and nar-
row switching frequency variation [6]–[10]. For example,
pulsewidth modulation (PWM) control scheme is applied to
the HB LLC converter in [6] and [7]. This method basically
utilizes the frequency control to regulate the output voltage. On
the other hand, during the hold-up time, it can obtain a high
voltage gain by using the PWM control scheme. However, the
PWM control scheme causes not only large offset current in the
transformer but also large current stress on the external resonant
inductor. Thus, it increases core losses on both the transformer
and external resonant inductor due to their enlarged sized. To
achieve a high voltage gain without the offset current in the
transformer, the method proposed in [8] and [9] replaces two
diodes in the full-bridge rectifier with synchronous switches.
In this method, replaced two synchronous switches can reduce
the secondary conduction loss. Moreover, during the hold-up
time, they are able to increase the voltage gain without the
transformer offset current by adopting the phase-shifted control
scheme. However, this method also increases the core loss of
the external resonant inductor because the phase-shifted control
scheme results in large current stress on the external resonant
inductor. Finally, in [10], additional auxiliary LC circuit is stud-
ied. In this method, the magnetizing inductance is varied by the
switching frequency. Thus, it can improve the efficiency of the
HB LLC converter with large effective magnetizing inductance,
while obtaining a high voltage gain with small effective mag-
netizing inductance during the hold-up time. Nevertheless, this
method has additional core and conduction losses in the auxil- Fig. 2. Derivation of proposed PFC stage. (a) Boost PFC converter with boost
iary circuit. In addition, it causes large primary current stress on diode. (b) Boost PFC converter with synchronous switch and HB converter.
the external resonant inductor. Therefore, it is also difficult to (c) Proposed PFC stage.
accomplish a high efficiency.
In this paper, a boost PFC stage, which can be utilized as the II. CONCEPT OF PROPOSED PFC STAGE
HB converter, is proposed to achieve a high-efficiency HB LLC
converter. The proposed PFC stage can be effectively derived A. Derivation
by replacing a boost diode and inductor with a switch and trans- Typically, the boost PFC converter is required in PSUs to
former, respectively. When the ac line is supplied, the proposed satisfy the harmonic regulations and provide the nominal link
PFC stage basically operates like the conventional boost PFC voltage for the dc/dc stage at the normal state. However, as
converter. Thus, it provides nominal link voltage for the HB mentioned previously, since the ac line is lost, the boost PFC
LLC converter at the normal state. On the other hand, during the converter becomes inactive and the link voltage is decreased
hold-up time, the proposed PFC stage can deploy the inactive during the hold-up time. Thus, the dc/dc stage should cover
boost PFC converter as the HB converter, which can cover wide wide link voltage range. On the other hand, the proposed PFC
link voltage range instead of the HB LLC converter. As a re- stage enables the dc/dc stage to operate only at the normal state
sult, because the HB LLC converter operates only at the normal by utilizing the inactive boost PFC converter as the HB converter
state, it can be designed with a large magnetizing inductance and efficiently during the hold-up time.
narrow switching frequency variation without aforementioned Fig. 2 shows the derivation of the proposed PFC stage. First,
drawbacks. as shown in Fig. 2(a), the boost PFC converter is composed of
This paper is an improved version of the paper reported in the boost inductor LB , boost switch QB , boost diode DB , and
[11]. Compared to the previous paper, the analysis and exper- link capacitor CLink . Moreover, the input filter capacitor Cin
imental results are newly added, and the overall contents were is generally employed to decrease the electromagnetic interfer-
improved. This paper presents derivation and analysis, includ- ence (EMI) noise [12]–[13]. Meanwhile, the boost diode can be
ing operational principles and design example, of the proposed replaced with a synchronous switch QS to reduce the conduction
PFC stage. Finally, the effectiveness of the proposed PFC stage loss of the boost PFC converter, which has been generally used
is confirmed by the experimental results. [14], as depicted in Fig. 2(b). From this figure, when the boost
BAEK et al.: BOOST PFC STAGE UTILIZED AS HALF-BRIDGE CONVERTER FOR HIGH-EFFICIENCY DC–DC STAGE IN POWER SUPPLY UNIT 7451

Fig. 3. Circuit diagram of proposed PSU.

PFC converter with QS is arranged in the bilateral symmetric,


the HB inverter can be easily derived by substituting the boost
inductor LB with a boost transformer TB . Therefore, the boost
PFC converter can be effectively utilized as the HB converter in
the proposed PFC stage, as shown in Fig. 2(c). As can be seen
in this figure, the proposed PFC stage has three modifications:
1) the boost diode DB is substituted with a synchronous switch
QS , 2) the boost inductor LB is replaced with a transformer TB ,
and 3) the rectifier of the HB converter is added to the secondary
side of the dc/dc stage. From efficiency point of view, although
the boost transformer can increase the conduction loss of the
proposed PFC stage, the efficiency of the proposed PFC can
be slightly improved because the synchronous switch QS can Fig. 4. Operation modes of proposed PSU. (a) At normal state. (b) During
hold-up time.
compensate the conduction loss.
B. Implementation
The proposed PFC stage can employ various types of HB
converters. Among them, the HB flyback (HBF) converter with
a single-ended rectifier is utilized to minimize the complexity of
the proposed circuit in this paper. Thus, the circuit diagram of
the proposed PSU can be depicted as shown in Fig. 3. From this
figure, the HBF converter is composed of two main switches
QB and QS , input filter capacitor Cin as the blocking capacitor,
and boost transformer TB including the boost inductor LB , and
leakage inductor LB -lkg [15]–[16]. In case of the HB LLC con-
verter, it consists of the primary switches Q1 and Q2 , resonant
inductor LR , resonant capacitor CR , magnetizing inductor Lm ,
rectifier diodes D1 and D2 , output capacitor CO , and output
resistance RO . Typically, LR is the sum of a leakage inductor of
the transformer Llkg and an external resonant inductor Lext . Fur-
thermore, one additional switch QA is added to the secondary
side of the proposed PSU to implement ON/OFF control of Fig. 5. Key waveforms of HBF converter during hold-up time.
the HBF converter. Therefore, the HBF converter does not oper-
ate when QA is turned OFF at the normal state, while it regulates the circuit diagram of the proposed PSU at the normal state. In
the output voltage VO during the hold-up time by turning on QA . this figure, since QA is turned OFF, the proposed PFC stage can
From power loss point of view, since QA is series connected with operate like the conventional boost PFC converter. On the other
diode DA , it causes additional conduction loss during the hold- hand, during the hold-up time, the proposed PFC stage can be
up time. However, its impact on the hold-up time operation is utilized as the HBF converter by turning ON QA , as shown in
negligible because the hold-up time is very short as well as the Fig. 4(b). As a result, the HBF converter can cover wide link
additional loss is small. voltage range instead of the HB LLC converter.
In this part, brief operational principles of the HBF converter
C. Operational Principles
are presented to explain the design guideline of the proposed
The basic operation of the proposed PSU can be classified PFC stage easily. Fig. 5 shows the key waveforms of the HBF
according to status of the ac line. For instance, Fig. 4(a) shows converter. From this figure, each switching period is simply
7452 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 10, OCTOBER 2017

divided into two intervals, i.e., t0 − t1 and t1 − t2 , except for the TABLE I
DESIGN PARAMETERS OF BOOST PFC CONVERTERS
dead time between QB and QS . To perform the mode analysis,
several assumptions are made as follows: 1) D1 and D2 are
Parameters Conventional Proposed
turned OFF because the HB LLC converter has lower voltage
gain than the HBF converter during the hold-up time. 2) VLink , Boost switch, Q S IPP60R125C6
VO , and output current IO , and voltage of input filter capacitor Rectifier devices, D B /Q S D B : SCS206AM Q S : C3M006509J
VC in are constant. Input filter capacitor, Ci n 1μF
Build-up period [t0 -t1 ]: When QB is turned OFF and QS Boost inductor, L B Core: EI3633 × 2B L B -m a x : -
is turned ON at t0 , build-up period begins. Since VLink -VC in 0.35T, L B : 1 mH, N1 :
is applied to LB and LB -lkg , the rectifier diode DA is reverse 27 turns
Boost transformer, T B Core: EI3633 × 2B L B -m a x :
biased, and the currents of LB and LB -lkg are given by -
0.35T, L B : 1 mH, L B -l k g :
6μH, N1 : N2 = 27: 9
VLink -VC i n Link capacitor, CL i n k 250μF
iL B (t) = iB -L lkg (t) = iL B (t0 ) + (t − t0 )
(LB + LB -lkg ) Hold-up time, tH o l d 18ms @ Full load condition
(1) Link voltage, VL i n k 250-400 V (VL i n k −n o m : 390 V)
where VC in is approximately Dfly VLink , nfly and Dfly are the
transformer turns-ratio and duty cycle of the HBF converter,
respectively. A. Boost PFC Converter
Meanwhile, the maximum flux density of the boost trans- The design procedure of the conventional boost PFC con-
former BL B -m ax can be expressed as verter is well described in [17], which can be also applied to
the proposed PFC stage. Table I shows the design parameters
LB iL B - m ax of the conventional and proposed boost PFC converters. The
BL B - m ax = (2)
N1 AL B boost PFC converters employ silicon carbide devices to solve
the reverse recovery problems. The input filter capacitor Cin
where iL B -m ax is the maximum current of iL B , N1 and AL B
is selected as 1 μF to reduce the EMI noise [12]. The boost
are the primary turns and effective cross-section area of the
inductor LB is designed to be about 1 mH using the amorphous
boost transformer, respectively. From (1) and (2), and Fig. 5, it
EI3633 core for 30% inductor current ripple. Meanwhile, the
is obvious that BL B -m ax occurs at t1 .
proposed one has the additional boost leakage inductor LB -lkg ,
Powering period [t1 -t2 ]: When QS is turned OFF and QB
which is measured as 6 μH in the experiment due to the sec-
is turned on at t1 , powering period begins. As shown in
ondary turns N2 designed in the HBF converter part. However,
Fig. 5, LB -lkg and Cin start to resonate. Thus, the difference
it can be negligible because it is much smaller than LB . Further-
of iB -L lkg (t) and iL B (t) is reflected to the secondary current
more, although the proposed one uses the synchronous switch
isec (t), and it can be expressed as follows:
QS , it does not degrade the regulation performance of the boost
PFC converter because QS can be generally controlled only to
isec (t) = nfly [iB -L lkg (t) − iL B (t)]
reduce the conduction loss. Finally, the 450 V/250 μF capacitor
(nfly VO − Dfly VLink ) is used as a link capacitor CLink . Thus, when the nominal link
= nfly sin wR -fly (t − t1 ) (3)
ZR -fly voltage VLink−nom is regulated as 390 V at the normal state, the
maximum ripple voltage ΔVLink-m ax and minimum link voltage
where ZR -fly = (LB -lkg /Cin )0.5 and wR -fly = 1/[(Cin VLink-m in can be calculated by
LB -lkg )0.5 ]. From (3) and Fig. 5, it is noted that if the powering
PO -m ax
period, i.e., (1 − Dfly )TS -fly , is smaller than π/wR -fly , the ΔVLink-m ax = (4)
HBF converter is not able to achieve the zero-current-switching 2πfLine CLink ηdc-dc VLink-nom
(ZCS) operation of DA . VLink-m in

2PO -m ax tHold
III. DESIGN CONSIDERATIONS = (VLink-nom − 0.5ΔVLink-m ax )2 − (5)
CLink ηdc-dc
To illustrate the design procedure of the proposed PSU, the
boost PFC, HB LLC, and HBF converters should be considered. where PO -m ax is the maximum output power, fLine is the line
Moreover, they are compared with the conventional PSU. The frequency, ηdc-dc is the expected efficiency of the dc/dc stage,
design specifications are 180–264 Vrm s ac line and 480 W/48 V and tHold is the hold-up time. Based on Table I, (4), and (5), the
output. link voltage range can be determined as 250–400 V.

VO 1
ML L C = =   (6)
VLink  2 2  2 
 2 
f R −L L C
2nL L C 1+ 1
k 1 − f S −L L C + 8nπ 2 Q ffRS −L LC
−L L C
− f R −L L C
f S −L L C
LLC
BAEK et al.: BOOST PFC STAGE UTILIZED AS HALF-BRIDGE CONVERTER FOR HIGH-EFFICIENCY DC–DC STAGE IN POWER SUPPLY UNIT 7453

TABLE II
TRANSFORMER CORE DESIGN OF HB LLC CONVERTERS

Parameters Conventional Proposed

Design point VL i n k : 250 V VL i n k : 375 V


Magnetizing inductance, L m 180 μH 440 μH
Max. magnetizing current, iL m −m a x 3.24 A 1.27 A
Max. flux density, Bm a x 0.2 T
Window utility factor, K U 0.3
Current density, J 1000 A/cm2
Primary RMS current, iL R −r m s 4.48 A 3.00 A
Secondary RMS current, i D 1 -r m s 10.10 A 8.25 A
Area product, AP −T r a n s 9248.55 mm4 6641.35 mm4
Fig. 6. DC-conversion ratio of HB LLC converter according to fS -LLC and Selected transformer core PQ2625(9548mm4 ) PQ2620(6825mm4 )
Lm .

B. HB LLC Converter by considering the ZVS conditions of the primary switches as


follows:
Based on part III-A, the HB LLC converter in the conventional
nL L C VO tdead
PSU, i.e., conventional HB LLC converter, should be designed Lm ≤ (7)
with 250–400-V link voltage range to satisfy the hold-up time 8CO S S VLink-m ax fS-L L C -M ax
requirement. On the other hand, the HB LLC converter in the where tdead is the dead time between the primary switches,
proposed PSU, i.e., proposed HB LLC converter, can be de- CO S S is the output capacitance of the primary switches, and
signed to cover narrow link voltage range (375–400 V) because VLink-m ax and fS -L L C -M ax are the maximum link voltage and
the HBF converter can be in charge of wide link voltage range switching frequency, respectively. From (7), if tdead is 110 ns,
(250–380 V) during the hold-up time. In this part, two HB LLC CO S S is 125 pF, and fS -L L C -M ax is 110 kHz, maximum Lm can
converters are designed and compared considering their link be calculated as 480 μH. Thus, Lm can be chosen as 440 μH
voltage range. Moreover, the resonant inductor, resonant capac- with a margin in the proposed HB LLC converter. From Fig. 6,
itor, and resonant frequency were selected as 40 μH, 78 nF, and despite of a large Lm , the proposed maximum gain is sufficiently
90 kHz, respectively, considering the frequency variation and obtained at VLink = 375 V. As a result, the proposed HB LLC
voltage gain. converter can more reduce the primary conduction and switch
1) Transformer Turns-Ratio nL L C : The dc-conversion ratio turn-off losses compared to the conventional HB LLC converter
of the HB LLC converter ML L C can be expressed as follows: because it can be designed with a larger Lm [8]–[10].
(6) as shown at the bottom of the previous page, where k = 3) Transformer Core: In general, the transformer core can be
Lm /LR , Q = (LR /CR )0.5 , and nL L C , fR -L L C ,, and fS -L L C selected using the area product value, which is the product of the
are the transformer turns-ratio, resonant frequency, switching window area and effective cross-section area of the transformer
frequency of the HB LLC converter, respectively. From (6), core. Thus, the area product of the transformer AP -Trans can be
two features can be found. First, nL L C can be determined as 4 expressed as follows:
because the HB LLC converter is commonly designed to operate  
Lm iL m -m ax 1 2iD 1-rm s
near fR -L L C at the normal state. Second, ML L C is increased as AP -Trans = · iLR -rm s + (8)
fS -L L C is decreased so that lower fS -L L C is required to obtain Bm ax KU J nL L C
a higher voltage gain. where Bm ax-Trans is the maximum flux density, iLm -m ax is the
2) Transformer Magnetizing Inductance Lm : In the HB LLC maximum magnetizing current, iLR-rm s is the primary RMS
converter, the transformer magnetizing inductance Lm should current, iD 1-rm s is the secondary RMS current of D1 , KU is the
be designed as large as possible because a large Lm can reduce window utility factor, and J is the current density. Typically, as
the primary conduction and switch turn-off losses. However, the switching frequency fS -L L C is decreased from the resonant
from (6), a large Lm makes it difficult for the HB LLC converter frequency fR -L L C , the currents peak of the HB LLC converter
to achieve high voltage gain due to large k, as shown in Fig. 6. is also increased. Thus, iLm -m ax , iL R -rm s , and iD 1-rm s are max-
In this figure, the solid line is for a large Lm , and the dotted imized at its minimum link voltage, where is the design point of
line is for a small Lm . As seen in this figure, a large Lm cannot the transformer core [8], [9].
achieve conventional maximum gain at VLink-m in . Thus, Lm in Meanwhile, the conventional HB LLC converter has large
the conventional HB LLC converter should be smaller consider- iLm -m ax , iL R -rm s , and iD 1-rm s because its operating frequency
ing the peak voltage gain to cover wide link voltage range. With is very small at VLink-m in , as shown in Fig. 6. On the other hand,
a sufficient margin, Lm of the conventional HB LLC converter since the proposed HB LLC converter operates near resonant
can be selected as 180 μH. frequency at VLink = 375 V, it has small iLm -m ax , iL R -rm s ,
On the other hand, due to narrow link voltage range, Lm and iD 1-rm s . Thus, as shown in Table II, the proposed HB LLC
in the proposed HB LLC converter can be determined only converter has smaller area product than the conventional one.
7454 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 10, OCTOBER 2017

As a result, the proposed HB LLC converter can utilize smaller


transformer core (PQ2620) than conventional one (PQ2625),
which reduces the transformer core loss.
4) External Resonant Inductor Core: The external resonant
core can be also designed with the area product value like the
transformer core design, as follows:
LR iL R -m ax iL R -rm s
AP −L R = · (9)
Bm ax KU J
where AP -L R is the area product of the external resonant induc-
tor and iL R -m ax is the maximum primary current. From (9) and
Table II, the conventional HB LLC converter requires larger ex-
ternal core size (AP -L R = 3176 mm4 ) than the proposed HB
Fig. 7. DC-conversion ratio of HBF converter according to fS -fl y and n fl y .
LLC converter (AP -L R = 1114 mm4 ). Therefore, the proposed
converter can also reduce the core loss of the external inductor.

C. HBF Converter
The HBF converter shares the structure of the boost PFC
converter in the proposed PFC stage. Thus, the HBF converter
should not influence the design procedure of the boost PFC
converter. Above all, it has to regulate the output voltage with
designed parameters of the boost PFC converter. Therefore, for
utilizing the HBF converter effectively, the transformer turns
ratio nfly and switching frequency fS -fly of the HBF converter
should be designed considering following features: 1) the dc-
conversion ratio of the HBF converter, 2) the maximum current Fig. 8. Maximum current stresses of L B and D A according to n fl y .
stresses of LB and DA , and 3) the ZCS condition of DA .
1) DC-Conversion Ratio of HBF Converter: The dc-
conversion ratio of the HBF converter MH B F can be varied
by fS -fly or the duty cycle Dfly , which can be respectively ex-
pressed as follows:
VO
2
MH B F = = 1 + A(1 − 1/fn2 −fly )
VLink

2 −0.5
+ B 2 fn −fly − 1/fn −fly (10)

VO Dfly
MH B F = = (11)
VLink nfly
where A = LB -lkg /LB , B = π 2 IO ZR /[2(nfly )2 VO ], fn -fly Fig. 9. Switching frequency for ZCS operation of D A according to n fl y .
= fS -fly /fR -fly , and fR -fly is the resonant frequency of the HBF
converter. As can be seen in (10), the HBF converter is limited this figure, iL B -m ax is increased as nfly is decreased. Especially,
in obtaining a high voltage gain with frequency control because when nfly is smaller than 2.8, iL B -m ax of the HBF converter
A and B are already designed in the boost PFC converter. There- exceeds that of the boost PFC converter at the normal state.
fore, in the proposed PFC stage, the HBF converter should be Thus, it can cause the core saturation of the boost transformer.
designed with variable duty cycle and fixed switching frequency Above all, it has impact on the design procedure of the boost PFC
control based on (11). In this case, nfly should be designed to converter. On the other hand, as nfly is increased, since iD A -m ax
guarantee that MH B F is not to be sensitive to the switching is also increased, too large nfly can result in high current stress
frequency variation for achieving stable operation. Fig. 7 shows on DA . Therefore, medium nfly is appropriate to reduce the
MH B F according to fS -fly and nfly . As shown in this figure, current stresses of LB and DA .
when nfly becomes smaller, MH B F is more sensitive to fS -fly , 3) ZCS Condition of DA : The reverse recovery problem of
which means small variation of fS -fly can affect the operation DA can cause severe EMI noise and high voltage and cur-
of the HBF converter. As a result, a large nfly is recommended rent stresses on the PSU [18], [19]. Thus, to eliminate it, the
to achieve stable output voltage regulation of the HBF converter ZCS condition of DA should be considered. Based on (3),
near its switching frequency. Fig. 9 presents the switching frequency fS -fly to obtain the ZCS
2) Maximum Current Stresses of LB and DA : Using (1), (3), operation of DA according to nfly . From this figure, when nfly
and Table I, the maximum current stress of the boost inductor is smaller than 2.4, the ZCS operation of DA cannot be achieved
LB and secondary diode DA can be depicted in Fig. 8. From because fS -fly is larger than the resonant frequency fR -fly , i.e.,
BAEK et al.: BOOST PFC STAGE UTILIZED AS HALF-BRIDGE CONVERTER FOR HIGH-EFFICIENCY DC–DC STAGE IN POWER SUPPLY UNIT 7455

TABLE III
DESIGN PARAMETERS OF HB LLC CONVERTERS

Parameters Conventional Proposed

Primary switches, Q1 & Q2 IPA60R280E6


Secondary diodes, D1 & D2 STPS30150
Transformer Core: PQ2625, L m : Core: PQ2620,
180.41 μH, Ll k g : 3.87 μH, L m : 440 μH Ll k g : 4.05 μH,
N P :N S :N S = 24:6:6 N P :N S :NS = 24:6:6
External resonant inductor, Core: CM203060 Core: CM172026
Le x t Le x t : 35.18 μH Le x t : 35.51 μH
Resonant capacitor, C R 78 nF
Digital controller TMS320F28069

Fig. 12. Experimental waveforms under 10% load condition at normal state.
(a) Conventional HB LLC converter. (b) Proposed HB LLC converter.

secondary turns of the boost transformer N2 be chosen as nine


Fig. 10. Control block diagram of PSU with proposed PFC stage. turns. For this reason, the primary wire of the boost transformer
should be thinner than the wire of the conventional boost induc-
tor, which can lead to large wire resistance and conduction loss.
However, the increased conduction loss can be compensated by
QS in the proposed PFC stage.

IV. EXPERIMENTAL RESULTS


To confirm the validity of the proposed PFC stage, a 480-W
prototype PSU with the specifications of 180–264 Vrm s ac line
and 48 V/480 W output has been built and tested. For the com-
parison, the prototype of the conventional PSU is also imple-
mented. The designed parameters are presented in Tables I and
III, and MBRB40250T and IRFB4321 are used for the sec-
ondary diode DA and additional switch QA , respectively. Based
on Sections III-A and III-C, the proposed boost PFC converter
has the same parameters with the conventional boost PFC con-
verter except for the wire N1 of the boost transformer and boost
inductor: 1) the conventional boost PFC converter uses 0.1Φ ×
250 Litz wire and 2) the proposed one utilizes 0.1Φ × 100 Litz
wire due to the secondary turns of the boost transformer N2 .
Fig. 10 shows the control block diagram of the proposed PSU.
Fig. 11. Experimental waveforms under 100% load condition at normal state. From this figure, when the ac-Loss signal is low at the normal
(a) Conventional HB LLC converter. (b) Proposed HB LLC converter.
state, QB and QS are controlled by the PFC controller and QA
is turned OFF. Moreover, Q1 and Q2 are controlled by the LLC
above region operation. On the other hand, when nfly is larger controller. On the other hand, QB and QS are controlled by the
than 4.3, fS -fly becomes smaller than audible frequency, i.e., HBF controller and QA is turned ON when the ac-Loss signal
20 kHz. Therefore, to achieve the ZCS operation of DA , it is is high during the hold-up time
desirable that nfly is designed between 2.4 and 4.3. Figs. 11 and 12 show the experimental waveforms of the con-
In summary, based on Part C-1–C-3, too large nfly or too small ventional and proposed HB LLC converters under 100% and
nfly can cause susceptible dc-conversion ratio and large current 10% load conditions at the normal state, respectively. As shown
stresses of DA and LB . Thus, nfly is recommended between 2.8 in these figures, the proposed HB LLC converter has a smaller
and 3.5. In this example, nfly is selected as 3, which makes the magnetizing iLm and primary iL R currents compared to the
7456 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 10, OCTOBER 2017

Fig. 13. Experimental waveforms of HBF converter during hold-up time.


(a) Steady state. (b) Mode transition.

conventional HB LLC converter over the entire load conditions


due to its large magnetizing inductance. Thus, it is demon-
strated that a large magnetizing inductance reduces the primary
conduction and switch turn-off losses. Fig. 13(a) shows experi-
mental waveforms of the HBF converter in the proposed PSU at
the minimum link voltage (VLink = 250 V). From this figure,
the HBF converter achieves the ZCS operation of DA with de-
signed parameters. Finally, Fig. 13(b) shows the mode transient
waveforms of the proposed converter when the ac line is lost.
From this figure, the measured hold-up time is 19.74 ms, which
satisfies the hold-up time requirement.
Fig. 14 shows the measured efficiency of the conventional
and proposed PSUs in the normal state at 230 Vrm s where the
PSU usually operates. The efficiency was measured with two
power analyzers, i.e., Yokogawa WT3000 and WT1600, for in- Fig. 14. Measured efficiency in normal state at 230Vrm s . (a) Boost PFC
converter. (b) HB LLC Converter. (c) Overall efficiency of PSU.
put and output power measuring, respectively. From Fig. 14(a),
the proposed boost PFC converter has slightly higher efficiency
than the conventional one because the synchronous switch QS
reduces more conduction loss than the increased boost trans- V. CONCLUSION
former conduction loss. In case of the HB LLC converter, the In this paper, a boost PFC stage which can be deployed as a
proposed HB LLC converter exhibits considerably improved ef- HB converter is proposed to improve the efficiency of the HB
ficiency compared to the conventional one over the entire load LLC converter. The proposed PFC stage is simply derived by
conditions, as shown in Fig 14(b). This result is achieved by the replacing a boost diode and inductor with a switch and trans-
reduction of the core loss and primary conduction and switch former, respectively. During the hold-up time, the HB converter
turn-off losses. As a result, the proposed PSU obtains a higher can regulate the output voltage, and the HB LLC converter is
overall efficiency than the conventional PSU over the entire load turned off. Thus, the HB LLC converter can be designed with a
conditions, as shown in Fig. 14(c). large magnetizing inductance and narrow switching frequency
Meanwhile, since the proposed circuit employed additional variation, which enables it to achieve a high efficiency at the
diode DA and switch QA , the cost of the proposed circuit is normal state. Furthermore, because the proposed PFC stage can
increased. However, despite of the additional components, the apply various HB converters, it can also obtain a high com-
power density of the proposed circuit can be improved due to patibility. Therefore, the proposed method is expected to be
the reduced core size of the proposed HB LLC converter and the very attractive in PSUs, which should satisfy the hold-up time
improved overall efficiency. requirement.
BAEK et al.: BOOST PFC STAGE UTILIZED AS HALF-BRIDGE CONVERTER FOR HIGH-EFFICIENCY DC–DC STAGE IN POWER SUPPLY UNIT 7457

REFERENCES Jae-Il Baek (S’14) received the B.S. degree


in electronics and electrical engineering from
[1] Y J. P. Hong and G. W. Moon, “A digitally controlled soft valley change Sungkyunkwan University, Suwon, South Korea, in
technique for a flyback converter,” IEEE Trans. Ind. Electron., vol. 62. 2007, and the M.S. degree from the Department of
no. 2, pp. 966–971, Feb. 2015. Electrical Engineering from Korea Advanced Insti-
[2] “External AC-DC power supplies: Worldwide forecasts-tenth edition,” tute of Science and Technology (KAIST), Daejeon,
Dublin, Ireland, Apr. 2011. [Online]. Available: http://www.researchand South Korea, in 2015. He is currently working toward
markets.com/reports/1922132/acdc_power_supplies_worldwide_forecas the Ph.D. degree in KAIST.
ets_tenth#rela5 His research interests are in the areas of power
[3] H. Sarnago, O. Lucia, A. Mediano, and J. M. Burdio, “Design and im- electronics, particularly dc/dc converters, ac/dc con-
plementation of a high-efficiency multiple-output resonant converter for verters, LED driver, battery chargers, and digital con-
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[4] Limits for Harmonic Current Emissions (Equipment Input Current <16A
per Phase), IEC Int. Standard 1000-3-2, 2001. Jae-Kuk Kim (S’08–M’15) received the B.S. de-
[5] J. B. Lee, J. K. Kim, J. H. Kim, J. I. Baek, and G. W. Moon, “A high- gree in electrical engineering from Inha University,
efficiency PFM Half-bridge converter utilizing a half-bridge LLC con- Incheon, Korea, in 2004, and the M.S. and Ph.D.
verter under light load conditions,” IEEE Trans. Power Electron., vol. 30, degrees in electrical engineering from the Korea Ad-
no. 9, pp. 4931–4942, Sep. 2015. vanced Institute of Science and Technology, Daejeon,
[6] B. C. Kim, K. B. Park, and G. W. Moon, “Asymmetric PWM control South Korea, in 2007 and 2011, respectively.
scheme during hold-up time for LLC resonant converter,” IEEE Trans. From 2011 to 2015, he was a Senior Engineer in
Ind. Electron., vol. 59. no. 7, pp. 2992–2997, Jul. 2013. Samsung Electro-Mechanics, Suwon, Korea. He is
[7] I. H. Cho, Y. D. Kim, and G. W. Moon, “A half-bridge LLC reso- currently an Assistant Professor in the Department
nant converter adopting boost PWM control scheme for hold-up state of Electrical Engineering, Inha University. His re-
operation,” IEEE Trans. Power Electron., vol. 29, no. 2, pp. 841–850, search interests include converter topology design,
Feb. 2014. soft-switching technique, display driving system, server power system, and bat-
[8] H. Wu, T. Mu, X. Gao, and Y. Xing, “A secondary-side phase-shift- tery charger system.
controlled LLC resonant converter with reduced conduction loss at normal
operation for hold-up time compensation application,” IEEE Trans. Power Jae-Bum Lee (S’12) was born in Korea, in 1983.
Electron., vol. 30, no. 10, pp. 5352–5357, Oct. 2015. He received the B.S. degree in electrical engineering
[9] J. W. Kim and G. W. Moon, “A new LLC series resonant converter from Korea University, Seoul, Korea, in 2010, and
with a narrow switching frequency variation and reduced conduction the M.S. and Ph.D. degrees in electrical engineer-
losses,” IEEE Trans. Power Electron., vol. 29, no. 8, pp. 4278–4287, ing from the Korea Advanced Institute of Science
Aug. 2014. and Technology, Daejeon, South Korea, in 2012 and
[10] D. K. Kim, S. C. Moon, C. O. Yeon, and G. W. Moon, “High efficiency 2016, respectively.
LLC resonant converter with high voltage gain using auxiliary LC resonant He is currently a Researcher in Korea Railroad
circuit,” IEEE Trans. Power Electron., vol. 31, no. 10, pp. 6901–6909, Research Institute, Uiwang, South Korea. His main
Oct. 2016. research interests include high-voltage/power trans-
[11] J. I. Baek, J. K. Kim, J. B. Lee, H. S. Youn, B. G. Kang, and G. W. Moon, former design, high-efficiency AC/DC and DC/DC
“A new efficient hold-up time compensation method for high efficiency converters, and digital control method in high-power vehicles such as electric
DC-DC stage,” in Proc. IEEE 8th Int. Power Electron. Motion Control vehicles and rolling stock.
Conf., May 2016, pp. 2521–2526.
[12] J. Sun, “On the zero-crossing distortion in single-phase PFC con-
verters,” IEEE Trans. Power Electron., vol. 19, no. 3, pp. 685–692, Han-Shin Youn (S’14) received the B.S. degree
May 2004. in electrical engineering from Hanyang University,
[13] H. S. Youn, J. B. Lee, J. I. Baek, and G. W. Moon, “A digital phase Seoul, Korea, in 2009, and the M.S degree from
leading filter current compensation (PLFCC) technique for CCM boost the Department of Electrical Engineering from Ko-
PFC converter to improve PF in high line voltage and light load con- rea Advanced Institute of Science and Technology
dition,” IEEE Trans. Power Electron., vol. 31, no. 9, pp. 6596–6606, (KAIST), Daejoen, South Korea, in 2011. He is cur-
Sep. 2016. rently working toward the Ph.D. degree in KAIST.
[14] J. Yang, “Efficiency improvement with GaN-based SSFET as synchronous His main research interests include AC/DC con-
rectifier in PFC boost converter,” in Proc. Int. Exhib. Conf. Power verters, DC/DC converters, drive system, and digital
Electron., Intell. Motion, Renewable Energy Energy Manage. Europe, control method.
May 2014, pp. 1011–1016.
[15] T. M. Chen and C. L. Chen, “Analysis and design of asymmetrical half Gun-Woo Moon (S’92–M’00) received the M.S. and
bridge flyback converter,” IEE Elect. Power Appl., vol. 149, no. 6, pp. 433– Ph.D. degrees in electrical engineering from the Ko-
440, Nov. 2002. rea Advanced Institute of Science and Technology
[16] G. Y. Jeong, “High efficiency asymmetrical half-bridge flyback converter (KAIST), Daejeon, South Korea, in 1992 and 1996,
using a new voltage-driven synchronous rectifier,” IEEE Trans. IET Power respectively.
Electron., vol. 3, no. 1, pp. 18–32, Jan. 2010. He is currently a Professor in the Department of
[17] S. Abdel-Rahman, “CCM PFC Boost Converter Design (DN 2013-01),” Electrical Engineering, KAIST. His research inter-
Infineon Technologies North America, Jan. 2013. [Online]. Available: ests include modeling, design and control of power
http:www.infineon.com converters, soft-switching power converters, resonant
[18] D. Lu, D. K.-W. Cheng, and Y.-S. Lee, “A single-switch continuous- inverters, distributed power systems, power-factor
conduction-mode boost converter with reduced reverse-recovery and correction, electric drive systems, driver circuits of
switching losses,” IEEE Trans. Power Electron., vol. 50, no. 4, pp. 767– plasma display panels, and flexible ac transmission systems.
776, Aug. 2003. Dr. Moon is a Member of the Korean Institute of Power Electronics, Korean
[19] H. Wu, Y. Lu, T. Mu, and Y. Xing, “A family of soft-switching DC-DC Institute of Electrical Engineers, Korea Institute of Telematics and Electronics,
converters based on a phase-shift-controlled active boost rectifier,” IEEE Korea Institute of Illumination Electronics and Industrial Equipment, and Soci-
Trans. Power Electron., vol. 30, no. 2, pp. 657–667, Feb. 2015. ety for Information Display.

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