ANNA UNIVERSITY: CHENNAI – 600 025

B.E / B.Tech DEGREE PRACTICAL EXAMINATIONS, APRIL 2018

Regulations 2013

Sixth Semester

ELECTRONICS AND COMMUNICATION ENGINEERING

EC6612 – VLSI DESIGN Laboratory

Time: 3 Hours Maximum Marks: 100

Date:12.4.2018

1. i). Design full adder in gate level modeling and do the P&R Design for full adder. (50)
ii). Obtain the CMOS NAND LAYOUT and Calculate the power for CMOS NAND. (50)

2. Design and synthesize the parallel array multiplier and obtain the Simulation result and
Place and Route report. (100)

3. i). Design and synthesize the D flip flop and obtain the Simulation result and Place and
Route report. (50)
ii). Design and synthesize the Up-Down Counter and obtain the Simulation result and
Place and Route report. (50)

4. Design and synthesize the 8 bit Ripple Carry Adder by using Full- Adder and obtain the
Simulation result and Place and Route report. (100)

5. i). Design and synthesize the 4 bit Ripple Carry Adder by using Full- Adder and obtain
the Simulation result and Place and Route report. (50)
ii). Obtain the CMOS NOR LAYOUT and Calculate the power for CMOS NOR. (50)

6. i). Design basic gates in Gate level modeling and do the Place and Route Design for full
adder. (50)
ii). Obtain the LAYOUT for Differential Amplifier and Calculate the power also. (50)
 7. Design and synthesize the State Machine and obtain the Simulation result and Place and
Route report. (100)

8. i). Design and synthesize the Up-Down Counter and obtain the Simulation result and Place
and Route report. (50)
ii). Obtain the CMOS NOR LAYOUT and Calculate the power for CMOS NOR. (50)

9. i).Design and synthesize the D flip flop and obtain the Simulation result and Place and
Route report. (50)
ii). Obtain the LAYOUT for Differential Amplifier and Calculate the power for Differential
Amplifier Gate. (50)

10. i). Design full adder in Behavioral level modeling and do the Place and Route Design for
full adder. (50)
ii). Obtain the LAYOUT for CMOS Inverter and Calculate the power for CMOS
Inverter. (50)

11. i). Design full adder in Data flow modeling and do the Place and Route Design for full
adder. (50)
ii). Obtain the LAYOUT for Differential Amplifier and Calculate the power for
Differential Amplifier. (50)

12. i). Design and synthesize the Up-Down Counter and obtain the Simulation result and Place
and Route report. (50)
ii). Obtain the CMOS NAND LAYOUT and Calculate the power for CMOS NAND. (50)

13. i). Design and synthesize the 4 bit Ripple Carry Adder by using Full- Adder and obtain
the Simulation result and Place and Route report. (50)
ii). Obtain the CMOS NAND LAYOUT and Calculate the power for CMOS NAND. (50)

14. i). Design full adder in gate level modeling and do the P&R Design for full adder. (50)
ii). Obtain the LAYOUT for Differential Amplifier and Calculate the power for
Differential Amplifier. (50)
 15. Obtain the LAYOUT for Differential Amplifier, CMOS NAND and CMOS NOR and
Calculate the power also. (50)

16. i). Design basic gates in Data flow modeling and do the Place and Route Design for full
adder. (50)
ii). Obtain the LAYOUT for CMOS NAND and CMOS NOR and Calculate the power
also. (50)

17. i).Design and synthesize the D flip flop and obtain the Simulation result and Place and
Route report. (50)
ii). Obtain the LAYOUT for CMOS NOR and Calculate the power for CMOS NOR Gate.(50)

18. i). Obtain the CMOS NOR LAYOUT and Calculate the power for CMOS NOR. (50)
ii). Design full adder in gate level modeling and do the P&R Design for full adder. (50)

19. i).Obtain the LAYOUT for Differential Amplifier and Calculate the power for
Differential Amplifier. (50)
ii). Design full adder in Behavioral level modeling and do the Place and Route Design for
full adder. (50)

20. i). Design and synthesize the 4 bit Ripple Carry Adder by using Full- Adder and obtain the
Simulation result and Place and Route report. (50)
ii). Obtain the LAYOUT for Differential Amplifier and Calculate the power for Differential
Amplifier. (50)

21. i). Design and synthesize the Up-Down Counter and obtain the Simulation result and Place
and Route report. (50)
ii). Obtain the Differential Amplifier LAYOUT and Calculate the power for Differential
Amplifier. (50)

22. i). Design and synthesize the 4 bit Ripple Carry Adder by using Full- Adder and obtain the
Simulation result and Place and Route report. (50)
ii). Obtain the LAYOUT for CMOS inverter and Calculate the power for CMOS Inverter. (50)
23. i). Obtain the LAYOUT for CMOS NAND and Calculate the power for CMOS NAND
Gate. (50)
ii). Design full adder in Behavioral level modeling and do the Place and Route Design for
full adder. (50)

24. i).Design and synthesize the D flip flop and obtain the Simulation result and Place and
Route report. (50)
ii). Obtain the LAYOUT for CMOS NAND gate and Calculate the power for CMOS NAND
Gate. (50)

25. i). Design basic gates in Data flow modeling and do the Place and Route Design for full
adder. (50)
ii). Obtain the LAYOUT for Differential Amplifier and Calculate the power also. (50)

INTERNAL EXAMINER EXTERNAL EXAMINER