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Kuruvilla Varghese
DESE
Indian Institute of Science
Kuruvilla Varghese
Introduction / Features 2
1
Schematic 3
source: linuxtoys.org
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VHDL Features 4
b(3)
a
a(2)
b = equals b(2)
equals
a(1)
b(1)
a(0)
b(0)
Function
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2
Equality Comparator 5
-- 4 bit equality comparator bit - ‘0’, ‘1’
library ieee;
std_logic – ‘0’, ‘1’, ‘Z’, …
use ieee.std_logic_1164.all;
in out
entity eqcomp is
port (a, b: in std_logic_vector(3 downto 0);
equals: out std_logic); inout
buffer
end eqcomp;
Kuruvilla Varghese
Equality Comparator 6
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3
Syntax, Operators 7
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Operators 8
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4
Operators 9
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Operators 10
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5
Operators - precedence 11
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6
Design Flow - Tools 13
• VHDL Editor
• Synthesis Tool
• Constraint Editor
• Place and Route (PAR) / Fitting
Tool
• VHDL Simulator
– Functional/Behavioral simulation
– Logic Simulation
– Timing Simulation
• Static Timing Analysis Tool
• Programmer
Kuruvilla Varghese