INSTITUTE OF AERONAUTICAL ENGINEERING

(Autonomous)
Dundigal, Hyderabad - 500 043

ELECTRONICS AND COMMUNICATION ENGINEERING

COURSE INFORMATION SHEET

Course Title DIGITAL IC APPLICATIONS USING VHDL

Course Code AEC516
Programme B.Tech
Semester V
Course type ELECTIVE
Regulation IARE-R16
Course Structure Lectures Tutorials Practicals Credits
3 - - 3
Course Coordinator Dr. Vijay Vallabhuni, Professor, Department of ECE
Course Faculty Dr. K Nehru, Professor, Department of ECE
Mr. D KhalandarBasha, Assistant Professor, Department of ECE

I. COURSE OVERVIEW
In this course students will learn digital system fundamental applications. Topics include: logic gates; logic
system design using gate combinations and VHDL (Very High Speed Integrated Circuit Hardware
Description Language); Combinational Circuits; flip-flop theory; shift register theory; counter theory;
VHDL for combinational and sequential circuits. This course is intended to describe the memories like
SRAM and DRAM cells and their opertions along with their timing diagrams.

II. COURSE PRE-REQUISITES

Level Course Code Semester Prerequisites Credits

UG AEC002 III Digital System Design 4
UG AEC103 IV Digital System Design Laboratory 2

III. MARKS DISTRIBUTION

Subject SEE Examination CIA Examination Total

Marks
Digital IC applications 70 Marks 30 Marks 100
using VHDL Marks

Semester End Examination (SEE)

The SEE is conducted for 70 marks of 3 hours duration. The syllabus for the theory courses is divided into
FIVE units and each unit carries equal weightage in terms of marks distribution. The question paper pattern
is as follows: two full questions with „either‟ „or‟ choice will be drawn from each unit. Each question
carries 14 marks.

Continuous Internal Assessment (CIA)

CIA is conducted for a total of 30 marks, with 25 marks for Continuous Internal Examination (CIE) and 05
marks for Quiz / Alternative Assessment Tool (AAT).

Continuous Internal Examination (CIE)

The CIE exam is conducted for 25 marks of 2 hours duration consisting of two parts. Part–A shall have five
compulsory questions of one mark each. In part–B, four out of five questions have to be answered where,
each question carries 5 marks. Marks are awarded by taking average of marks scored in two CIE exams.
.
 Quiz / Alternative Assessment Tool (AAT)
Two Quiz exams shall be online examination consisting of 20 multiple choice questions and are be answered
by choosing the correct answer from a given set of choices (commonly four). Marks shall be awarded
considering the average of two quizzes for every course. The AAT may include seminars, assignments, term
paper, open ended experiments, microprojects, five minutes video and MOOCs.

IV. DELIVERY / INSTRUCTIONAL METHODOLOGIES:

 CHALK & TALK  QUIZ  ASSIGNMENTS  MOOCs

 LCD / PPT  SEMINARS  MINI PROJECT  VIDEOS
 OPEN ENDED EXPERIMENTS

V. ASSESSMENT METHODOLOGIES–DIRECT:

 CIE EXAMS  SEE EXAMS  ASSIGNEMNTS  SEMINARS

LABORATORY STUDENT
X X  MINI PROJECT X CERTIFICATION
PRACTICES VIVA

 TERM PAPER

VI. ASSESSMENT METHODOLOGIES–INDIRECT

ASSESSMENT OF COURSE STUDENT FEEDBACK ON FACULTY

 OUTCOMES (BY FEEDBACK, ONCE)  (TWICE)
 ASSESSMENT OF MINI PROJECTS BY EXPERTS

VII. COURSE OBJECTIVES

The course should enable the students to:

I. Familiarization of Digital Logic families.

II. Design of combinational circuits using digital ICs.
III. Design of sequential circuits using digital ICs.
IV. Strategy of digital circuits using VHDL Programming
V. Acquire knowledge of memories like SRAM, DRAM memories construction, operation and timing
diagrams.

VIII. COURSE LEARNING OUTCOMES

Students, who complete the course, will have demonstrated the ability to do the following
S. No Description
CAEC516.01 Understand logic families of CMOS, TTL and ECL
Construct the circuits of CMOS basic gates like inverter, NAND, NOR, AOI and OAI logic
CAEC516.02
with functionality verification.
Construct the circuits of TTL logic family by understanding NAND, NOR gates with
CAEC516.03
functionality verification.
Identify the need of interfacing CMOS logic family with TTL logic family and interfacing
CAEC516.04
TTL with CMOS logic.
CAEC516.05 Understand the Static and dynamic electrical behavior of CMOS circuits.
CAEC516.06 Understand the different design methods in VHDL.
CAEC516.07 Acquire the basic constucts in VHDL programming.
CAEC516.08 Understand the terms simulation and synthesis in the area of VLSI.
Familarization of basic combinational circuits viz decoders, encoders, multiplexers,
CAEC516.09
demultiplexers, parity circuits.
CAEC516.10 Familarization of basic arithmetic circuits for addition, subtraction and multiplication.
CAEC516.11 Distinguish between combinatorial and sequential circuits.
CAEC516.12 Design sequential circuits like latches, flip-flops.
CAEC516.13 Design sequential circuits like shift registers and counters.
CAEC516.14 Understand synchronous design methodology in combinational and sequencetial circuits.
CAEC516.15 Learns impediments to synchronous design in digital memory circuits.
 CAEC516.16 Learn the internal structure of SRAM and decoding mechanism.
CAEC516.17 Analyze timing diagrams of SRAM for read and write operations
CAEC516.18 Understand the importance and also internal structure of DRAM
CAEC516.19 Analyze timing diagrams of DRAM for read and write operations

IX. HOW PROGRAME OUTCOMES AREASSESSED

Proficiency
Program Outcomes Level
assessed by
PO1 Engineering knowledge: Apply the knowledge of
mathematics, science, engineering fundamentals, and an
S Assignments.
engineering specialization to the solution of complex
engineering problems.
PO2 Problem analysis: Identify, formulate, review research
literature, and analyze complex engineering problems
H Design
reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
PO3 Design/development of solutions: Design solutions for
complex engineering problems and design system
components or processes that meet the specified needs with S
Mini Project
appropriate consideration for the public health and safety,
and the cultural, societal, and environmental considerations.
PO4 Conduct investigations of complex problems: Use research-
based knowledge and research methods including design of
Open ended
experiments, analysis and interpretation of data, and synthesis S
experiments
of the information to providevalid
conclusions.
PO5 Modern tool usage: Create, select, and apply appropriate
techniques, resources, and modern engineering and IT tools
S Mini Project
including prediction and modeling to complex engineering
activities with an understanding of the limitations.
PO6 The engineer and society: Apply reasoning informed by the
contextual knowledge to assess societal, health, safety, legal
N
and cultural issues and the consequent responsibilities --
relevant to the professional engineering practice.
PO7 Environment and sustainability: Understand the impact of
the professional engineering solutions in societal and
N
environmental contexts, and demonstrate the knowledge of, --
and need for sustainable development.
PO8 Ethics: Apply ethical principles and commit to professional
ethics and responsibilities and norms of the engineering N
--
practice.
PO9 Individual and team work: Function effectively as an
individual, and as a member or leader in diverse teams, and S Project Work
in multidisciplinary settings.
PO10 Communication: Communicate effectively on complex
engineering activities with the engineering community and
with society at large, such as, being able to comprehend and
N
write effective reports and design documentation, make
Seminars
effective presentations, and give and receive clear
instructions.
PO11 Project management and finance: Demonstrate knowledge
and understanding of the engineering and management
principles and apply these to one‟s own work, as a member N
--
and leader in a team, to manage projects and in
multidisciplinary environments.
PO12 Life-long learning: Recognize the need for, and have the
preparation and ability to engage in independent and life- S --
long learning in the broadest context of technological change.

N= None S – Supportive H - Highly Related

X. HOW PROGRAM SPECIFIC OUTCOMES ARE ASSESSED

Proficiency
Program Specific Outcomes Level Assessed
by
PSO 1 Professional Skills: An ability to understand the basic concepts
in Electronics & Communication Engineering and to apply them
Lectures and
to various areas, like Electronics, Communications, Signal S
Assignments
processing, VLSI, Embedded systems etc., in the design and
implementation of complex systems.
PSO 2 Problem-Solving Skills: An ability to solve complex
Electronics and communication Engineering problems, using
S Tutorials
latest hardware and software tools, along with analytical skills
to arrive cost effective and appropriate solutions.
PSO 3 Successful Career and Entrepreneurship: An understanding
of social-awareness & environmental-wisdom along with ethical
responsibility to have a successful career and to sustain passion S Guest lectures
and zeal for real-world applications using optimal resources as
an Entrepreneur.

N= None S – Supportive H - Highly Related

XI. SYLLABUS:

UNIT – I : CMOS LOGIC AND BIPOLAR LOGIC AND INTERFACING

Introduction to logic families, CMOS logic, CMOS steady state electrical behavior, CMOSdynamic electrical
behavior, CMOS logic families; Bipolar logic, transistor logic, TTL families, CMOS/TTL interfacing, low
voltage CMOS logic and interfacing, emitter coupled logic, comparison of logic families, familiarity with
standard 74XX and CMOS 40XX series-ICs – specifications.
UNIT – II :THE VHDL HDL AND ITS ELEMENTS
Design flow, program structure, types and constants, functions and procedures, libraries and packages; The
VHDL design elements: Structural design elements, data flow design elements, behavioral design elements,
time dimension and simulation synthesis.
UNIT – III :COMBINATIONAL LOGIC DESIGN USING VHDL
Decoders, encoders, three state devices, multiplexers and demultiplexers, Code Converters, EX-OR gates and
parity circuits, comparators, adders and subtractors, ALUs, combinational multipliers. VHDL modes for the
above ICs. Design examples (using VHDL) - Barrel shifter, comparators, floating-point encoder, dual parity
encoder
UNIT – IV :SEQUENTIAL LOGIC DESIGN
Latches and flip-flops, PLDs, counters, shift register, and their VHDL models, synchronous design
methodology, impediments to synchronous design.
UNIT – V :MEMORIES
ROMs: Internal structure, 2D-decoding commercial types, timing and applications; Static RAM: Internal
structure, SRAM timing, standard SRAMS, synchronous SRAMS; Dynamic RAM: Internal structure, timing,
synchronous DRAMs; Familiarity with component data sheets : Cypress CY6116, CY7C1006, specifications.

TEXTBOOKS:
1 John F.Wakerly, “Digital Design Principles & Practices”, 3rd Edition, 2005, PHI/ Pearson Education
Asia,
2 J. Bhasker, “VHDL Primer”, Pearson Education / PHI, 3rd Edition. Pearson Higher Education

REFERENCES:

1 Charles H. Roth Jr., “Digital System Design Using VHDL”, PWS Publications, 1998.
2 Alan B. Marcovitz, “Introduction to Logic Design”, TMH, 2nd Edition, 2005.
 3 Stephen Brown, ZvonkoVransesic, “Fundamentals of Digital Logic with Verilog Design”, TMH, 2003.
4 Cypress Semiconductors Data Book (Download from website).
5 K. Lalkishore, “Linear Integrated Circuit Applications”, Pearson Educations 2005.

XII. COURSE PLAN

At the end of the course, the students are able to achieve the following course learning outcomes:

Lecture
Topic Outcomes Topics to be covered Reference
No.
1. Understand thelogic family, Introduction to Logic Family, MOS transistor T1: 3.3
Operation of MOS transistor operation
2. Understand the functioning of CMOS logic and voltage levels, CMOS T1: 3.3
CMOS inverter Inverter
3. Design and analyze CMOS NAND CMOS NAND and NOR gates T1: 3.3.4
and NOR gates
4. Design and analyze CMOS AOI and CMOS AOI, OAI logic T1: 3.3.7
OAI gates
5. Design and analyze CMOS AND CMOS AND & OR gates T1: 3.3.7
andOR gates
6. Design and analyze CMOS XOR and CMOS XOR and XNOR gates T1: 3.3.7
XNOR gates
7. Understand the characteristics of CMOS steady state electrical behavior, CMOS T1: 3.4
CMOS circuit dynamic Electrical behavior
8. Familiar about various CMOS logic CMOS logic families, Diode Logic T1: 3.8-3.9
families
9. Design and analyze TTL NAND gates TTL NAND Gate T1: 3.10

10. Design and analyze TTL NOR gates TTL NOR Gate, CMOS/TTL interfacing, Low T1: 3.10. 3.12
voltage CMOS logic and interfacing
11. Understand ECL logic, comparision Emitter Coupled Logic, Comparison of logic T1:3.14
of logic families families, Familiarity withstandard 74XX and
CMOS 40XX series-ICs – Specifications.
12. Understand the design flow of Design flow, Program structure, types and R5: 8.5-8.6
VHDL constants
13. Understand functions, procedures, Functions and Procedures, R5: 8.5-8.6
libraries and packages Libraries and packages
14. Understand structural design Structural design elements with example T1: 6.1-6.2
elements
15. Understand dataflow design elements Data flow design elements with example T1: 6.1-6.2
16. Understand behavioural design Behavioral design elements with example T1: 6.3
elements
17. Understand time dimension, Time dimension and simulation synthesis T1: 6.3
simulation and synthesis
18. Design and implementation of 74x139 Decoder and VHDL model T1: 5.4.3
decoder
19. Design and implementation of 74x138 Decoder and VHDL model T1: 5.4.4
decoder
20. Design and implementation of 74x148 encoders and VHDL model T1: 5.5.2
encoder
21. Design and implementation of three Three state devices and VHDL model T1: 5.6
state devices
22. Design and implementation of Multiplexers and VHDL model T1: 5.7
multiplexers
23. Design and implementation of Multiplexers and VHDL model T1: 5.7
multiplexer
24. Design and implementation of Demultiplexers and VHDL model T1: 5.7
demultiplexer
 25. Design and implementation of code Code Converters and VHDL model T1: 5.7
converters
26. Design and implementation of parity EX-OR gates and parity circuits, comparators T1: 5.8, 5.9
circuits and comparators and VHDL model
27. Design and implementation of adders HA, FA adders and FA using HA and VHDL T1:5.10
model
28. Design and implementation of CLA CLA adder and VHDL model T1: 5.10
adder
29. Design and implementation of Subtractors, FS using FA and VHDL model, T1: 5.10
subtractors ALUs and VHDL model
30. Design and implementation of Combinational multipliers T1: 5.11
multiplier
31. Design and implementation of Combinational multipliers VHDL model T1: 5.11
multiplier
32. Design and implementation of barrel Barrel shifter T1: 6.1.1
shifter
33. Design and implementation of barrel Barrel shifter VHDL model T1: 5.1.2
shifter
34. Design and implementation of Comparators, floating-point encoder and T1: 5.1.3
comparators, encoders VHDL model
35. Design and implementation of dula Dual parity encoder and VHDL model T1: 5.13
parity encoder
36. Design and implementation of Latches & flip-flops and VHDL model T1: 7.2
latches and flipflops
37. Realize Flip flops from latches Realization of Lathes and Flip Flops, PLD and T1: 7.2
VHDL model
38. Design and implementation of Synchronous counters and VHDL model T1: 8.4
counters
39. Design and implementation of Asynchronous counters and VHDL model T1: 8.4
counters
40. Design and implementation of Shift register and VHDL model T1:8.5
registers
41. Understand synchrounous design Synchronous design methodology. T1:8.7-8.8
methodology Impediments to synchronous design
42. Understand ROMs structure ROMs Internal structure T1:8.6
43. Understand 2D decoding mechanism 2D-decoding ROMs, Commercial types, T1: 8.2
in RAMs timing and applications R5: 4.4
44. Understand static RAM internal Static RAM internal structure, T1: 8.2
structure R5: 4.4
45. Understand SRAM timing diagram SRAM timing Standard SRAMS, synchronous T1: 8.9
SRAMS R6: 4.5
46. Understand DRAM internal structure Dynamic RAM internal structure T1: 8.12-8.13
47. Understand DRAM timing diagram DRAM timing T1: 10.6
48. Familiar about Cypress devices Synchronous DRAMs Familiarity with T1: 10.4
Component Data Sheets –Cypress CY6116,
CY7C1006, Specifications

XIII.GAPS IN THE SYLLABUS - TO MEET INDUSTRY / PROFESSIONAL REQUIREMENTS:

Relevance With Relevance With

S No Description Proposed Actions PSOs
POs
1 Design of Laboratory Practices, PO 1, PO 2, PO 3 PSO 1
combinational Project/ NPTEL
applications
2 Design of sequential Laboratory Practices, PO 2,PO 3, PO 5 PSO 1
applications Project
3 Design of memories Seminars/ NPTEL PO 1, PO 3 PSO 1
XIV. MAPPING COURSE OBJECTIVES LEADING TO THE ACHIEVEMENT OF
PROGRAM OUTCOMES AND PROGRAM SPECIFIC OUTCOMES

Course Program Out Comes Program Specific

Objectives Outcomes
PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO PSO
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
1 H S S H S S
2 S S H S S
3 H S S S S S
4 H H S S S
S – Supportive H - Highly Related

XV. MAPPING COURSE LEARNING OUTCOMES LEADING TO THE ACHIEVEMENT OF

PROGRAM OUTCOMES AND PROGRAM SPECIFIC OUTCOMES

Course Program Outcomes Program Specific

Learning Outcomes
Outcomes PO PO PO PO PO PO PO PO PO PO PO PO PSO PSO PSO
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
CAEC001.01 S S S S
CAEC001.02 S S S S S H
CAEC001.03 H H S S S
CAEC001.04 H H H S S S
CAEC001.05 H H S H S
CAEC001.06 H H H S H
CAEC001.07 S S H S S S S
CAEC001.08 S S H S S S
CAEC001.09 H H S S
CAEC001.10 H H H S S S
CAEC001.11 H H S H H
CAEC001.12 H H H S S
CAEC001.13 S S H S S S S
CAEC001.14 S S S
CAEC001.15 S S S
CAEC001.16 S S S S
CAEC001.17 S S S
CAEC002.18 S S H S S S S
CAEC002.19 H H H S H H S

S – Supportive H - Highly Related

XVI. DESIGN BASED PROBLEMS (DP) / OPEN ENDED PROBLEM

1. Design and analyzes different troplogiesof combinational circuits for better performance in terms of
power and delay.
2. Design sequential application using melay machine.
3. Design sequential application using moore machine.
4. Design a memory blocks with various archetectures.
Prepared by:
Dr. Vijay Vallabhuni, Professor,Department of ECE
Dr. K Nehru, Professor, Department of ECE
Mr. D KhalandarBasha, Assistant Professor, Department of ECE

HOD, ELECTRONICS AND COMMUNICATION ENGINEERING