Ele863 Lab Manual

EE8503/ELE863
VLSI Circuits and Systems for Data

Communications
Laboratory Project Manual

ver. 2016
F. Yuan, PhD, PEng.

Department of Electrical and Computer Engineering
Ryerson University
Toronto, ON, Canada
Copyright Fei
c Yuan 2016
Preface
This laboratory design manual is an essential component of graduate

course EE8503 and undergraduate course ELE863 VLSI Circuits and Systems
for Data Communications offered by the Department of Electrical and Com-
puter Engineering at Ryerson University, Toronto, ON, Canada. It deals with
the design of a 1 Gbps serial link with pre-emphasis and post-equalization.
The laboratory design manual consists of the following 7 laboratory projects
:
• Laboratory Project 1 : Wire channels (5%).
• Laboratory Project 2 : Continuous-time linear equalizers (5%).
• Laboratory Project 3 : Phase-locked loops (5%).
• Laboratory Project 4 : Pre-emphsis (5%).
• Laboratory Project 5 : Decision feedback equalizers (5%).
• Laboratory Project 6 : Clock and data recovery (5%).
• Laboratory Project 7 : Adaptive decision feedback equalizers (5%).
Laboratory 7 is mandatory for graduate students. It is optional for un-

dergraduate students.
Each design laboratory provides a brief background information of the
systems to be designed. In addition, it describes the detailed laboratory
work and analyses to be completed. The requirements of the laboratory
report and the grading scheme of each design laboratory are given explicitly.
Each design laboratory must be completed individually. No group work
is allowed.
Professor Fei Yuan

Jan. 2016
1
Contents
1 Wire Channels 5
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 PRBS Generator . . . . . . . . . . . . . . . . . . . . . 6
2.2 Current-Mode Driver . . . . . . . . . . . . . . . . . . . 6
2.3 Wire Channel . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Laboratory Report . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Continuous-Time Linear Equalizers 10

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.1 Serial Link with CTLE . . . . . . . . . . . . . . . . . . 12
2.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Phase-Locked Loops 16
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.1 Voltage-Controlled Ring Oscillators . . . . . . . . . . . 16
1.2 Bang-Bang Phase Detector . . . . . . . . . . . . . . . . 19
1.3 Phase-Locked Loop . . . . . . . . . . . . . . . . . . . . 22
2 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.1 Charge Pumps . . . . . . . . . . . . . . . . . . . . . . 23
2
2.2 Loop Filters . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3 Open-Loop Test of PLL . . . . . . . . . . . . . . . . . 24
2.4 Closed-Loop Test of PLL . . . . . . . . . . . . . . . . . 25
4 Pre-Emphasis 29
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.1 Unit Delay Cells . . . . . . . . . . . . . . . . . . . . . 30
1.2 Pre-Emphasis Tap Multiplier . . . . . . . . . . . . . . 30
1.3 Summer/Driver . . . . . . . . . . . . . . . . . . . . . . 31
2 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.1 Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2 Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . 32
2.3 Power Consumption . . . . . . . . . . . . . . . . . . . 32
5 Decision Feedback Equalizers 35

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.1 Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.2 Unit Delay Cells . . . . . . . . . . . . . . . . . . . . . 36
1.3 Tap Multiplier . . . . . . . . . . . . . . . . . . . . . . . 37
1.4 Summer . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.1 Serial Link . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.2 Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . 39
6 Clock and Data Recovery 42

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 43
3
4
7 Adaptive Decision Feedback Equalizers 46

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2 Laboratory Work . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.1 Serial Link with Adaptive DFE . . . . . . . . . . . . . 48
2.2 Adaptation . . . . . . . . . . . . . . . . . . . . . . . . 49
2.3 Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . 49
Chapter 1
Wire Channels
1 Introduction
Wire channels over which data are transmitted include printed-circuit-board
(PCB) traces, interconnects, vias, connectors, etc. Due to resistive, capaci-
tive and inductive losses at high frequencies1 , wire channels suffer from finite
bandwidth, which is the main cause of inter-symbol interference (ISI). In this
laboratory, you will study the characteristics of wire channels in both time
and frequency domains. You will design a 1 Gbps serial link consisting of a
pseudo-random bit sequence (PRBS) generator, a current-mode transmitter,
a wire channel modeled as a transmission line, and termination resistors.
1
Resistive loss also known as ohmic loss is due to skin effect and proximity effect of
conductors at high frequencies. Capacitive loss also known as dielectric loss arises from
the shunt capacitance between channels and ground planes/substrates. Inductive loss is
caused by the inductance of channels.
5
CHAPTER 1. WIRE CHANNELS 6
2 Laboratory Work
2.1 PRBS Generator
The PRBS generator used in this laboratory is a behavioral functional block
coded in Verilog. It outputs a pseudo-random bit-sequence. It is located in
the library called ahdlLib, cell rand-bit-stream.
2.2 Current-Mode Driver

Fig. 1.1 shows the schematic of a widely used current-mode transmitter. The
PRBS generator outputs a pseudo-random bit sequence. The cross-coupled
NAND2 gates generate a pair of complimentary output bits D and D2 The
driver is a current-steering cell with a constant tail current 4 mA. The tail
current is steered completely between the two branches of the cell by D and
D. The use of current-steering driver provides the following attractive advan-
tages : (i) Because the current drawn from VDD rail and that injected into VSS
rail are constant, the switching noise generated by the driver is minimized.
(ii) The current conveyed to the channel is constant during each symbol time,
minimizing interference with neighboring devices. (iii) Although the current-
steering driver consumes static power quantified by Ps = Itail VDD , at Gbps
data rates, this static power consumption is significantly lower as compared
with the dynamic power consumed by inverter-based voltage-mode drivers,
2
which is quantified by Pd = CVDD f where f is the frequency.
2.3 Wire Channel

There are a number of ways to model wire channels, depending upon the
requirements. The simplest model of wire channels is RC networks with
2
The use of cross-coupled NAND2 gates to generate complimentary outputs is critical
as it ensures that D and D are completely complimentary. If only an inverter is used to
generate D from D, D and D will not be completely non-overlapping.
Figure 1.1: Transmitter and wire channel.
various configurations such as π-network or T-network3 .

Wire channels can also be modeled using micro-strip T-line model avail-
able in library analogLib, cell mtline.
2.4 Analysis
The following analyses are to be performed :
1. Time-domain response of the channel : Replace the PRBS gen-

erator with a pulse generator with pulse width 1 ns, pulse amplitude
1.2V and period 20 ns. Plot the time-domain response vo (t) of the chan-
nel for three difference lengths of the channel (10 cm, 50 cm, and 100
cm). Measure the pre-cursors, main cursor, and post-cursors of vo (t) in
each case. Save all plots and measurement results for laboratory report.
2. Frequency-domain response of the channel : Terminate the T-

line cell with 2 50Ω resistors (due to differential configuration) and
apply a differential voltage source to the input of the channel. Perform
AC analysis by sweeping the frequency of the input and record the
3
For details on these, see text J. Rabaey, Digital Integrated Circuits - A Design Per-
spective, Prentice-Hall, 1996. 2nd edition is also available.
voltage across the termination resistors.
3. Eye diagram of the response of the channel : Activate the PRBS

generator. The output bit stream of the PRBS generator should be of
swing 0-1.2V and duration 1 ns (1 Gbps). Plot the eye diagram of the
time-domain response vo (t) of the channel for three difference lengths
of the channel (10 cm, 50 cm, and 100 cm). Measure the vertical and
horizontal openings of data eyes. Measure peak-to-peak jitter at the
zero-crossing of data eyes. Save all results for laboratory report.
3 Laboratory Report
Laboratory reports must be prepared in either Microsoft Word, LaTeX, or
other text editors. Figures, tables, and expressions should be embedded
in the main body of reports. All expressions, figures, and tables must be
numbered. All figures and tables must be captioned. Cadence print-outs
attached to the end of laboratory reports are not acceptable. Hand-
written laboratory reports will be rejected. Laboratory reports must
contain the followings :
1. Front matter (10%) :
• A cover page containing the name and student identification num-

ber
• Table of contents
• List of figures
• List of tables
2. Main body (80%):
• The schematic of the entire design (10%)

• Tabulate the dimension of all transistors, the parameters of the

channel, the parameters of independent sources, and the parame-
ters of any other block of your design (20%).
• Time-domain response of the channel for 3 different channel lengths.
Tabulate the measured pre-cursors, main cursor, and post-cursors
of the response of the channel for each channel length (20%).
• Frequency-domain response of the channel for 3 different channel
lengths. Tabulate the measured bandwidth of the channel for each
channel length (20%).
• Eye diagram of the channel for 3 different channel lengths. Tab-
ulate the measured vertical and horizontal openings of data eyes,
and peak-to-peak timing jitter at the zero-crossing of data eyes
for each channel length (20%).
3. Conclusions (10%)
Provide no less than three (3) but no more than five (5) conclusions
that you can draw from this design laboratory. Your conclusions must
be supported by the simulation results obtained and must be as specific
and precise as possible.
Chapter 2
Continuous-Time Linear
Equalizers
1 Introduction
It was observed in Laboratory 1 that the longer the channel, the severer the
attenuation of the signal traveling along the channel. One effective way to
compensate for the loss of the channel is to boost the received signal at the
receiving end using an amplifier. In order to cope with the timing constraint
of multiple Gbps data rates, the amplifier must have a large bandwidth.
Since the effect of the finite bandwidth of the channel is the attenuation
of the high-frequency components of the transmitted signal (Note that the
transmitted signal is broadband and contains both low and high-frequency
components) while having no effect on the low-frequency components of the
transmitted signal, the amplifier should therefore behave in such a way that
it provides a small voltage gain at low frequencies and a large voltage gain
at high frequencies, typically at the baud-rate frequency of the transmitted
signal. Although it seems that the larger the voltage gain of the amplifier,
the better the compensation, a large voltage gain at high frequencies will
also deteriorate crosstalk, which typically intensifies at high frequencies. At
a result, only a moderate gain at high frequencies should be provided by the
10
CHAPTER 2. CONTINUOUS-TIME LINEAR EQUALIZERS 11
amplifier. To achieve both a moderate gain at high frequencies and a small

gain at low frequencies, source degeneration with a resistor in parallel with a
+ −
capacitor, as shown in Fig.2.1, is widely used. Since vin and vin are typically
very small due to the loss of the channel, the NMOS transistors are operated
in saturation. The DC bias of the transistors are provided by the common-
mode input voltage. If we treat Rf as two resistors of resistance Rf /2 that are
connected in series, then the connection node of the resistors will be an AC
ground. Similarly, if we treat Cf as two capacitors of capacitance 2Cf that
are connected in series, then the connection node of the capacitors will also
be an AC ground. We can now replace the parallel-connected Rf and Cf with
two series-connected RC circuits, each consists of a resistor resistance Rf /2
in parallel with a capacitor of capacitance 2Cf . The connection node will be
an AC ground. This allows we to separate the amplifier into two common-
source amplifiers with source degeneration, as shown in in Fig.2.1. At low
frequencies where the effect of 2Cf is negligible, the source degeneration
provided by Rf /2 will lower the gain of the amplifier. At high frequencies
where 2Cf will behave as a short-circuit to short Rf /2, source degeneration
will be removed. As a result, a large voltage gain will be obtained.
Figure 2.1: Continuous-time linear equalizer.

2 Laboratory Work
2.1 Serial Link with CTLE
Connect CTLE of Fig.2.1 to the output of the serial link designed in Labo-
ratory 1, as shown in Fig.2.2.
One important issue that needs to be addressed is the common-mode
input voltage of CTLE. The 50Ω termination resistors at the far end of
the channel will result in a large common-mode input voltage of CTLE,
which might give rise to an improper dc bias of the NMOS transistors of
CTLE subsequently a low voltage gain. The tail current sources and load
resistors of CTLE should be carefully chosen such that the NMOS transistors
are properly biased in saturation in order to have a large transconductance
subsequently a large voltage gain. In order to have a large voltage gain
at high frequencies, the load resistors of CTLE can be replaced with spiral
inductors. The added inductors resonate out the load capacitance of the
CTLE at the desired frequency, such as the baud-rate frequency of the serial
link so as to boost the bandwidth.
Another important issue is the choice of the value of Rf and Cf . Using
small-signal analysis one can show that the CTLE has a zero at frequency 1
1
ωz = (2.1)
Rf Cf
and a pole at frequency
1 R f gm Rf gm

ωp = + 1 = ωz +1 . (2.2)
Rf Cf 2 2
Since ωz < ωp , the zero boosts the gain of CTLE at 20 dB/dec when
ω > ωz . If the channel is modeled as a single-pole system with bandwidth
ωch , then ωz should be set in the vicinity of ωch so as to effectively compensate
for the loss of the channel.
1
These results are obtained under the assumption that Cgs , Cgd Cf and RL ro .
Figure 2.2: Serial link with CTLE.
The resistance of the load resistors should also be chosen with care. A
large load resistance will certainly benefit voltage gain. This, however, is at
the expense of reduced bandwidth as the output pole is formed by the load
resistor and the capacitance at the output of CTLE. A large load resistance
will also lower the common-mode voltage of the output of CTLE. Note that
in a typical DFE, CTLE is followed by a slicer (comparator). The common-
mode output voltage of CLTE affects the operation of the slicer and needs
to be set as per the common-mode input voltage range of the slicer.
2.2 Analysis
The following analyses are to be performed :
1. Frequency response of CTLE : Perform the frequency-domain of

CTLE. Provide the same DC bias as that with the rest of the circuit
(transmitter, channel, and termination resistors) present. Sweep the
frequency of the input signal and record the output of CTLE. Record
ωz of CTLE. Plot the frequency response of CTLE by (i) sweeping Rf
while keeping Cf unchanged and (ii) sweeping Cf while keeping Rf
unchanged. Record the results.
2. Time-domain response serial link : Replace the PRBS generator

with a pulse generator with pulse width 1 ns, pulse amplitude 1.2V and
period 20 ns. Plot the time-domain response vo (t) of CTLE for three
difference lengths of the channel (10 cm, 50 cm, and 100 cm). Measure
the pre-cursors, main cursor, and post-cursors of vo (t). Compare these
results with those without the CTLE obtained in Laboratory 1.
3. Eye diagram of the response : Activate the PRBS generator. The

output bit stream of the PRBS generator should be of swing 0-1.2V and
period 1 ns. Plot the eye diagram of the time-domain response vo (t) of
CTLE for three difference lengths of the channel (10 cm, 50 cm, and
100 cm). Measure the vertical and horizontal openings of data eyes.
Measure peak-to-peak jitter at the zero-crossing of data eyes. Compare
these results with those without CTLE obtained in Laboratory 1.
3 Laboratory Report

ber
• List of figures
• List of tables
2. Main body (80%):

• The schematic of the entire design (5%)

• Tabulate the dimension of all transistors of CTLE (5%).
• Frequency response of CTLE. Tabulate the gain of CTLE at DC
and at the peak, ωz at which the gain rises at 20 dB/dec and ωm
at which the gain of CTLE is maximized (10%).
• Frequency response of CTLE by (i) sweeping Rf while keeping
Cf unchanged and (ii) sweeping Cf while keeping Rf unchanged
(10%).
• Time-domain response of the output of CTLE for 3 different chan-
nel lengths. Tabulate the measured pre-cursors, main cursor, and
post-cursors for each channel length (20%).
• Eye diagram of the output of CTLE for 3 different channel lengths.
Tabulate the measured vertical and horizontal openings of data
eyes, and peak-to-peak timing jitter at the zero-crossing of data
eyes for each channel length (20%).
Provide no less than three (3) but no more than five (5) conclusions that
you can draw from this design laboratory with a particular focus on the
comparison of the results obtained without CTLE in Laboratory 1 and
those obtained in this laboratory. Your conclusions must be supported
by the simulation results obtained and must be as specific and precise
as possible.
Chapter 3
Phase-Locked Loops
1 Introduction
Phase locked loops are used extensively in data communications, computer
systems, RF communications, instrumentation, and signal processing. In se-
rial links, PLLs are used at both transmitters and receivers. In transmitters,
PLLs are locked to a clean reference, often the output of a crystal oscilla-
tor. The clocks generated by the PLLs are used to perform important tasks
such as pre-emphasis. In receivers, PLLs are locked to incoming data sym-
bols with embedded timing information to perform clock recovery. In this
laboratory, you are required to design a PLL with an Alexander bang-bang
phase detector, a 4-stage voltage-controlled ring oscillator, and a 500 MHz
50% duty-cycle digital input.
1.1 Voltage-Controlled Ring Oscillators

In this laboratory, you are required to design a 4-stage fully differential
CMOS voltage-controlled ring oscillator as part of the phase-locked loop of
a 1 Gbps serial link. The oscillation frequency of the oscillator is 500 MHz
(1 Gbps). The delay cell of the oscillator shown in Fig.3.1 utilizes a posi-
16
CHAPTER 3. PHASE-LOCKED LOOPS 17
tive latch to sharpen the falling edge of the waveform of the oscillator1 . As
pointed out by Weigandt et al. that the noise of VCOs at threshold-crossing
shifts threshold-crossing time by an amount that is proportional to the noise
injected at the threshold-crossing and inversely proportional to the slew rate
of the output voltage2 :
vn2
∆τ 2 = , (3.1)
(dvo /dt)2
where ∆τ 2 and vn2 are the power of timing jitter and that of the noise injected
at the threshold-crossing, respectively and dvo /dt is the slew rate of the
output voltage of the oscillator at the threshold-crossing. It is seen from (3.1)
that sharpening transition edges lowering timing jitter. Reducing the
timing jitter or phase noise of VCOs is critical to lower the overall phase
noise of PLLs. As the output of the VCO is used to sample incoming data,
minimizing the timing jitter of the sampling clock, i.e., the output of the
VCO, is pivotal to the reliable recovery of data especially when data rate is
high.
Laboratory Work
1. Design the 4-stage CMOS fully differential voltage-controlled ring os-

cillator shown in Fig.3.1. The width of M3-M4 should be sufficiently
large such that they are capable of breaking the latch formed by M1-
M2 and yet not over-sized to impose a severe penalty on the output
capacitance of delay stages subsequently the frequency of the oscillator.
2. Rise and Fall times : Perform the time-domain analysis of the oscillator.
The oscillator can be activated by connecting a small capacitor with
1
X. Mailand, F. Devisch, and M. Kuijk, “A 900 Mb/s CMOS data recovery DLL using
half-frequency clock,” IEEE Journal of Solid-State Circuits, vol. 37, No. 6, pp 711-715,
June 2002.
2
T. Weigandt, B. Kim, and P. Grey, “Analysis of timing jitter in ring oscillators,” Proc.
of IEEE International Symp. Circuits and Systems, pp. 27-30, London, 1994.
Figure 3.1: 4-stage voltage-controlled ring oscillator.
an initial voltage to the output node of one of the delay stages of the
oscillator. Note that the value of the capacitor should be small in order
to minimize its loading effect. Alternatively, you can inject a current
pulse of a narrow pulse width and a long period into any node of the
oscillator to start oscillation. Both methods mimic the injection of
noise to start oscillation in real oscillators. Plot the output voltage
of the each stage of the oscillator. Measure the rise and fall times of
the output voltage of the oscillator. Note that transistors should be
properly size in order to have the same rise and fall times3 .
3. Frequency Tuning Curve : Use parametric analysis and calculator tools

to obtain the oscillation frequency-control voltage plot of the oscilla-
tor by sweeping the control voltage of the oscillator from 0 to 1.2V
while recording the frequency of the oscillator. Although the frequency
tuning range of an oscillator could be large, it is typically the linear
portion of the frequency tuning curve that is considered as the effec-
tive frequency tuning range. Estimate the gain of the oscillator defined
as
3
Rise time is the amount of the time for the output of the oscillator to rise from 10%
to 90% of its peak-to-peak value. Fall time is defined similarly.
fmax − fmin
Kvco = (3.2)
Vc,max − Vc,min
over the linear portion of the frequency tuning curve where fmax and
fmin , Vc,max and Vc,min are the maximum and minimum frequencies
and their corresponding control voltages of the oscillator in the linear
portion of the frequency tuning curve, respectively. Note the unit of
Kvco is Hz/V.
1.2 Bang-Bang Phase Detector

Phase detectors (PDs) are one of the vital building blocks of phase-locked
loops and delay-locked loops. The main functionality of PDs is to sense
the phase difference between an input digital stream and the output of a
local oscillator and output a pulse whose width is proportional to the phase
difference (linear PDs). The output of the PD is used to control a charge
pump and a low-pass filter (loop filter) whose output voltage adjusts the
frequency of the oscillator.
Phase detectors can be loosely classified into linear PDs and bang-bang
PDs (nonlinear PDs). The output of a linear PD is a pulse whose width
is proportional to the phase difference. The output of a bang-bang PD is
a binary signal (i.e., 0 or 1) whose value corresponds to the polarity of the
phase difference. When a linear PD is used, the amount of the current
sourced or sinked by the charge pump is proportional to the phase difference.
When a bang-bang PD is used, the amount of the current sourced or sinked
by the charge pump is maximized thereby maximizing the adjustment of
the frequency of the oscillator. Due to stringent timing constraints4 , phase
detectors used in multi-Gbps serial links are most bang-bang phase detectors.
4
For a serial link of data rate 10 Gb/s, the symbol time is 100 ps. PLLs must establish
lock in less than 100 ps, often half of the symbol time, thereby imposing a stringent
constraint on the lock time of the PLLs.
Alexander phase detector shown in Fig.3.2 is a widely used bang-bang

phase detector 5 . Because the sampling clock period is the same as the
symbol time, this phase detector is categorized as full-rate phase detectors.
A difficulty of using this phase detector for multi-Gb/s CDR is the need for
a multi-GHz clock. The frequency constraint can be relaxed by introducing
sub-rate sampling. leading to the half-rate Alexander phase detector shown
in Fig.3.36 .
Figure 3.2: Full-rate Alexander phase detector.
Since a large number of DFFs are used in Alexander PDs, the character-
istics of DFFs undoubtedly affects the performance of the PDs. There are
many ways to construct a DFF. The conventional DFF shown in Fig.3.4(a)
suffers from a large transistor count, high power consumption, and a long
propagation delay. True-single-phase-clocking (TSPC) logic circuits pro-
posed by Yuan and Svensson7 offer the advantages of a low transistor count,
5
J. Alexander, “Clock recovery from random binary signals,” IEE Electronics Letters,
Vol. 11, No. 22, pp. 541-542, 1975.
6
B. Razavi, “Challenges in the design of high-speed clock and data recovery circuits,”
IEEE Comm. Mag., pp. 94-101, Aug. 2002.
7
J. Yuan and C. Svensson, “New single-clock CMOS latches and flipflops with improved
Figure 3.3: Half-rate Alexander phase detector.
a small chip area, low power consumption, and a fast transient response. In
this laboratory, TSPC positive-edge triggered DFF shown in Fig.3.4(b) is
used to construct Alexandar PDs8 .
Laboratory Work
Apply two 500 MHz digital signals of different phases to the input of the
phase detector. Vary the phase of the two input signals in such a way that
one leads the other or one lags the other and record the output of the phase
detector. Plot the output of the phase detector versus the phase difference
between the two inputs and determine the minimum phase difference that
the phase detector cannot detect.
speed and power savings,” IEEE J. Solid-State Circuits, Vol. 32, No.1, pp. 62-69, Jan.
1997.
8
For various configurations of TSPC dynamic circuits, please see text book : J. Rabaey,
Digital Integrated Circuits : A Design Perspective, Upper Saddle River, NJ : Prentice-Hall,
1996. The 2nd edition of the book is also available.
Figure 3.4: (a) DFF using standard logic cells. (b) TSPC positive-edge
triggered DFF.
1.3 Phase-Locked Loop

The basic configuration of type-II phase-locked loops also known as charge
pump PLLs is shown in Fig.3.5. The phase detector detects the phase differ-
ence ∆φ between the incoming digital signal Vin and the output of the local
oscillator and maps it to Boolean signals UP and DN. They are then fed to
the downstream charge pump where UP and DN are mapped to a current
of constant amplitude but different directions. When UP=1/DN=0, JU P is
conveyed to the loop filter, increasing the output voltage of the loop filter.
When UP=0/DN=1, JDN is sinked from the loop filter, lowering the output
voltage of the loop filter. The loop filter is a low-pass that performs I/V con-
version and filters out high-frequency spikes. The output of the loop filter
controls the frequency of the oscillator. By adjusting the frequency of the
oscillator, the phase difference ∆φ can be driven to zero. When this occurs,
no current will flow to/out of the loop filter and the output of the loop filter
will remain unchanged (lock state).
In this laboratory, you are required to design a phase-locked loop that
makes use of the 4-stage voltage-controlled oscillator and the Alexander PD
designed previously. In order to construct the phase-locked loop, you are also
required to design and analyze two additional function blocks of phase-locked
Figure 3.5: Basic configuration of type II phase-locked loops.
loops, namely the charge pump and the loop filter.
2 Laboratory Work
2.1 Charge Pumps
The main functionality of a charge pump is to map UP and DN from the
preceding PD to a current of constant amplitude but different directions.
Fig.3.6 is the schematic of a current-steering charge pump. The charge pump
conveys a constant current JU P to or sinks a constant current JDN from the
output node, as shown in Fig.3.6. For a rich collection of charge pumps,
please see text CMOS Current-Mode Circuits for Data Communications (F.
Yuan, Springer, 2008).
2.2 Loop Filters

In order to convert the output current of the charge pump to a voltage, a loop
filter consisting of two capacitors C1 and C2 and a resistor R2 is employed at
the output of the charge pump, as shown in Fig.3.5 is employed. Note that
C2 C1 , typically C2 = 10C1 . C2 and R2 form the main part of the loop
filter and dictate the loop bandwidth. Since for high-frequency signals, C2
acts as a short-circuit. As a result, high-frequency signals will generate high-
Figure 3.6: Implementation of current-steering charge pump.
frequency voltages (voltage spikes) across R2 , which will in turn generate

unwanted frequency tunes in the spectrum of the oscillator. These unwanted
tunes are called reference spurs9 . To minimize reference spurs, a smaller
capacitor C1 can be added in parallel with R2 ∼ C2 to filter out the unwanted
high-frequency signals. At frequencies inside the loop bandwidth, C1 behaves
as an open-circuit and therefore has no effect on the indented operation of
the PLL.
2.3 Open-Loop Test of PLL

Construct an open-loop test schematic containing a PD, a charge pump, and
a loop filter, as per Fig3.7. Apply two 500 MHz square waves A and B to the
PD. Let input A lead input B with a phase difference ∆φ. Use parametric
analysis to sweep ∆φ for 3 different values and record the output voltage of
the loop filter Vc . Repeat the simulation with A lagging B.
9
The reason that these unwanted tunes are termed reference spurs is that if the in-
put signal is a square wave, although ideally the output of the loop filter should remain
unchanged in lock state, the imperfections of charge pumps such as current mismatch,
charge injection, and clock feed-through give rise to periodic spikes in the output of the
loop filter. The period of these spikes is the same as that of the input (reference).
Figure 3.7: Open-loop test circuit.
2.4 Closed-Loop Test of PLL

Apply a 500 MHz square wave to the input A of the phase detector. The other
input of the phase detector B comes from the output of the 500 MHz local
oscillator10 . When a lock state of the PLL is established, the average value
of the control voltage Vc of the oscillator should settle down to a constant
value. Repeat the preceding test for 3 different phase differences.
The following tips are useful in ensuring the lock of the PLL :
• TSPC DFFs : Unlike DFFs implemented using static logic gates, TSPC
logic circuits are dynamic circuits whose logic states are retained by the
charge of the capacitors between neighboring stages. These capacitors
are formed by the input capacitance of the driven stage and the output
capacitance of the driving stage. As the voltages of these capacitors
might not be full swing (0-1.2V), a care must be taken in sizing tran-
sistors to ensure that the voltage swing of these capacitors exceeds the
threshold voltage of the driven stage so as to ensure the proper and
reliable operation of the DFFs.
10
Note that the output of the local oscillator of PLLs typically does not have 0-1.2V
swing. An voltage buffer such as a inverter chain connected to the output of the oscillator
is often used.
• The current of the charge pump needs to be chosen with a care. If the
current is overly small, the resultant voltage change of the loop filter
will be too small to provide an adequate adjustment of the frequency
of the oscillator. As a result, the PLL might not be able to achieve
lock. If the current of the charge pump is overlay large, the resultant
voltage change of the loop filter will be too large to overly adjust the
frequency of the oscillator, which will also not be able to achieve lock.
• Loop filter : The bandwidth of the PLL is dictated by R2 and C2 of

the loop filter. A large R2 C2 will result in a small loop bandwidth,
which helps minimizing the effect of the noise of the reference (input)
of the PLL. A small R2 C2 will result in a large loop bandwidth, which
helps minimizing the effect of the noise of the oscillator. For the PLL
of transmitters, the reference of the PLL is from a crystal oscillator
whose phase noise is low and the dominant noise source is the one from
the oscillator, maximizing the loop bandwidth in this case is preferred.
For PLL of receivers, the input of the PLL of the receivers is incoming
data sequence, which is typically corrupted by noise and disturbances
coupled to the channel. The dominant noise in this case is the one
from the input rather than that from the oscillator. Minimizing the
loop bandwidth in this case is preferred. Minimizing loop bandwidth,
however, will increase lock time.
3 Laboratory Report

ber
• List of figures
• List of tables
2. Main body (80%)
• The schematic of the voltage-controlled oscillator and a table tab-

ulating the dimension of all transistors of the oscillator (5%).
• The schematic of the phase detector and a table tabulating the
exact dimension of all transistors of the phase detector (5%).
• The schematic of the charge pump and loop filter, and a table
tabulating the dimension of all transistors (5%).
• The schematic of the phase-locked loop (5%).
• Voltage-controlled oscillator : The waveform of the voltage of
the output of all 4 stage of the oscillator and the frequency tuning
curve of the oscillator obtained by sweeping the control voltage of
the oscillator and recording the frequency of the oscillator. De-
termine the frequency tuning range (the linear portion only) and
the gain of the oscillator (10%).
• Phase detector : The plot of the output of the phase detector
versus the phase difference of the two inputs. Determine the min-
imum phase difference that the phase detector can detect (10%)
• Open-loop test of PLL : The plot of the output of the loop
filter versus the difference of the inputs of the phase detector for
both a positive phase difference and a negative phase difference
(20%).
• Closed-loop test of PLL :The plot of the waveform of the con-

trol voltage Vc of the oscillator from the time instance at which
a 500 MHz square wave input is applied to the phase detector to
the time instance at which the average value of the control voltage
of the oscillator converges to a constant value. Measure the lock
time of the PLL11 (20%).
11
The lock time of a PLL is the time from the injection of the input of the PLL to the
time instance at which the control voltage of the oscillator converges.
Chapter 4
Pre-Emphasis
1 Introduction
Pre-emphasis is an effective channel equalization technique performed on the
transmitter side prior to data transmission. It purposely pre-distorts data
symbols to be transmitted at the near end of the channel prior to their trans-
mission in such a way that when the pre-distorted data symbols reach the
far end of the channel, they will emerge as desired data symbols, i.e., data
symbols that yield the optimal bit error rate. Since the main impact of chan-
nels is to attenuate the high-frequency components of data symbols, arising
from the finite bandwidth of the channels, pre-emphasis can be performed
in one of the following two different ways to achieve the same results : (i)
Amplify the high-frequency components of data symbols or (ii) attenuate the
low-frequency components of data symbols. The former is undesirable as it
signifies crosstalk, which typically identifies at high frequencies. Although
the latter deteriorates signal-to-noise ratio as most of the energy of data
symbols is located at frequency of the baud rate of data symbols, it is still a
preferred choice as it does not deteriorate crosstalk.
In this laboratory, you are required to design a 2-tap pre-emphasis block
that equalizes the channel studied in previous laboratories. The pre-emphasis
block consists of (i) two unit interval (UI) delay blocks whose propagation
29
CHAPTER 4. PRE-EMPHASIS 30
delay is the symbol time, (ii) two tap multipliers that multiply the delayed
version of the data to be transmitted with tap coefficients, (iii) one summer
that constructs the pre-emphasized data symbols, and (vi) a phase-locked
loop that provides clocking signals for delay units.
1.1 Unit Delay Cells

Two unit delay stages that have the propagation delay of one symbol time
are used to delay the transmitted data prior to their transmission. Although
one can use a pair of static inverters and a capacitor to construct a unit delay
cell, process spread makes it difficult to ensure that the delay of the delay
cell is exactly one symbol time. One effective way to avoid this difficulty is
to use clocked delay cells. The period of the clocking signal is one symbol
time. Fig.5.2 shows one implementation of such a clocked delay cell.
Figure 4.1: Clocked delay stage.
1.2 Pre-Emphasis Tap Multiplier

Tap multipliers perform the function of multiplying the delayed versions of
data to be transmitted by tap coefficients. In order to meet timing con-
straints of multi-Gbps, current-steering is the most widely used architecture
of tap multipliers. In this architecture, the delayed versions of the data to
be transmitted are the current-steering signals while the tap coefficients to

be multiplied are the tail currents, as shown in Fig.4.2.
Figure 4.2: Tap multipliers of pre-emphasis.
1.3 Summer/Driver
The summation of the products of the delayed version of the data to be
transmitted and their corresponding pre-emphasis tap coefficients is typically
performed in the current domain so as to take the advantages of the speed
advantages of current-mode circuits. When the number of pre-emphasis taps
is large, the capacitance encountered at the summing node becomes large.
This will have a detrimental effect on the speed of the transmitter. In order
to lower the constant of the summing node, pre-emphasis block and driver
are often combined such that although the capacitance of the summing node
is large, the resistance seen at the summing node is only 50Ω, effectively
minimizing the time constant of the summing node, as shown in Fig.4.3.
2 Laboratory Work
2.1 Serial Link
Construct the serial link consisting of the PRBS generator, pre-emphasis
block, and channel designed previously as per Fig.4.4.
Figure 4.3: Summer and driver of pre-emphasis block.
Figure 4.4: Serial link with pre-emphasis
2.2 Eye Diagram

Perform the transition analysis of the serial link and plot the eye diagram
of vout . Adjust pre-emphasis tap coefficients to achieve the maximum eye
openings, both vertically and horizontally.
Repeat the preceding procedures with pre-emphasis disabled. Compare
the results with and without pre-emphasis.
2.3 Power Consumption

Plot the current drawn by (i) the pre-emphasis block including the driver
and (ii) the phase-locked loop. These measurements provide the breakdown
of the power consumption of the serial link.
3 Laboratory Report

ber
• List of figures
• List of tables
2. Main Body (80%)
• Schematics (20%)
– The schematic of the pre-emphasis block including the driver.
– The complete schematic (block-level diagram) of the serial
link.
• The eye diagram of the serial link without pre-emphasis block
(20%).
• The eye diagram of the serial link with pre-emphasis block (20%).,
• The plot of the current drawn by the pre-emphasis block and PLL
and a table tabulating the power consumption of the pre-emphasis
block and PLL (20%).
Chapter 5
Decision Feedback Equalizers
1 Introduction
Decision feedback equalization is the most widely used post channel equal-
ization technique for multi-Gbps serial links. In this laboratory, you are
required to design a 2-tap decision feedback equalizer that will utilize blocks
such as the transmitter, channel, continuous-time linear equalizer, and PLL
designed in the previous laboratories. A 2-tap decision feedback equalizer
consists of (i) a slicer that samples the difference between the output of the
continuous-time linear equalizer and the sum of the DFE taps, (ii) 2 unit
interval (UI) delay blocks whose propagation delay is the symbol time, (iii)
2 tap multipliers, each multiplies the past decision of the slicer with a tap
coefficient, and (iv) a summer that subtracts the DFE taps from the output
of the continuous-time linear equalizer.
1.1 Slicer
Slicers are essentially voltage comparators that compare the difference be-
tween the output of the continuous-time linear equalizer and the DFE taps
with a threshold reference and produce a digital output. The threshold ref-
erence is typically the common-mode voltage of the difference signal. Fig.5.1
35
CHAPTER 5. DECISION FEEDBACK EQUALIZERS 36
shows one possible implementation of slicers. It compares differential input

+ −
vin with reference voltage Vref . During φ = 0, the inputs vin and vin charge
the input capacitors Cgs2 and Cgs5 , respectively. M7-8 and M9-10 form a
pair of cross-coupled inverters. M6 and M11 force v1 = v2 . Also, M12 and
M13 force v1 and v2 to VDD . Note that M12 and M13 should be large enough
such that they will break the cross-coupled inverter pair and force v1 and
v2 to VDD . During φ = 1, the inverter pairs are enabled and v1 and v2 are
set by the voltages of Cgs2 and Cgs5 . The positive feedback formed by the
cross-coupled inverter pair provides fast state transition.
Figure 5.1: Slicer.
1.2 Unit Delay Cells

Two unit delay cells that have the propagation delay of one symbol time
are used to generate two past decisions of the slicer. Fig.5.2 show a possible
implementation of such a clocked delay cell.
Figure 5.2: Clocked delay cells.
1.3 Tap Multiplier

Two tap multipliers are used to generate the product of the past decisions
of the slicer and the tap coefficients. In order to meet timing constraints
at multi-Gbps, current-steering is the most widely used architecture of tap
multipliers. In this architecture, the past decision is the current-steering
signal, the tap coefficient is the tail current, and the product of the past
decision and the tap coefficient is the steered current, as shown in Fig.5.3.
Figure 5.3: Tap multiplier. The past decision is the current-steering signal,
the tap coefficient is the tail current, and the product of the past decision
and the tap coefficient is the steered current.
1.4 Summer
The subtraction of DFE taps from the output of the continuous-time linear
equalizer is performed in the current domain to take the speed advantage
of current-mode circuits, as shown in Fig.5.4. The polarity of the current-
steering signals D1 , D1 , D2 , and D2 should be arranged in such a way that
the currents steered by them are subtracted from the output current of the
continuous-time linear equalizer. Since the time constant of the output of the
summer is the product of the output capacitance of the summer and the load
resistance of the CTLE, and the output capacitance rises with the increase in
the number of DFE taps, the load resistance of CTLE should be kept small.
If the load resistance is overly low, the output voltage of the summer will be
too small to be picked up reliably by the downstream slicer. To overcome
this difficulty, inductors are often added in series with the load resistors to
boost the gain of the summer at high frequencies without using large load
resistors.
Figure 5.4: Current-mode summer.

2 Laboratory Work
2.1 Serial Link
Construct a 1 Gbps serial link that consists of the PRBS generator, pre-
emphasis block, channel, continuous-time linear equalizer, and PLL at the
transmitter and PLL at the receiver designed previously, as well as the DFE
detailed earlier as per Fig.5.5. For the pre-emphasis block, use the coefficients
obtained in previous laboratory. Optimal DFE tap coefficients are to be
obtained in this laboratory using a trial-and-error approach.
Figure 5.5: Serial link with a 2-tap pre-emphasis block and a 2-tap decision
feedback equalizer.
2.2 Eye Diagram

Perform the transition analysis of the serial link. Plot the eye diagram of
the equalized data symbols, i.e., the input of the slicer, with DFE enabled1 .
Adjust DFE tap coefficients to achieve the maximum eye openings, both
vertically and horizontally. Since tap 1 is used to eliminate the first post-
cursor, which is typically much larger as compared with the second post-
cursor, the adjustment of tap 1 will therefore have a greater impact on eye
1
Equalized data symbols are the input of the slicer. Unequalized data symbols are the
output of the continuous-time linear equalizer.
openings as compared with that of tap 2. Suggest to disable tap 2 first

and only adjust tap 1 until no further improvement in eye openings can be
obtained. Then keep tap 1 unchanged and adjust tap 2 to further improve
eye openings.
Repeat the preceding procedures without DFE. Record eye openings with-
out DFE and compare the results with those with DFE.

Plot the current drawn by (i) pre-emphasis block, (ii) transmitter PLL, (iii)
CTLE, (iv) receiver PLL, and (v) DFE. The amount of the power consump-
tion of these blocks is the product of the current of these blocks and VDD .
These results provide the detailed breakdown of the total power consumption
of the serial link.
3 Laboratory Report
in the main body of the report. All expressions, figures, and tables must
be numbered. All figures and tables must be captioned. Cadence print-
outs attached to the end of the report are not acceptable. Hand-
written post-laboratory reports will be rejected. Laboratory reports
must contain the followings :

ber
• List of figures
• List of tables
2. Main Body (80%)
– The schematic of the slicer
– The schematic of the delay unit
– The schematic of tap multiplier
link.
• The eye diagram of the serial link without DFE (20%).
• The eye diagram of the serial link with DFE (20%).,
• The plots of the current drawn by (i) the pre-emphasis block, (ii)
transmitter PLL, (iii) CTLE, (iv) receiver PLL, and (v) DFE and
a table tabulating the average power consumption of these blocks
(20%).
Chapter 6
Clock and Data Recovery
1 Introduction
As the timing information of serial links is embedded in data symbols using
data encoding such as 8/10 encoding, clock recovery operation recovers the
timing information of serial links from received data symbols by detecting the
periodic transitions of data symbols. There are two widely used approaches
for clock recovery, namely phase-tracking and phase-picking. The former
utilizes a phase-locked loop at the receiver end to align the output of the
oscillator of the PLL with the transition edge of received data while the
latter allocates the transition edge of received data by sampling each data
symbol multiple times. Phase-tracking is a closed-loop approach and enjoys
the advantages of a low sensitivity to the effect of PVT (process, voltage,
and temperature) variation but suffers from a stiff challenge in achieving fast
lock. Phase-picking is an open-loop approach and enjoys the advantages of
a high data rate but are more sensitive to the effect of PVT variation.
In this laboratory, you are required to design a clock and data recovery
block using phase-tracking.
42
CHAPTER 6. CLOCK AND DATA RECOVERY 43
2 Laboratory Work
Reuse the serial link with the longest channel that you designed in the pre-
vious design laboratory. It is shown in Fig.6.1 for your convenience. The
recovered clock is the output of the oscillator of the PLL while the recovered
data is the output of the slicer.
Figure 6.1: Serial link. Additional circuitry (in red color) is added to compute
the BER.
Although the eye diagram of equalized data symbols provides a virtual

assessment of the quality of serial links, it is the bit-error-rate (BER) plot
also known as bathtub curve of serial links shown in Fig.6.2 that provides
the quantitative measure of the performance of serial links. To generate this
plot, you need to vary the sampling position of the slicer in red color from
the center of data eyes to the edge of data eyes by adjusting the delay ∆τ
∗
of the delay cell and compare the output of the auxiliary slicer Dout with
the output of the PRBS block Din 1 . Specifically, for each sampling position
of the slicer, perform the transient analysis of the link over a long interval,
∗
record Din and Dout , and compute BER of the link2 . Repeat this for all
1 ∗ ∗
Dout differs from Dout as Dout is the sample at the center of data eyes whereas Dout
is the sample at the time instant displaced from the center of data eyes by ∆τ .
2 ∗
BER can be computed using a simple Matlab routine once Din and Dout are available.
∗
Record Din and Dout in Spectre and input them to Matlab. Compares each element of
sampling positions. Plot BER for each sampling position.
Figure 6.2: Bathtub curve of BER.
3 Laboratory Report

ber
∗
Din with the corresponding element of Dout . Record the number of data bits transmitted
∗
and the number of times that Din 6= Dout . BER is the ratio of the number of times that
∗
Din 6= Dout to the number of data bits transmitted.
• List of figures
• List of tables
2. Main Body (80%)
• The schematic of the delay block (10%).

• The complete schematic (block-level diagram) of the serial link
with the inclusion of additional circuitry for BER (10%).
• Transient waveform plot that shows discrepancies between the re-
covered data and the transmitted data (20%)
• The MATLAB routine that is used to compute the BER of the
serial link (20%)
• The BER bathtub plot of the serial link (20%).
Chapter 7
Adaptive Decision Feedback

Equalizers
1 Introduction
The performance of DFE critically depends upon tap coefficients. The opti-
mal tap coefficients that yield the maximum eye openings varies with both
data rate and the characteristics of channels. In Laboratory 5, a trial-and-
error approach was used to find optimal tap coefficients. In this laboratory,
a systematic method that is based on the principle of least-mean-square will
be used to guide the search for optimal tap coefficients. The method searches
for optimal tap coefficients with the objective to minimize the power of the
difference between the desired and equalized data symbols, i.e., the output
and input of the slicer. In this design laboratory, you are required to design a
2-tap adaptive decision feedback equalizer that will utilize blocks such as the
transmitter, channel, continuous-time linear equalizer, and PLLs that you
designed in the previous design laboratories. The adaptive decision feedback
equalizer will consist of (i) a slicer that samples the difference between the
output of the continuous-time linear equalizer and the DFE taps, (ii) 2 unit
interval (UI) delay blocks whose propagation delay is the symbol time, (iii)
2 tap multipliers that multiply the past decisions of the slicer with appro-
46
CHAPTER 7. ADAPTIVE DECISION FEEDBACK EQUALIZERS 47
priate tap coefficients, (iv) a summer that subtracts the DFE taps from the
output of the continuous-time linear equalizer, and (v) an adaptive engine
that computes the amount of the adjustment of tap coefficients and adjusts
the tap coefficients by varying the tail currents of the tap multipliers.
The uncertainty of the characteristics of channels requires that tap co-
efficient be set in accordance of both data rate and the characteristics of
channels such that a complete removal of post cursors can be achieved. The
optimal tap coefficients are obtained by minimizing the power of the differ-
ence between the desired and equalized data symbols measured at the center
of the data eye, i.e., least-mean-square (LMS). In a LMS adaptive DFE, the
jth optimal tap coefficient is obtained using iterative operation
cj,k+1 = cj,k + hk vs,k , (7.1)
where cj,k+1 and cj,k are the coefficients of tap-j in iterations k + 1 and k,
respectively, k is the difference between the output and input of the slicer
measured at the center of the data eye, i.e., the desired and equalized data
symbols, and h is the step size used to adjust the tap coefficient.
The preceding LMS adaptive DFE is difficult to implement due to the
need for k and vk , which can only be obtained using ADCs. Sign-sign LMS
adaptive DFE that only uses the signs of k and vs,k rather than their actual
values to obtain the optimal tap coefficient
cj,k+1 = cj,k + hsign[k ]sign[vs,k ], (7.2)
where sign[x] = 1 if x≥0 and -1 otherwise is proven to be an effective com-

promise.
2 Laboratory Work
2.1 Serial Link with Adaptive DFE
Construct the serial link consisting of the PRBS generator, transmitter,
block, channel, CTLE, PLLs, and adaptive DFE designed previously as per
Fig.7.1. The core of the adaptive DFE is the adaptive engine that performs
the following tasks : (i) Compute the amount of the adjustment of tap co-
efficients. (ii) Adjust tap coefficients. The amount of the adjustment of tap
coefficients is given by hsign[k ]sign[vs,k ]. sign[vs,k ] is the output of the slicer
and is readily available. k quantifies the difference between the desired and
equalized data symbols. Although the desired data symbols are the output of
the slicer, if the output of the slicer is 1, the difference will always be greater
than 0. Similarly, if the output of the slicer is 0, the difference will always be
less than 0. These observations reveal that k should be defined differently
in order to ensure the proper operation. Since if the transmitted data is 0,
the equalized data should also be 0 ideally. Similarly, if the transmitted data
is 1, the equalized data should also be 1 ideally. These observations suggest
that k should be generated by comparing the equalized data with Vref,H if
the transmitted data is 1 and Vref,L if the transmitted data is 0 where Vref,H
and Vref,L are desired voltage for 1 and that for 0, respectively. The exact
values of Vref,H and Vref,L depend on both data rate and the characteristics
of the channel over which data are transmitted. A simple logic circuit can
therefore be developed to generate sign[k ]. The inputs to this logic circuit
include (i) the equalized data symbol, (ii) Vref,H , (iii) Vref,L , and (iv) the
output of the slicer that indicates whether the transmitted data is 0 or 1.
Although the amount of the adjustment of tap coefficients is given by
hsign[k ]sign[vs,k ]. sign[vs,k ], only h is an analog quantity whereas the other
two are digital, revealing that h quantifies the amount of the adjustment of
tap coefficients while sign[k ]sign[vs,k ] determines whether the adjustment
is incremental or decremental. A natural circuit that can provide both
incremental or decremental changes of a voltage is a charge pump. The
Figure 7.1: Serial link with pre-emphasis and adaptive decision feedback
equalization
charge-up or charge-down control signals of the charge pump is provided by

sign[k ]sign[vs,k ] while the current of the charge pump is provided by h. Since
the DFE has two taps, 2 charge pumps will therefore be needed. The out-
puot of the charge pumps are routed to the tail current sources of the tap
multipliers to tune the tap coefficients.
2.2 Adaptation
Perform transition analysis of the serial link and plot the output voltages
of the two charge pumps that set the tail currents of the tap multipliers.
When adaptation ends, the voltages of the charge pumps will converge to
constant values. These two plots show the adaptation process, in particular,
the amount of the time needed to find the optimal tap coefficients.
2.3 Eye Diagram

Plot the eye diagram of the equalized data symbols when adaptation has
ended. Compare the eye openings with those obtained in using the trial-end-
error method in Laboratory 5.

Plot the current drawn by (i) the transmitter, (ii) transmitter PLL, (ii)
CTLE, (iii) receiver PLL, and (vi) adaptive DFE. These measurements will
provide the detailed breakdown of the power consumption of the serial link.
3 Laboratory Report

ber
• List of figures
• List of tables
2. Main Body (80%)
– The schematic of the adaptive engine.
link.
• The eye diagram of the serial link when adaptation has ended
(20%).
• The plots of the output voltages of the two charge pumps showing
adaptation process (20%).
• The plots of the current drawn by (i) the transmitter, (ii) trans-
mitter PLL, (iii) CTLE, (iv) receiver PLL, and (v) adaptive DFE
and a table tabulating the average power consumption of these
blocks (20%).

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EE8503/ELE863

VLSI Circuits and Systems for Data

Laboratory Project Manual

F. Yuan, PhD, PEng.

This laboratory design manual is an essential component of graduate

• Laboratory Project 1 : Wire channels (5%).

• Laboratory Project 2 : Continuous-time linear equalizers (5%).

• Laboratory Project 3 : Phase-locked loops (5%).

• Laboratory Project 4 : Pre-emphsis (5%).

• Laboratory Project 5 : Decision feedback equalizers (5%).

• Laboratory Project 6 : Clock and data recovery (5%).

• Laboratory Project 7 : Adaptive decision feedback equalizers (5%).

Laboratory 7 is mandatory for graduate students. It is optional for un-

Professor Fei Yuan

2 Continuous-Time Linear Equalizers 10

5 Decision Feedback Equalizers 35

6 Clock and Data Recovery 42

7 Adaptive Decision Feedback Equalizers 46

2.2 Current-Mode Driver

2.3 Wire Channel

Figure 1.1: Transmitter and wire channel.

various configurations such as π-network or T-network3 .

1. Time-domain response of the channel : Replace the PRBS gen-

2. Frequency-domain response of the channel : Terminate the T-

voltage across the termination resistors.

3. Eye diagram of the response of the channel : Activate the PRBS

1. Front matter (10%) :

• A cover page containing the name and student identification num-

2. Main body (80%):

• The schematic of the entire design (10%)

• Tabulate the dimension of all transistors, the parameters of the

amplifier. To achieve both a moderate gain at high frequencies and a small

Figure 2.1: Continuous-time linear equalizer.

Figure 2.2: Serial link with CTLE.

1. Frequency response of CTLE : Perform the frequency-domain of

2. Time-domain response serial link : Replace the PRBS generator

3. Eye diagram of the response : Activate the PRBS generator. The

1. Front matter (10%) :

• A cover page containing the name and student identification num-

2. Main body (80%):

• The schematic of the entire design (5%)

1.1 Voltage-Controlled Ring Oscillators

1. Design the 4-stage CMOS fully differential voltage-controlled ring os-

Figure 3.1: 4-stage voltage-controlled ring oscillator.

3. Frequency Tuning Curve : Use parametric analysis and calculator tools

1.2 Bang-Bang Phase Detector

Alexander phase detector shown in Fig.3.2 is a widely used bang-bang

Figure 3.2: Full-rate Alexander phase detector.

Figure 3.3: Half-rate Alexander phase detector.

1.3 Phase-Locked Loop

Figure 3.5: Basic configuration of type II phase-locked loops.

loops, namely the charge pump and the loop filter.

2.2 Loop Filters

Figure 3.6: Implementation of current-steering charge pump.

frequency voltages (voltage spikes) across R2 , which will in turn generate

2.3 Open-Loop Test of PLL

Figure 3.7: Open-loop test circuit.

2.4 Closed-Loop Test of PLL

• Loop filter : The bandwidth of the PLL is dictated by R2 and C2 of

1. Front matter (10%) :

• A cover page containing the name and student identification num-

2. Main body (80%)

• The schematic of the voltage-controlled oscillator and a table tab-

• Closed-loop test of PLL :The plot of the waveform of the con-

cj,k+1 = cj,k + hk vs,k , (7.1)

cj,k+1 = cj,k + hsign[k ]sign[vs,k ], (7.2)