A 2-10 GHz Digital CMOS Phase Shifter for Ultra-

Wideband Phased Array System

Dong-Woo Kang and Songcheol Hong

Dept. EECS, Korea Advanced Institute of Science and Technology (KAIST)

373-1, Guseong-dong, Yuseong-gu, Daejeon, 305-701, Republic of Korea

Abstract — This paper describes a digital true time-delay synthesized with lumped spiral inductors. An analog phase
phase shifter implemented in 0.18-µm CMOS process for shifter in SiGe was implemented a varactor loaded line
ultra-wideband phased array application. The phase shifter where both series and shunt elements are adjusted to
exhibits linear phase change versus frequency, digital control,
low insertion loss, and reduced circuit size. Shunt-series continuously vary the phase [5]. A multiband phase shifter
peaked load increases the bandwidth of the phase shifter, was designed by employing a distributed amplifier
yielding a flat gain response over a wide bandwidth. The between varactor-tuned LC networks [6]. However, the
fabricated circuit demonstrates a measured 157.5o phase overall performance of the phase shifters are limited by
tuning range in steps of 22.5o at 10 GHz. the low quality factors of varactors and inductors in
Index Terms — CMOS integrated circuit, phase shifters, silicon technology.
phased arrays.
This paper presents the design and development of a
digital distributed phase shifter in 0.18-µm CMOS process
I. INTRODUCTION for ultra-wideband phased array system. The proposed
phase shifter exhibits low insertion loss over an ultra-
An ultra-wideband system is an emerging solution for
wideband frequency band while maintaining a reduced
high-data rate broadband communication, high-resolution
circuit size and low power consumption.
radar, and precision-positioning fields. In a wideband
phased array antenna, a progressive phase shift between
successive radiating elements must be a linear function of II. CIRCUIT DESIGN
frequency in order to scan to be frequency insensitive over
a wide signal bandwidth [1]. This can be achieved through
the use of true time-delay phase shifters.
One of the easiest ways to implement a true time-delay
phase shifter is by using the switched delay-line technique.
However, many researchers have studied on the
distributed analog phase shifter with diode-loaded
(a)
transmission line due to its low power consumption and
low insertion loss. This technique has been demonstrated
using Schottky junction varactors [2],
microelectromechanical system (MEMS) bridges [3], or
thin-film ferroelectric barium strontium titanate (BST)
varactors [4]. A tunable delay line consists of a high-
impedance transmission line periodically loaded with (b)
voltage variable capacitors. By applying a single bias
voltage to varactors or MEMS bridges, the effective Fig. 1. (a) The distributed analog phase shifter (b) The digital
distributed capacitance of the synthetic transmission line distributed phase shifter
can be changed, which in turn changes the phase velocity, Fig.1 (a) shows a conventional varactor-loaded
and thus the associated time delay through the line. The transmission line phase shifter. The relative phase shift
major drawback of the distributed analog phase shifter is can be controlled by varying the capacitance C. At
the considerably large chip area. frequencies well below the Bragg frequency, the
In recent commercial silicon integrated circuit maximum possible differential phase shift of n T-sections
technologies, RF phase shifters can be developed using is given by [6]
loaded line where the required transmission line section is

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 ∆ φ = 2 π f 0 n L ( C max − C min ).
where Cmin and Cmax are the minimum and maximum
capacitance of the varactor, respectively, and fo represents
the center frequency. The phase control range is limited by
a given capacitance tuning ratio. Furthermore, as the
capacitance of the varactor varies, the characteristic
impedance Zo changes and is given by
L L
Z0 max = Z0 min =
C min C max
This indicates that there is trade off between the matching
performance and the amount of phase per section.
Fig.1 (b) shows the concept of the digital distributed
phase shifter [7]. Note that the series inductance and shunt
capacitance are fixed value. The input signal propagates
along the artificial transmission line. By tailoring the
voltage across each capacitor in succession, the phase shift
is incremented by the steps of the single-section phase
shift while maintaining a good matching performance. The
maximum possible differential phase shift of n T-sections
can be written as
∆ φ = 2 π f 0 ( n − 1 ) LC .
We can see that the phase tuning range increases with the
section number n. Even if the differential phase shift
varies, the characteristic impedance of the artificial
transmission line is constant, resulting in a good matching
performance.
For circuit implementation, the phase selection in
parallel is realized by the distributed active switch using a
cascode MOSFET as shown in Fig.2 [7].
A single T section consists of series inductances and gate
capacitance of common source MOSFET. The cascode
MOSFET operates as active switches, as the gate bias (Vp)
Fig. 2. The schematic of a single T-section.
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(1)
(a) (b)
. (2)
Fig. 3. (a) Shunt and series peaking load (b) Simplified
model
of the common gate MOSFET can be used as an effective
means of switching between VDD and GND. Moreover, it
provides high gain, high output resistance, and high
reverse isolation.
In general, shunt-peaking is a form of bandwidth
enhancement in which a one-port network is connected
between the amplifier proper and the capacitive load. In
case of shun-peaking, the maximum bandwidth is 2
times that of the uncompensated case [8]. To increase the
bandwidth, a series inductor can be inserted between a
shunt peaking inductor and a capacitive load. Fig.3 (a)
shows the output of phase shifter with shunt-series
(3) peaking load. A series inductor (L2) is added between the
output of phase shifter and the rest of the network. Fig.3
(b) shows the simplified model for small signals. The
capacitance C1 represents the loading on the output node
of the distributed phase shifter. The capacitance C2 is the
input capacitance of a subsequent stage. Compared to an
ordinary shunt-peaked topology, the combination of shunt
and series peaking can provide three distinct resonance
frequencies, thereby improving the bandwidth of the phase
shifter by a factor of 2 3 [9].
Fig. 4. Schematic of a 3-bit distributed phase shifter
396
 Fig.4 shows the schematic of the proposed phase shifter.
An RF signal applied at the input end of the gate line
travels down the artificial transmission line to the
terminating resistor. The input signal sampled by the gate
circuits at different phases is transferred to the drain load
through the activated cascode cell. The differential phase
shift can be obtained by selecting one of the active
cascode switches in parallel. Because the artificial line has
lossy components, which are series resistance and shunt
conductance, the gate voltage throughout the gate line will
unequally excite the gates of common gate MOSFETs.
This results in a significant loss variation of the phase
shifter between each state. In order to minimize the state-
Fig. 6 Measured relative phase response.
to-state loss variation, the size of common gate MOSFET
must increase as the differential phase shift increases.
The drain of each active switch is combined with binary
tree to maintain a same time delay. Hence, the relative
phase shift is only dependent on the input artificial
transmission line. The output of the binary tree is
connected to shunt-series peaked load. A second stage is
common source amplifier with shunt peaking inductor in
order to enhance the overall gain. A source follower is
used as an active buffer for wideband output matching.
o
In this design, the LSB of the phase shifter is 22.5 . The
o o
circuit provides eight phase states between 0 and 157.5 in
o
increments of 22.5 at the design frequency of 10 GHz. Fig. 7 Measured gain response.
For a 50 Ω port impedance and a design frequency of 10
GHz, capacitance Cgs and inductance Lg are determined as
0.125 pF and 0.312 nH, respectively.

III. FABRICATION AND MEASUREMENT

The proposed 3-bit distributed phase shifter was
fabricated using TSMC’s 0.18-µm CMOS technology,

Fig. 8 Measured input return losses.

Fig. 9 Measured output return losses.

Fig. 5 The chip photograph of the proposed phase which provides one poly layer for the gate of the
shifter. MOSFET and six metal layers for inter-connection. The

397
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circuit draws a maximum 16 mA dc current from a 1.8 V
power supply; thus, the maximum power consumption is
28.8 mW. The 3-bit distributed phase shifter is biased at
Vg=0.9 V with the drain current varying from 5.7 mA to
6.0 mA. The gate bias of the common gate MOSFET is
toggled between 0 V and 1.8 V. The gate biases of second
stage amplifier and source follower are 0.75 V and 0.7 V,
respectively. The die photograph is shown in Fig. 5. The
total die area is 1.3 mm × 1.2 mm.
Fig.6 shows the measured phase responses of the phase
shifter. The differential phase shift increases linearly as
frequency increases. Phase errors are mainly caused by
inaccuracy of a microstrip line. Fig. 7 shows measured
insertion gain for the eight states. Over 2 to 9 GHz, the
gain is better than -2 dB. Fig. 8 shows the input return
losses. The input return losses of all states are below -15
dB. The output return losses are less than -7 dB as shown
in Fig. 9. In the Fig. 10 and the Fig. 11, RMS phase error
o
exhibits less than 4.5 and RMS amplitude error is less
than 0.42 dB.
Fig. 10 Measured RMS Phase Error
Fig. 11 Measured RMS Amplitude Error
398
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IV. CONCLUSION
This paper presents a 3-bit distributed phase shifter
using 0.18-µm CMOS technology. The phase shifter
exhibits a linear phase change versus frequency with a
purely digital control. The shunt-series peaked load
provides a relatively flat gain response over wideband
frequency ranges. The measured gain is better than -2 dB
o
from 2 to 9 GHz. The maximum phase shift is 157.5 in
o
steps of 22.5 at 10 GHz. The proposed phase shifter can
be used in time-delay phased arrays, especially those
covering a wide bandwidth.
ACKNOWLEDGEMENT
This work was supported in part by the Agency for
Defense Development, Korea, through the Radio
Detection Research Center at Korea Advanced Institute of
Science and Technology.
REFERENCES
[1] S. K. Koul and B. Bhat, Microwave and Millimeter Wave
Phase Shifters, Boston: Artech House, 1991, ch.1
[2] A. S. Nagra and R. A. York, “Distributed analog phase
shifters with low insertion loss,” IEEE Trans. Microw.
Theory Tech., vol. 47, no. 9, pp. 1705-1711, Sep. 1999.
[3] N. S. Barker, and G. M. Rebeiz, “ Distributed MEMS true-
time delay phase shifters and wideband switches,” IEEE
Trans. Microw. Theory Tech., vol. 46, no. 11, pp. 1881-
1890, Nov. 1998.
[4] D. Kuylenstierna, A. Vorobie, P. Linner, and S. Gevorgian,
“Ultrawide-band Tunable True-Time Delay Lines using
Ferroelectric varactors,” IEEE Trans. Microw. Theory Tech.,
vol. 53, no. 6, pp. 2164-2170, June, 2005.
[5] T. M. Hancock and G. M. Rebeiz, “A 12-GHz SiGe Phase
Shifter with integrated LNA,” IEEE Trans. Microw. Theory
Tech., vol. 53, no. 3, pp. 977-983, Mar. 2005.
[6] C. Lu, A. –V. Pham, and D. Livezey, “Development of
Multiband Phase Shifters in 180-nm RF CMOS Technology
with Active Loss Compensation,” IEEE Trans. Microw.
Theory Tech., vol. 54, no. 1, pp. 40-45, Jan. 2006.
[7] D.-W. Kang and S. Hong, “A 4-Bit CMOS Phase Shifter
using Distributed Active Switches,” IEEE Trans. Microw.
Theory Tech., submitted.
[8] T. H. Lee, The Design of CMOS Radio-Frequency
Integrated Circuits, Cambridge University Express, 2004,
ch. 9.
[9] S. Galal and B. Razavi, “40-Gb/s Amplifier and ESD
Protection Circuit in 0.18-um CMOS Technology,” IEEE J.
Solid-State Circuits, vol. 39, no. 12, pp. 2389-2396, Dec.
2004.