A B C D E

1 1

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Compal Confidential

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x
2 2

Z5WAE Schematics Document

fi
AMD "Beema" Platform

a
AMD 25W APU With Puma+ Core and 25W DGPU with Jet

in
LA-B231P REV: 1.0
3

h
2014-03-27
3
.c
w
w
w

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
COVER PAGE
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 1 of 45
A B C D E
 A B C D E

Compal Confidential
Model Name : Z5WAE
1 1

GFX*4
DGPU
JET With DDR3*4

m
Reserve OPAL With DDR3*8 204pin DDRIII-SO-DIMM X2
Display Port
AMD Memory BUS(DDR3) Single Channel

1.5V DDRIII 1600MHz

BANK 0, 1, 2
Port 1 Port 0

o
HDMI Conn. eDP Conn. Beema USB2.0

.c
Port 0,1 Port 2 Port 3 Port 5
VGA DAC
Sub/B WLAN USB Touch
2
2.0 Conn. BT Combo Camera Screen 2

AMD FT3b APU

x
USB3.0
CRT Conn.
Puma+ Core Port 0

fi
PCIE MB Port 8
BGA 769-balls
3.0 Conn.
GPP2 GPP1

a
HD Audio(AZ)
LAN+Card Reader
MINI Card
RTL8411B
(WLAN/BT)
SATA III

in
3
Port 0 Port 1 3

SPI LPC Audio

HDD/ Colay HDD Cable ODD ALC283-CG
Transformer Card Reader
Conn. Conn.
RJ45 Conn. BIOS (8M) h ENE
.c
Share ROM
KBC9022 Discrete TPM
Sub-borad

Digital MIC Int. MIC Int. Speaker Combo Jacks

Power/B
w

Int.KBD Touch Pad Conn.

4 4
w

USB/B Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BLOCK DIAGRAMS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
w

B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 2 of 45
A B C D E
 5 4 3 2 1

RAM DDRIII SODIMMX2

+1.5V VDD_MEM 8A
AMD APU FT3 Kabini (25W)

+0.75VS VTT_MEM 2A
D D

B+ +APU_CORE +0.5~+1.4V VDDCR_CPU @ 21A(EDC)

AC ADAPTOR VIN PU201
19V 65W CHARGER PU901
ISL6277HRTZ-T

m
BQ24725ARGRR +APU_CORE_NB
+0.7~1.325V VDDCR_NB @ 17A(EDC)

BATT+
+1.5V

o
+1.5V VDDIO_MEM_S @ 3A
BATTERY PU501
RT8207MZQW +0.75VS +1.5VS
Q20 +1.5VS VDDIO_AZ_ALW @ 0.1A

.c
LP2301ALT1G
CRT / HDMI
VDD_095_USB3_Dual @ 1A
+5VS +0.95VALW
C +5VS_DISP VDD_095_ALW @ 0.5A C

+0.95VALW +0.95VS VDD_095 @ 5A

x
PU1 +0.95VS
HDD x1 SY8208DQNC U3 VDD_095_GFX @ 0.6A
ODD x1 TPS22966DPUR
+5VS

fi
+5VS_HDD @ 1.1A +1.8VS VDD_18 @ 1.5A
+5VS_ODD @ 2A +1.8VS
PU601 +1.8VALW
SY8033BDBC
Audio +1.8VALW VDD_18_ALW @ 0.5A
ALC259-VC2-CG

a
+5VDDA_CODEC
+5VS
+5VS_PVDD +3VS +3VALW
PU401 +3VALW VDD_33_ALW @ 0.2A
+3VDD_CODEC +1.5VS SY8208BQNC

in
+IOVDD_CODEC
+3VS
+3VS VDD_33 @ 0.2A
B EC U2 B
FAN TPS22966DPUR +5VS
+3VLP +1.5V_RTC VDDBT_RTC_G @ 4.5uA
+VCC_FAN +5VS +EC_VCC
+3VALW

USB2.0 x2
USB3.0 x1
LCD panel
14"
h
PU402
SY8208BQNC
U1895
TPS22966DPUR
U74
AP2821
+RTC_APU
+RTCBATT
.c
B+ PU101 RTC
+USB3_VCCA +5VALW +INVPWR_B+ +0.95VSDGPU +1.8VSDGPU +3VSDGPU NCP698SQ15T1G
+LCDVDD @ 1.4A Bettary
+3VS
PU101 +1.5VSDGPU
TPS51212
LAN/CR Combo
RTL8411-CG HD Camera
w

VGA JET
+3V_LAN @ 1A +3VALW +3VS_CMOS +3VS PU1201 +VGA_CORE
A ISL6288 A
w

Mini Card (WLAN) Touch Screen

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

+3VS_WLAN @ 2A
+3VS +5VS_TS POWER MAP
+5VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
+1.5VS Document Number Rev
+1.5VS
w

B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 3 of 45
5 4 3 2 1
 A B C D E

Board ID / SKU ID Table for AD channel

Voltage Rails
BOARD ID Table
Power Plane Description S0 S3 S5
Board ID PCB Revision
VIN Adapter power supply (19V) ON ON ON
0 EVT
B+ AC or battery power rail for power circuit. ON ON ON
1 DVT
+APU_CORE Core voltage for APU ON OFF OFF
2 PVT
1
+APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF 1
3
+0.95VALW 0.95V always on power rail ON ON ON
4
+0.95VS 0.95V switched power rail ON OFF OFF
5
+1.8VALW 1.8V always on power rail ON ON ON

m
6
+1.8VS 1.8V switched power rail ON OFF OFF
7
+1.5V 1.5V power rail for APU and DDR ON ON OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF

o
+3VALW 3.3V always on power rail ON ON ON
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON

.c
+5VS 5V switched power rail ON OFF OFF
+RTC_APU RTC power ON OFF OFF
+3VSDGPU VGA power ON OFF OFF
+1.8VSDGPU VGA power ON OFF OFF
+1.5VSDGPU VGA power ON OFF OFF

x
2
+0.95VSDGPU VGA power ON OFF OFF 2

+VGA_CORE VGA power ON OFF OFF

fi
BOM Structure Table
SMBus List SIGNAL
BOM Structure BTO Item STATE SLP_S3# SLP_S5# +VALW +V +VS Clock
EC SMBus Port1 (+3VALW) EC SMBus Port2 (+3VS) @ Unpop

a
Full ON HIGH HIGH ON ON ON ON
CONN@ Connector part control by ME
Device Address HEX Device Address HEX
EMI@ EMI pop component S1(Power On Suspend) HIGH HIGH ON ON ON LOW
Smart Battery 0001 011X b 16H SB-TSI (APU) 1001 100X b 98H @EMI@ EMI unpop component

in
S3 (Suspend to RAM) HIGH HIGH ON ON OFF OFF
ESD@ ESD pop component
VGA Temp. 41H
@ESD@ ESD unpop component S4 (Suspend to Disk) LOW HIGH ON OFF OFF OFF
AL@ Auto Load EC ROM
S5 (Soft OFF) LOW LOW ON OFF OFF OFF
RS@ R-short
JP@ Jump
APU POWER SEQUENCE
3
APU SMBus Port0 (+3VS) APU SMBus Port1(+3VALW)
Device Address HEX Device Address HEX
TP@
SP@
1DMIC@
h Test point
Short pad for clear CMOS
Use 1 DMIC
G-A +RTC
3
.c
2DMIC@ Use 2 DMIC
DDR DIMM1 1010 000Xb A0H EC_ON
45@ HDMI royalty
G-B +3VALW/+5VALW
DDR DIMM2 1010 001Xb A2H 9012@ Use KBC9012
9022@ Use KBC9022
Mini Card (DNI) +1.8VALW
A6@ Use A6 APU
+0.95VALW
E1@ Use E1 APU
w

SYSON
BL@ Keyboard backlight
ZZZ ZZZ UAPU1 A6@ UAPU1 E1@ G-C +1.5V
TPM@ Use discrete TPM module
SUSP#
X7681@
TPUSB@ Use USB to I2C IC for T/P
G-D +3VS
w

TPSM@ Use APU SMBus for T/P

PCB X76550BOL81 APU APU +1.8VS
Part Number = DA60014I000 HYN 128M16*4 Part Number = SA00007R900 Part Number = SA00007RC00 VGA@ Have discrete graphic
PCB 157 LA-B231P REV0 M/B 2 S IC A6-6310 AM6310ITJ44JB 1.8G BGA 769P S IC E1-6010 EM6010IUJ23JB 1.35G BGA769P +1.5VS
ZZZ
MARS@ Use Opal
ZZZ UAPU1 A4@ UAPU1 E2@ +0.95VS
JET@ Use Jet
X7682@ VR_ON
w

4 128@ Dual channel VRAM,pop with MARS@ 4

G-E +APU_CORE
X76550BOL82 X76@ VRAM type select,control by X76XX@
HDMI_ROYALTY MIC 128M16*4 APU APU +APU_CORE_NB
ROYALTY HDMI W/LOGO+HDCP Part Number = SA00007RA00 Part Number = SA00007RB00
X76XX@ VRAM type select, control level X76
RO0000003HM ZZZ S IC A4-6210 AM6210ITJ44JB 1.8G BGA 769P S IC E2-6110 EM6110ITJ44JB 1.5G BGA 769P
45@
U44 9022@ U75 JET@ re check
X7683@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title
X76550BOL83 NOTES LIST
SAM 128M16*4 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC VGA Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
Part Number = SA000075S20 Part Number = SA000079010 B 1.0
S IC KB9022QC LQFP 128P EC CONTROLLER, A.3 S IC 216-0856000 A0 JET XT M2 FCBGA ABO!,
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 4 of 45
A B C D E
 5 4 3 2 1

@
UAPU1A
<10,11> DDRAB_SMA[15..0] DDRAB_SDQ[63..0] <10,11>
MEMORY
DDRAB_SMA0 AG38 M_ADD0 M_DATA0 B30 DDRAB_SDQ0
DDRAB_SMA1 W35 M_ADD1 M_DATA1
A32 DDRAB_SDQ1
DDRAB_SMA2 W38 M_ADD2 M_DATA2 B35 DDRAB_SDQ2
DDRAB_SMA3 W34 M_ADD3 M_DATA3
A36 DDRAB_SDQ3 @
DDRAB_SMA4 U38 B29 DDRAB_SDQ4 UAPU1B
M_ADD4 M_DATA4
DDRAB_SMA5 U37 M_ADD5 M_DATA5 A30 DDRAB_SDQ5 PCIE
DDRAB_SMA6 U34 A34 DDRAB_SDQ6
D M_ADD6 M_DATA6 D
DDRAB_SMA7 R35 M_ADD7 M_DATA7 B34 DDRAB_SDQ7
DDRAB_SMA8 R38 R10 L2
M_ADD8 P_GPP_RXP0 P_GPP_TXP0
DDRAB_SMA9 N38 B37 DDRAB_SDQ8 R8 L1
M_ADD9 M_DATA8 P_GPP_RXN0 P_GPP_TXN0
DDRAB_SMA10 AG34 M_ADD10 M_DATA9 A38 DDRAB_SDQ9
DDRAB_SMA11 R34 M_ADD11 M_DATA10
D40 DDRAB_SDQ10 R5
P_GPP_RXP1 P_GPP_TXP1
K2 PCIE_ATX_DRX_P1 C19 1 2 .1U_0402_16V7K
<23> PCIE_ARX_DTX_P1 PCIE_ATX_C_DRX_P1 <23>
DDRAB_SMA12 N37 M_ADD12 M_DATA11 D41 DDRAB_SDQ11 R4 P_GPP_RXN1 LAN P_GPP_TXN1 K1 PCIE_ATX_DRX_N1 C20 1 2 .1U_0402_16V7K
<23> PCIE_ARX_DTX_N1 PCIE_ATX_C_DRX_N1 <23>

m
DDRAB_SMA13 AN34 M_ADD13 M_DATA12
B36 DDRAB_SDQ12
DDRAB_SMA14 L38 M_ADD14 M_DATA13
A37 DDRAB_SDQ13 N5
P_GPP_RXP2
J2 PCIE_ATX_DRX_P2 C17 1 2 .1U_0402_16V7K
<26> PCIE_ARX_DTX_P2 P_GPP_TXP2 PCIE_ATX_C_DRX_P2 <26>
DDRAB_SMA15 L35 M_ADD15 M_DATA14 B41 DDRAB_SDQ14 N4 P_GPP_RXN2 WLAN J1 PCIE_ATX_DRX_N2 C18 1 2 .1U_0402_16V7K
C40 <26> PCIE_ARX_DTX_N2 P_GPP_TXN2 PCIE_ATX_C_DRX_N2 <26>
M_DATA15 DDRAB_SDQ15
AJ38 M_BANK0 N10 P_GPP_RXP3 P_GPP_TXP3 H2
<10,11> DDRAB_SBS0# AG35 F40 +0.95VS_APU_GFX N8 H1 +0.95VS_APU_GFX
M_BANK1 M_DATA16 DDRAB_SDQ16 P_GPP_RXN3 P_GPP_TXN3
<10,11> DDRAB_SBS1# N34 F41
M_BANK2 M_DATA17 DDRAB_SDQ17
<10,11> DDRAB_SBS2#

o
M_DATA18 K40 DDRAB_SDQ18 1 2 P_TX_ZVDD_095 W8 P_TX_ZVDD_095 W7 P_RX_ZVDD_095 2 1
<10,11> DDRAB_SDM[7..0] B32 K41 P_RX_ZVDD_095
DDRAB_SDM0 M_DM0 M_DATA19 DDRAB_SDQ19 R404 R73
DDRAB_SDM1 B38 M_DM1 M_DATA20 E40 DDRAB_SDQ20 1.69K_0402_1% 1K_0402_1%
DDRAB_SDM2 G40 E41 DDRAB_SDQ21
M_DM2 M_DATA21
DDRAB_SDM3 N41 J40 DDRAB_SDQ22 PEG_GTX_C_ARX_P0 L5 G2 PEG_ATX_GRX_P0
M_DM3 M_DATA22 P_GFX_RXP0 P_GFX_TXP0
DDRAB_SDM4 AG40 J41 DDRAB_SDQ23 PEG_GTX_C_ARX_N0 L4 P_GFX_TXN0 G1 PEG_ATX_GRX_N0

.c
M_DM4 M_DATA23 P_GFX_RXN0
DDRAB_SDM5 AN41
M_DM5
DDRAB_SDM6 AY40 M_DM6 M_DATA24 M41 DDRAB_SDQ24 PEG_GTX_C_ARX_P1 J5 P_GFX_RXP1 P_GFX_TXP1 F2 PEG_ATX_GRX_P1
DDRAB_SDM7 AY34 N40 DDRAB_SDQ25 PEG_GTX_C_ARX_N1 J4 F1 PEG_ATX_GRX_N1
M_DM7 M_DATA25 P_GFX_RXN1 P_GFX_TXN1
Y40 T41 DDRAB_SDQ26
M_DM8 M_DATA26
M_DATA27 U40 DDRAB_SDQ27 PEG_GTX_C_ARX_P2 G5 P_GFX_RXP2 P_GFX_TXP2 E2 PEG_ATX_GRX_P2
C C
B33 L40 DDRAB_SDQ28 PEG_GTX_C_ARX_N2 G4 E1 PEG_ATX_GRX_N2
<10,11> DDRAB_SDQS0 M_DQS_H0 M_DATA28 P_GFX_RXN2 P_GFX_TXN2
A33 M_DQS_L0 M_DATA29 M40 DDRAB_SDQ29
<10,11> DDRAB_SDQS0# B40 R40 D7 D2
M_DQS_H1 M_DATA30 DDRAB_SDQ30 PEG_GTX_C_ARX_P3 P_GFX_RXP3 P_GFX_TXP3 PEG_ATX_GRX_P3
<10,11> DDRAB_SDQS1

x
A40 T40 DDRAB_SDQ31 PEG_GTX_C_ARX_N3 E7 D1 PEG_ATX_GRX_N3
<10,11> DDRAB_SDQS1# M_DQS_L1 M_DATA31 P_GFX_RXN3 P_GFX_TXN3
H41 M_DQS_H2
<10,11> DDRAB_SDQS2 H40 AF40
M_DQS_L2 M_DATA32 DDRAB_SDQ32
<10,11> DDRAB_SDQS2#
P41 M_DQS_H3 M_DATA33 AF41 DDRAB_SDQ33
<10,11> DDRAB_SDQS3 P40 AK40 <12> PEG_GTX_C_ARX_P[0..3] PEG_ATX_GRX_P[0..3] <12>
M_DQS_L3 M_DATA34 DDRAB_SDQ34
<10,11> DDRAB_SDQS3# <12> PEG_GTX_C_ARX_N[0..3] PEG_ATX_GRX_N[0..3] <12>

fi
AH41 AK41 DDRAB_SDQ35 FT3_BGA_769P-T_A39
<10,11> DDRAB_SDQS4 M_DQS_H4 M_DATA35
AH40 M_DQS_L4 M_DATA36 AE40 DDRAB_SDQ36 Part Number =
<10,11> DDRAB_SDQS4# AP41 AE41
M_DQS_H5 M_DATA37 DDRAB_SDQ37
<10,11> DDRAB_SDQS5
AP40 M_DQS_L5 M_DATA38 AJ40 DDRAB_SDQ38
<10,11> DDRAB_SDQS5# BA40 AJ41
M_DQS_H6 M_DATA39 DDRAB_SDQ39
<10,11> DDRAB_SDQS6 AY41
<10,11> DDRAB_SDQS6# M_DQS_L6
AY33 M_DQS_H7 M_DATA40 AM41 DDRAB_SDQ40
<10,11> DDRAB_SDQS7

a
BA34 AN40 DDRAB_SDQ41
<10,11> DDRAB_SDQS7# M_DQS_L7 M_DATA41
AA40 M_DQS_H8 M_DATA42 AT41 DDRAB_SDQ42
Y41 AU40 DDRAB_SDQ43
M_DQS_L8 M_DATA43
AL40 DDRAB_SDQ44
M_DATA44
AC35 M_CLK_H0 M_DATA45 AM40 DDRAB_SDQ45
<10> DDRA_CLK0 AC34 AR40 DDRAB_SDQ46

in
<10> DDRA_CLK0# M_CLK_L0 M_DATA46
AA34 M_CLK_H1 M_DATA47 AT40 DDRAB_SDQ47
<10> DDRA_CLK1 AA32
<10> DDRA_CLK1# M_CLK_L1
B AE38 AV41 DDRAB_SDQ48 B
<11> DDRB_CLK0 M_CLK_H2 M_DATA48
AE37 M_CLK_L2 M_DATA49 AW40 DDRAB_SDQ49
<11> DDRB_CLK0# AA37 BA38 DDRAB_SDQ50
<11> DDRB_CLK1 M_CLK_H3 M_DATA50
AA38 M_CLK_L3 M_DATA51 AY37 DDRAB_SDQ51
<11> DDRB_CLK1# AU41 DDRAB_SDQ52
<10,11> MEM_MAB_RST#
G38
M_RESET_L
M_DATA52
M_DATA53
AV40 DDRAB_SDQ53 MEMORY VREF
<10,11> MEM_MAB_EVENT#

<10> DDRA_CKE0
<10> DDRA_CKE1
<11> DDRB_CKE0
AE34

L34
J38
J37
J34
M_EVENT_L

M0_CKE0
M0_CKE1
M1_CKE0
M_DATA54
M_DATA55

M_DATA56
M_DATA57
AY39 DDRAB_SDQ54
AY38 DDRAB_SDQ55

BA36
AY35
BA32
DDRAB_SDQ56
DDRAB_SDQ57
DDRAB_SDQ58
h +1.5V

1
2
RP2
8
7
+MEM_VREF
.c
<11> DDRB_CKE1 M1_CKE1 M_DATA58
AY31 DDRAB_SDQ59 3 6 MEM_MAB_EVENT#
M_DATA59
AN38 M0_ODT0 M_DATA60 BA37 DDRAB_SDQ60 4 5 1 2
<10> DDRA_ODT0 AU38 AY36
M0_ODT1 M_DATA61 DDRAB_SDQ61
<10> DDRA_ODT1 AN37 BA33
M1_ODT0 M_DATA62 DDRAB_SDQ62 1K_0804_8P4R_1% C337 C163
<11> DDRB_ODT0
AR37 M1_ODT1 M_DATA63 AY32 DDRAB_SDQ63 1U_0402_6.3V6K .1U_0402_16V7K
<11> DDRB_ODT1 2 1
AJ34 M0_CS_L0 M_CHECK0 V41
<10> DDRA_SCS0# AR38 W40
<10> DDRA_SCS1# M0_CS_L1 M_CHECK1
w

AL38 AB40
<11> DDRB_SCS0# M1_CS_L0 M_CHECK2
AN35 M1_CS_L1 M_CHECK3 AC40
<11> DDRB_SCS1# U41
M_CHECK4
AJ37 M_RAS_L M_CHECK5 V40 M_ZVDDIO 1 2
<10,11> DDRAB_SRAS# AL34 AA41 +1.5V
A
M_CAS_L M_CHECK6 R74 A
<10,11> DDRAB_SCAS# AL35 AB41
M_WE_L M_CHECK7 39.2_0402_1%
<10,11> DDRAB_SWE#
w

AD40
+MEM_VREF
T33 APU_VREFDQ AC38
M_VREF
M_VREFDQ M_ZVDDIO_MEM_S AD41 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

FT3_BGA_769P-T_A39
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P05-FT3 MEMORY INTERFACE/PCIE
Part Number = AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
w

B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 5 of 45
5 4 3 2 1
 A B C D E

@
UAPU1C
DISPLAY/SVI2/JTAG/TEST
A9 TDP1_TXP0 DP_150_ZVSS B16 DP_150_ZVSS R401 1 2 150_0402_1%
<21> APU_DP1_P0
B9 TDP1_TXN0 DP_2K_ZVSS A21 DP_2K_ZVSS R400 1 2 2K_0402_1%
<21> APU_DP1_N0 B17
DP_BLON ENBKL <22>
A10 TDP1_TXP1 DP_DIGON A17
<21> APU_DP1_P1 B10 TDP1_TXN1 A18 ENVDD <19>
DP_VARY_BL
<21> APU_DP1_N1 INVTPWM <19>
HDMI
A11 TDP1_TXP2
<21> APU_DP1_P2 B11 TDP1_TXN2 D17
TDP1_AUXP
1 <21> APU_DP1_N2 HDMI_CLK <21> 1
TDP1_AUXN E17
A12 TDP1_TXP3 HDMI_DATA <21>
<21> APU_DP1_P3 B12 TDP1_TXN3 H19
TDP1_HPD
<21> APU_DP1_N3 HDMI_HPD <21>
A4 LTDP0_TXP0 LTDP0_AUXP D15
<19> EDP_TXP0 EDP_AUXP <19>
B4 LTDP0_TXN0 LTDP0_AUXN E15 RP23
<19> EDP_TXN0

m
EDP_AUXN <19> DAC_RED 1 8
A5 LTDP0_TXP1 LTDP0_HPD H17 DAC_GRN 2 7
<19> EDP_TXP1 EDP_HPD <19>
B5 LTDP0_TXN1 DAC_BLU 3 6
<19> EDP_TXN1 B14 4 5
DAC_RED
DAC_RED <20>
eDP A6 LTDP0_TXP2
B6 LTDP0_TXN2 DAC_GREEN A14 150_0804_8P4R_1%
DAC_GRN <20>
CRT

o
A7 LTDP0_TXP3 DAC_BLUE B15
B7 LTDP0_TXN3 DAC_BLU <20>
+3VS
DAC_HSYNC G19
K15 DISP_CLKIN_H E19 DAC_HSYNC <20>
DAC_VSYNC R115 1 2 1K_0402_5%
DAC_VSYNC <20>
H15 DISP_CLKIN_L DAC_HSYNC R113 1 2 1K_0402_5%

.c
DAC_SCL D19 NOTE: @
DAC_DDC_CLK <20>
R674 1 2 33_0402_5% APU_SVT_R G31 SVT DAC_SDA D21 DAC_HSYNC
<39> APU_SVT DAC_DDC_DATA <20>
R669 1 2 33_0402_5% APU_SVC_R D27 SVC
<39> APU_SVC
R670 1 2 33_0402_5% APU_SVD_R E29 SVD DAC_ZVSS A16 DAC_ZVSS R416 1 2 499_0402_1% PU FOR HDMI ENABLE
<39> APU_SVD PD FOR CUSTOMER (DNI)
2 2
B22 SIC THERMDA H27 APU_TEST4
<13,22> EC_SMB_CK2 T13
B21 SID THERMDC H29 APU_TEST5 T14 @
<13,22> EC_SMB_DA2 D25
DIECRACKMON RP7

x
APU_RST# B20 APU_RST_L BP0 A27 APU_TEST14 APU_TEST16 1 8
R117 1 RS@ 2 0_0402_5% LDT_RST# A20 LDT_RST_L BP1 B27 APU_TEST15 APU_TEST17 2 7
BP2 A26 APU_TEST16 APU_TEST14 3 6
APU_PWRGD B19 APU_PWROK BP3 B26 APU_TEST17 APU_TEST15 4 5
<39> APU_PWRGD +1.8VS
R118 1 RS@ 2 0_0402_5% LDT_PWRGD A19 LDT_PWROK PLLTEST1 B28 APU_TEST18

fi
PLLTEST0 A28 APU_TEST19 1K_0804_8P4R_5%
R120 1 RS@ 2 0_0402_5% APU_PROCHOT# A22 PROCHOT_L BYPASSCLK_H B24 APU_TEST25_H R19 1 2 511_0402_1% +1.8VS
<22,39,7> PROCHOT# B18 ALERT_L A24 APU_TEST25_L 1 2 511_0402_1%
APU_ALERT# BYPASSCLK_L R18 @
PLLCHRZ_H AV35 APU_TEST28_H T4 RP3
APU_TDI D29 TDI PLLCHRZ_L AU35 APU_TEST28_L APU_TEST36 1 8
T5
APU_TDO D31 TDO M_TEST E33 APU_TEST31 APU_TEST37 2 7
T6
APU_TCK D35 TCK APU_TEST36 3 6

a
APU_TMS D33 TMS FREE_2 A29 APU_TEST34_L APU_TEST37 4 5
T7
APU_TRST# G27 TRST_L GIO_TSTDTM0_SERIALCLK H21 APU_TEST36
APU_DBRDY B25 DBRDY GIO_TSTDTM0_CLKINIT H25 APU_TEST37 1K_0804_8P4R_5%
APU_DBREQ# A25 DBREQ_L
USB_ATEST0 AJ10 APU_TEST42 T10 APU_TEST35 R114 1 @ 2 1K_0402_5%
D23 VDDCR_NB_SENSE USB_ATEST1 AJ8 APU_TEST43

in
<39> APU_VDDNB_SEN T8
G23 VDDCR_CPU_SENSE M_ANALOGIN R32 APU_TEST39 T9
<39> APU_VDD_SEN E25 N32
VDDIO_MEM_S_SENSE M_ANALOGOUT APU_TEST40
3 <39> APU_VDD_RUN_FB_L
E23 VSS_SENSE TMON_CAL AP29 APU_TEST41
T11
T12 +1.8VS
HDT+ 3

AV33 VDD_095_FB_H HDMI_EN/DP_STEREOSYNC E21 APU_TEST35 JHDT1 @

AU33 VDD_095_FB_L 1 2 APU_TCK_R 1 @ESD@ 2 APU_TCK
1 2 R664 0_0402_5%
3 4 APU_TMS_R 1 @ESD@ 2 APU_TMS +1.8VS
3 4

FT3_BGA_769P-T_A39
Part Number =
h APU_TRST# 1 @ESD@ 2 APU_TRST#_R
5

9
5

7
6

8
6

10
APU_TDI_R

APU_TDO_R
R663

R662

R671
0_0402_5%
1 @ESD@ 2 APU_TDI
0_0402_5%
1 @ESD@ 2 APU_TDO
0_0402_5%
APU_PWRGD_R 1 @ESD@ 2 APU_PWRGD
APU_TDI
APU_TMS
APU_TCK
APU_DBREQ#
1
2
3
4
RP6
8
7
6
5
.c
+3VS APU_PWRGD 1 2 9 10
Close To PU801 @ESD@ R666 0_0402_5% R667 0_0402_5%
RP4 C1272 100P_0402_50V8J RP11 HDT_P11 11 12 APU_RST#_R 1 @ESD@ 2 APU_RST# 1K_0804_8P4R_5%
APU_ALERT# 1 8 1 8 11 12 R672 0_0402_5%
EC_SMB_DA2 2 7 Close To APU's Pin APU_PWRGD 1 2 ESD@ 2 7 HDT_P13 13 14 APU_DBRDY_R 1 @ESD@ 2 APU_DBRDY
APU_PROCHOT# 3 6 C1270 10P_0402_50V8J 3 6 13 14 R673 0_0402_5% RP8 +1.8VS
EC_SMB_CK2 4 5 APU_RST# 1 2 ESD@ 4 5 HDT_P15 15 16 APU_DBREQ#_R 1 @ESD@ 2 APU_DBREQ# 1 8
C1273 10P_0402_50V8J 15 16 R665 0_0402_5% APU_TRST# 2 7
1K_0804_8P4R_5% APU_PROCHOT# 1 2 @ESD@ 10K_0804_8P4R_5% 17 18 APU_TEST19 APU_TEST19 3 6
17 18
w

C1276 100P_0402_50V8J APU_TEST18 4 5

APU_ALERT# 1 2 @ESD@ 19 20 APU_TEST18
C1277 100P_0402_50V8J 19 20 1K_0804_8P4R_5%

4
PU +1.8VS @ +1.8VS 4
RP5 SAMTE_ASP-136446-07-B
APU_SVT_R 1 8
w

APU_SVC_R 2 7
APU_SVD_R 3 6 Security Classification Compal Secret Data Compal Electronics, Inc.
4 5 2014/03/27 2016/03/27 Title
Issued Date Deciphered Date
1K_0804_8P4R_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FT3 DISP/MISC/HDT
APU_RST# R80 1 2 300_0402_5%
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
w

APU_PWRGD R82 1 2 300_0402_5% B 1.0

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 6 of 45
A B C D E
 A B C D E

1 2 @
C615 150P_0402_50V8J UAPU1D
ACPI/SD/AZ/GPIO/RTC/MISC
R602 1 2 33_0402_5% LPC_RST_A# AY4 LPC_RST_L SD_PW R_CTRL BA23
<22,27> LPC_RST#
R907 1 2 33_0402_5% APU_PCIE_RST#_R AY9 PCIE_RST_L SD_CLK/GPIO73 AY22
<12,23,26> APU_PCIE_RST#
1 2 EC_RSMRST#_R AY5 RSMRST_L SD_CMD/GPIO74 AY23
C912 150P_0402_50V8J SD_CD/GPIO75 AY20
BA8 PW R_BTN_L SD_W P/GPIO76 BA20
<22> PBTN_OUT#
AM19 PW R_GOOD
<22> SYS_PW RGD_EC
T16 AY7 SYS_RESET_L/GEVENT19_L SD_DATA0/GPIO77 BA22
APU_PCIE_W AKE# AW11 W AKE_L/GEVENT8_L SD_DATA1/GPIO78 AY21
<23> APU_PCIE_W AKE#
SD_DATA2/GPIO79 AY24
1 AY3 SLP_S3_L SD_DATA3/GPIO80 BA24 1
<22> SLP_S3#
BA5 SLP_S5_L
<22> SLP_S5#
SD_LED/GPIO45 AY25
R40 1 2 15K_0402_5% APU_TEST0 AU13 TEST0
R41 1 2 15K_0402_5% APU_TEST1 AY10 TEST1/TMS SCL0/GPIO43 AU25 APU_SCLK0
APU_SCLK0 <10,11,26> +3VS
R42 1 2 15K_0402_5% APU_TEST2 AY6 TEST2 AV25 APU_SDATA0

m
SDA0/GPIO47 APU_SDATA0 <10,11,26>
AR23 KBRST_L SCL1/GPIO227 AY11 APU_SCLK1
<22> KBRST# APU_SCLK1 <29>

2
AR31 BA11 APU_SDATA1
<22> GATEA20
AN5
GA20IN/GEVENT0_L SDA1/GPIO228 APU_SDATA1 <29> PU at T/P side R693 UMA: LOW
<22> EC_SCI# LPC_PME_L/GEVENT3_L
AL7 LPC_SMI_L/GEVENT23_L GPIO49 AP27 R691 1 2 10K_0402_5% 10K_0402_5%
<22> EC_SMI#
AY28 DIS: HIGH
GPIO50
GPIO51 BA28 APU_GPIO51

1
AP15 AV23

o
AC_PRES/IR_RX0/GEVENT16_L GPIO55 DEVSLP0 <27>
AV13 IR_TX0/GEVENT21_L GPIO57 AP21 APU_GPIO51
BA9 IR_TX1/GEVENT6_L GPIO58 BA26

2
BA10 IR_RX1/GEVENT20_L GPIO59 AV19
AV15 IR_LED_L/LLB_L/GPIO184 GPIO64 AY27 PE_GPIO0 R692 @
PE_GPIO0 <12>
SPKR/GPIO66 BA27 10K_0402_5%
APU_SPKR <25>

.c
AU29 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/GPIO60 GPIO68 AU21 PE_GPIO1
PE_GPIO1 <16>
LAN_CLKREQ# AW29 CLK_REQ1_L/GPIO61 GPIO69 AY26
<23> LAN_CLKREQ#

1
W LAN_CLKREQ# AR27 CLK_REQ2_L/GPIO62 GPIO70 AV21
<26> W LAN_CLKREQ#
AV27 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/GPIO63 GPIO71 AM21 APU_GPIO71 R661 1 @ 2 0_0402_5%
PROCHOT# <22,39,6>
T21 AY29 CLK_REQG_L/GPIO65/OSCIN GPIO174 BA3 APU_GPIO174 R686 1 2 10K_0402_5%

USB_OC0# AY8 USB_OC0_L/SPI_TPM_CS_L/TRST_L/GEVENT12_L GEVENT2_L AV17 GEVENT2#

<28> USB_OC0#
USB_OC1# AW1 USB_OC1_L/TDI/GEVENT13_L GEVENT4_L BA4 GEVENT4# R687 1 2 10K_0402_5% GEVENT4# 1 @ 2
TP_I2C_INT#_APU <29>
T19 AV1 USB_OC2_L/TCK/GEVENT14_L GEVENT7_L AR15 R689 1 2 10K_0402_5% R668
AY1 AP17 0_0402_5%

x
T20 USB_OC3_L/TDO/GEVENT15_L GEVENT10_L
2 GEVENT11_L AP11 2
HDA_BITCLK AN2 AZ_BITCLK GEVENT17_L AN8
HDA_SDOUT AN1 AZ_SDOUT BLINK/GEVENT18_L AU17 T17
HDA_SDIN0 AK2 AZ_SDIN0/GPIO167 GEVENT22_L BA6
<25> HDA_SDIN0 EC_LID_OUT# <22>
AK1 AZ_SDIN1/GPIO168

fi
AM1 AZ_SDIN2/GPIO169 GENINT1_L/GPIO32 BA29
AL2 AZ_SDIN3/GPIO170 GENINT2_L/GPIO33 AP23
VGA_PW RGD <16,41,42>
HDA_SYNC AM2 AZ_SYNC
HDA_RST# AL1 AZ_RST_L FANOUT0/GPIO52 AV31
FANIN0/GPIO56 AU31

32K_X1 AJ2 X32K_X1

a
RTCCLK AV11 RTC_CLK
32K_X2 AJ1 X32K_X2

STRAPS OF APU

in
FT3_BGA_769P-T_A39
EMI@ Part Number =
RP13
1 8 HDA_RST#
LPC_FRAME# LPC_CLK0_EC LPC_CLK1 GEVENT2_L RTC_CLK
<25> HDA_RST#_AUDIO
2 7 HDA_SYNC
<25> HDA_SYNC_AUDIO
3 6 HDA_SDOUT SPI ROM BOOT FAIL TIMER CLKGEN 1.8V SPI ROM NORMAL POWR
<25> HDA_SDOUT_AUDIO
<25> HDA_BITCLK_AUDIO
4 5 HDA_BITCLK

33_0804_8P4R_5%
H (DEFAULT) ENABLED ENABLE
(DEFAULT)
UP/RESET TIMING
(DEFAULT)

3
+3VALW

R901
R905
R906
1
1
1
@

@
2
2
2
100K_0402_5%
100K_0402_5%
100K_0402_5%
APU_PCIE_W AKE#
USB_OC0#
USB_OC1#
h
+1.8VALW

L LPC ROM
BOOT FAIL TIMER
DISABLED
(DEFAULT)
CLKGEN
DISABLED
3.3V SPI ROM
(DEFAULT)
FAST POWER
UP/RESET TIMING
FOR SIMULATION
3
.c 2

R675 1 @ 2 1K_0402_5% EC_LID_OUT#

R345 R685
47K_0402_5% 10K_0402_5% +3VALW

+3VS
1

1 2 EC_RSMRST#_R
<22> EC_RSMRST#

1
R676 1 2 2.2K_0402_5% APU_SCLK0 D3
R677 1 2 2.2K_0402_5% APU_SDATA0 RB751V-40 SOD-323 @ @
R902 R904 R925 R928 R949
w

RB751 Max Vf=0.37V 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%

R684 1 @ 2 10K_0402_5% HDA_BITCLK SYS_PW RGD_EC

2
R688 1 @ 2 10K_0402_5% HDA_SDIN0
<22,27,8> LPC_FRAME#
<22,8> LPC_CLK0_EC
1 1 2 <27,8> LPC_CLK1
w

C209 C212 C948 GEVENT2#

32.768KMHz CRYSTAL 1U_0402_6.3V6K
2 2
1U_0402_6.3V6K
1
.1U_0402_16V7K
RTC_CLK
@ESD@
32K_X1

1
1

@ @ @
w

SJ100001K00 Y3 R903 R926 R927 R929 R950

4 32.768KHZ_12.5PF_CM31532768DZFT 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2.2K_0402_5% 4
2

2
2 1 32K_X2
R914
20M_0402_5%
1 1
C686 C682 Security Classification Compal Secret Data Compal Electronics, Inc.
18P_0402_50V8J 18P_0402_50V8J 2014/03/27 2016/03/27 Title
2 2 Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FT3 GPIO/AZ/MISC/STRAPS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 7 of 45
A B C D E
 A B C D E

@
UAPU1E
CLK/SATA/USB/SPI/LPC
BA14 W4
<27> SATA_FTX_DRX_P0 SATA_TX0P USBCLK/14M_25M_48M_OSC
AY14 SATA_TX0N
<27> SATA_FTX_DRX_N0
USB_ZVSS AG4 USB_ZVSS R641 1 2 11.8K_0402_1%
HDD BA16 SATA_RX0N
<27> SATA_FRX_DTX_N0 AY16 AL4
<27> SATA_FRX_DTX_P0 SATA_RX0P USB_HSD0P USB20_P0 <28>
AL5 USB/B port 0
USB_HSD0N USB20_N0 <28>
AY19 SATA_TX1P
<27> SATA_FTX_DRX_P1 BA19 AJ4
1 <27> SATA_FTX_DRX_N1 SATA_TX1N USB_HSD1P USB20_P1 <28> 1
ODD USB_HSD1N AJ5 USB/B port 1 Port 0-3 USB OHCI1 ( Dev 12 Func 0 )
AY17 USB20_N1 <28>
<27> SATA_FRX_DTX_N1 SATA_RX1N EHCI1 ( Dev 12 Func 2 )
BA17 AG7
<27> SATA_FRX_DTX_P1 SATA_RX1P USB_HSD2P USB20_P2 <26>
USB_HSD2N AG8 WLAN/BT combo
2 1 1K_0402_1% SATA_ZVSS AR19 USB20_N2 <26>
R90 SATA_ZVSS
+0.95VS R96 2 1 1K_0402_1% SATA_ZVDD AP19 SATA_ZVDD_095 USB_HSD3P AG1
USB20_P3 <19>

m
AG2 CAMERA
USB_HSD3N USB20_N3 <19>

+3VS 2 @ 1 SATA_ACT# BA30 SATA_ACT_L/GPIO67 USB_HSD4P AF1

R633 AF2
USB_HSD4N
10K_0402_5% AY12 SATA_X1
AE1
USB_HSD5P USB20_P5 <19>
AE2 Touch Screen Port 4-7 USB OHCI2 ( Dev 13 Func 0 )
USB_HSD5N USB20_N5 <19>

o
BA12 AD1 EHCI2 ( Dev 13 Func 2 )
SATA_X2 USB_HSD6P USB20_P6 <29>
USB_HSD6N AD2 USB to I2C bridge
USB20_N6 <29>
U4 AC1
<12> CLK_PEG_VGA GFX_CLKP USB_HSD7P
VGA U5 AC2

.c
<12> CLK_PEG_VGA# GFX_CLKN USB_HSD7N
AC8 GPP_CLK0P USB_HSD8P AB1
AC10 AB2 USB20_P8 <28>
GPP_CLK0N USB_HSD8N USB20_N8 <28> MB USB3.0 port0 (2.0)
AE4 GPP_CLK1P USB_HSD9P AA1
2 <23> CLK_PCIE_LAN AE5 AA2
2
LAN <23> CLK_PCIE_LAN# GPP_CLK1N USB_HSD9N USB2.0 Only
AC4 USB_SS_ZVSS AE10 USBSS_ZVSS R644 1 2 1K_0402_1% Port 8-9 USB OHCI2 ( Dev 16 Func 0 )
<26> CLK_PCIE_WLAN GPP_CLK2P

x
WLAN AC5 AE8 USBSS_ZVDD R645 1 2 1K_0402_1% EHCI2 ( Dev 16 Func 2 )
<26> CLK_PCIE_WLAN# GPP_CLK2N USB_SS_ZVDD_095_USB3_DUAL +0.95VALW
AA5 T2
GPP_CLK3P USB_SS_0TXP USB3_FTX_DRX_P0 <28>
AA4 GPP_CLK3N USB_SS_0TXN T1 USB3.0
USB3_FTX_DRX_N0 <28>
Port 0-1 USB XHCI ( Dev 10 Func 0 )

fi
AP13 V2
X14M_25M_48M_OSC USB_SS_0RXP USB3_FRX_DTX_P0 <28>
USB_SS_0RXN V1 USB3_FRX_DTX_N0 <28>
48M_X1 N2
X48M_X1
USB_SS_1TXP R1
R2
USB_SS_1TXN
48M_X2 N1 X48M_X2 USB_SS_1RXP W1

a
W2
USB_SS_1RXN

R103 1 RS@ 2 0_0402_5% AY2

LPCCLK0
<22,7> LPC_CLK0_EC
R104 1 RS@ 2 0_0402_5% AW2 LPCCLK1 SPI_CLK/GPIO162 AU7 APU_SPI_CLK_R R105 1 RS@ 2 0_0402_5% APU_SPI_CLK R1676 1 RS@ 2 0_0402_5%
<27,7> LPC_CLK1 AW9 EC_SPI_CLK <22>
APU_SPI_CS1# R1677 1 RS@ 2 0_0402_5%

in
SPI_CS1_L/GPIO165 EC_SPI_CS1# <22>
AT2 LAD0 SPI_CS2_L/GPIO166 AR4 T37
<22,27> LPC_AD0 AT1 AR11
LAD1 SPI_DO/GPIO163 APU_SPI_MOSI R1678 1 RS@ 2 0_0402_5%
<22,27> LPC_AD1 AR2 AR7 EC_SPI_MOSI <22>
3 LAD2 SPI_DI/GPIO164 APU_SPI_MISO R1679 1 RS@ 2 0_0402_5% 3
<22,27> LPC_AD2 EC_SPI_MISO <22>
AR1 LAD3 SPI_HOLD_L/GEVENT9_L AU11 APU_SPI_HOLD#
<22,27> LPC_AD3 AP2 AU9
LFRAME_L SPI_WP_L/GPIO161 APU_SPI_WP#
<22,27,7> LPC_FRAME#
AP1 LDRQ0_L
AV29
<22,27> SERIRQ SERIRQ/GPIO48
AP25
<27> CLKRUN# LPC_CLKRUN_L

48MHz CRYSTAL
<27> LPCPD#

48M_X2
AV2 LPC_PD_L/GEVENT5_L/SPI_TPM_CS_L

FT3_BGA_769P-T_A39
Part Number =
h 8MB SPI ROM +3VALW
.c
+3VALW 2 1
1 R938 2 48M_X1 RP12 C635 @
1M_0402_5% 1 8 APU_SPI_CS1# U56 .1U_0402_16V7K
2 7 APU_SPI_WP# APU_SPI_CS1# 1 8
3 6 APU_SPI_HOLD# APU_SPI_MISO 2 CS# VCC 7 APU_SPI_HOLD#
4 5 APU_SPI_WP# 3 DO(IO1) HOLD#(IO3) 6 APU_SPI_CLK
2 1 4 WP#(IO2) CLK 5 APU_SPI_MOSI
2 1 10K_0804_8P4R_5% GND DI(IO0)
w

EN25QH64-104HIP_SO8

APU_SPI_CLK1 2 1 2
Y1 R617 @EMI@ C636 @EMI@
4 48MHZ_8PF_X3S048000D81H-W 10_0402_5% 10P_0402_50V8J 4
Part Number = SJ10000AF00
w

3
3 4
4 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title
1

C794 C795
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FT3 SATA/CLK/USB/SPI
6P_0402_50V8D 6P_0402_50V8D AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
2

B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 8 of 45
A B C D E
 A B C D E

CORE POWER OF APU

+APU_CORE VDDCR_CPU

C179

C180

C181

C182

C183

C184

C186

C187

C188

C189

C190
1 1 1 1 1 1 1 1 1 1 1

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_0402_50V8J
2 2 2 2 2 2 2 2 2 2 2

1 1

m
INTEGRATED GPU POWER OF APU +3VALW/+3VS OF APU
+APU_CORE_NB VDDCR_NB +3VS +3VALW
C200

C201

C202

C192

C191

C193

C194

C195

C197

C249

C257

C252

C253

o
+1.5V
1 1 1 1 1 1 1 1 1 1 1 1 1
3A
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_0402_50V8J

1U_0402_6.3V6K

180P_0402_50V8J

1U_0402_6.3V6K

1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 @ @ @
UAPU1F UAPU1G UAPU1H
POWER GND GND

.c
J35 VDDIO_MEM_S_1 VDDCR_CPU_1 L21 +APU_CORE A8 VSS_1 VSS_63 J3 W29 VSS_125 VSS_187 AL39
L32 L23 A13 J7 W39 AL41
VDDIO_MEM_S_2 VDDCR_CPU_2 VSS_2 VSS_64 VSS_126 VSS_188
L37 L25 A23 J8 W41 AM11
VDDIO_MEM_S_3 VDDCR_CPU_3 VSS_3 VSS_65 VSS_127 VSS_189
N35 VDDIO_MEM_S_4 VDDCR_CPU_4 L27 A31 VSS_4 VSS_66 J39 Y1 VSS_128 VSS_190 AM27

2
R31 L29 A35 K11 Y2 AM31
VDDIO_MEM_S_5 VDDCR_CPU_5 VSS_5 VSS_67 VSS_129 VSS_191
R37 N21 R119 A39 K13 AA3 AN3
VDD_33 VDD_33_ALW U32
VDDIO_MEM_S_6 VDDCR_CPU_6
N23 0_0402_5% B8
VSS_6 VSS_68
K17 AA7
VSS_130 VSS_192
AN7
VDDIO_MEM_S_7 VDDCR_CPU_7 VSS_7 VSS_69 VSS_131 VSS_193
U35 N27 RS@ B13 K19 AA8 AN39
VDDIO_MEM_S_8 VDDCR_CPU_8 VSS_8 VSS_70 VSS_132 VSS_194
W31 VDDIO_MEM_S_9 VDDCR_CPU_9 R21 B23 VSS_9 VSS_71 K21 AA11 VSS_133 VSS_195 AP31

1
VDDIO_AZ_ALW W32 R23 B31 K23 AA15 AR3
+1.5V/+1.5VS OF APU (Could be S0 or S5 power rail) W37
AA31
VDDIO_MEM_S_10
VDDIO_MEM_S_11
VDDCR_CPU_10
VDDCR_CPU_11 R27
U21
B39
C1
VSS_10
VSS_11
VSS_72
VSS_73 K25
K27
AA19
AA25
VSS_134
VSS_135
VSS_196
VSS_197 AR13
AR17
VDDIO_MEM_S_12 VDDCR_CPU_12 VSS_12 VSS_74 VSS_136 VSS_198
PLANE SPLIT AA35 U23 C2 K29 AA29 AR21

x
+1.5V +1.5VS VDDIO_MEM_S_13 VDDCR_CPU_13 VSS_13 VSS_75 VSS_137 VSS_199
AC32 U27 C5 K31 AA39 AR25
2
VDDIO_MEM_S AC37
VDDIO_MEM_S_14 VDDCR_CPU_14
W21 C7
VSS_14 VSS_76
L3 AC3
VSS_138 VSS_200
AR29
2
VDDIO_MEM_S_15 VDDCR_CPU_15 VSS_15 VSS_77 VSS_139 VSS_201
AE31 VDDIO_MEM_S_16 VDDCR_CPU_16 W23 C9 VSS_16 VSS_78 L7 AC7 VSS_140 VSS_202 AR39
AE35 W27 C11 L8 AC11 AR41
VDDIO_MEM_S_17 VDDCR_CPU_17 VSS_17 VSS_79 VSS_141 VSS_203
C924

C925

C949

C923

C926

C927

C928

C929

C931

C930

C932

C211

C210

C208

C207

C230

C231

C258

C259

C161

C232

C254

C255

C256
AG32 AA21 C13 L10 AC15 AU1
VDDIO_MEM_S_18 VDDCR_CPU_18 VSS_18 VSS_80 VSS_142 VSS_204
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 AG37 VDDIO_MEM_S_19 VDDCR_CPU_19 AA23 C15 VSS_19 VSS_81 L11 AC19 VSS_143 VSS_205 AU2
AJ35 AA27 C17 L15 AC25 AU3

fi
VDDIO_MEM_S_20 VDDCR_CPU_20 VSS_20 VSS_82 VSS_144 VSS_206
AL32 VDDIO_MEM_S_21 VDDCR_CPU_21 AC21 C19 VSS_21 VSS_83 L19 AC29 VSS_145 VSS_207 AU15
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

.1U_0402_16V7K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

1U_0402_6.3V6K

.1U_0402_16V7K

1U_0402_6.3V6K

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

4.7U_0603_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_0402_50V8J
AL37 AC23 C21 L31 AC31 AU19
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VDDIO_MEM_S_22 VDDCR_CPU_22 VSS_22 VSS_84 VSS_146 VSS_208
AR35 AC27 C23 L39 AC39 AU23
VDDIO_MEM_S_23 VDDCR_CPU_23 VSS_23 VSS_85 VSS_147 VSS_209
VDDCR_CPU_24 AE21 C25 VSS_24 VSS_86 L41 AC41 VSS_148 VSS_210 AU27
AE23 C27 M1 AE3 AU39
VDDCR_CPU_25 VSS_25 VSS_87 VSS_149 VSS_211
VDDCR_CPU_26 AE27 C29 VSS_26 VSS_88 M2 AE7 VSS_150 VSS_212 AV9
C31 N3 AE25 AW3
VSS_27 VSS_89 VSS_151 VSS_213
VDDCR_NB_1 L13 C33 N7 AE29 AW7
+APU_CORE_NB VSS_28 VSS_90 VSS_152 VSS_214
VDDCR_NB_2 L17 C35 VSS_29 VSS_91 N15 AE32 VSS_153 VSS_215 AW13

a
VDDCR_NB_3 N11 C37 N19 AE39 AW15
VSS_30 VSS_92 VSS_154 VSS_216
@ @ @ @ @ VDDCR_NB_4 N13 C39 VSS_31 VSS_93 N25 AG3 VSS_155 VSS_217 AW17
VDDCR_NB_5 N17 C41 N29 AG5 AW19
VSS_32 VSS_94 VSS_156 VSS_218
VDDCR_NB_6 R11 D9 N31 AG10 AW21
VSS_33 VSS_95 VSS_157 VSS_219
VDDCR_NB_7 R13 D11 VSS_34 VSS_96 N39 AG11 VSS_158 VSS_220 AW23
VDDCR_NB_8 R17 D13 P1 AG13 AW25
VSS_35 VSS_97 VSS_159 VSS_221
U13 E3 P2 AG15 AW27
+0.95VALW/+0.95VS OF APU +1.8VALW/+1.8VS OF APU VDDCR_NB_9
U17 E4
VSS_36 VSS_98
R3 AG19
VSS_160 VSS_222
AW31

in
VDDCR_NB_10 VSS_37 VSS_99 VSS_161 VSS_223
W13 E9 R7 AG25 AW33
VDDCR_NB_11 VSS_38 VSS_100 VSS_162 VSS_224
W17 E11 R15 AG29 AW35
+0.95VS VDD_095 VDD_095_GFX +0.95VS_APU_GFX +1.8VS VDD_18 VDDCR_NB_12
AA13 E13
VSS_39 VSS_101
R19 AG31
VSS_163 VSS_225
AW37
VDDCR_NB_13 VSS_40 VSS_102 VSS_164 VSS_226
L22 VDDCR_NB_14 AA17 E27 VSS_41 VSS_103 R25 AG39 VSS_165 VSS_227 AW39
2 1 AC13 E31 R29 AG41 AW41
VDDCR_NB_15 VSS_42 VSS_104 VSS_166 VSS_228
FBMA-L11-201209-121LMA50T_0805 AC17 E35 R39 AH1 AY13
VDDCR_NB_16 VSS_43 VSS_105 VSS_167 VSS_229
C935

C934

C198

C199

C205

C204

C206

C260

C213

C950

C203

C933

C236

C237

C238

C239

C240

C233

VDDCR_NB_17 AE15 E38 VSS_44 VSS_106 R41 AH2 VSS_168 VSS_230 AY15
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 AE17 E39 U1 AJ3 AY18
VDDCR_NB_18 VSS_45 VSS_107 VSS_169 VSS_231
VDDCR_NB_19 AE19 G3 VSS_46 VSS_108 U2 AJ7 VSS_170 VSS_232 AY30
C946 C947 AG17 G7 U3 AJ15 BA2
VDDCR_NB_20 VSS_47 VSS_109 VSS_171 VSS_233
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_0402_50V8J

10U_0603_6.3V6M

1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_0402_50V8J

.1U_0402_16V7K .1U_0402_16V7K AL10 AG21 G11 U7 AJ17 BA7

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 +1.5VS VDDIO_AZ_ALW_1 VDDCR_NB_21 VSS_48 VSS_110 VSS_172 VSS_234
@ESD@ @ESD@ AL11 VDDIO_AZ_ALW_2 G13 VSS_49 VSS_111 U8 AJ19 VSS_173 VSS_235 BA13

@ @
+1.8VALW

+3VALW
h B1
B2

AL13
AM13
VDD_18_ALW_1
VDD_18_ALW_2

VDD_33_ALW_1
VDD_18_1
VDD_18_2
VDD_18_3
VDD_18_4

VDD_33_1
A2
A3
B3
C3

AM15
AM17
+1.8VS

+3VS
G15
G17
G21
G25
G29
G35
G37
G39
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
U11
U15
U19
U25
U29
U31
U39
W3
AJ23
AJ25
AJ29
AJ31
AJ32
AJ39
AL3
AL8
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
BA15
BA18
BA21
BA25
BA31
BA35
BA39
A15
3
.c
+0.95VALW +0.95VALW VDD_33_ALW_2 VDD_33_2 VSS_57 VSS_119 VSS_181 VSSBG_DAC
G41 W5 AL15 AL31
+1.8VALW VSS_58 VSS_120 VSS_182 VBURN
+0.95VALW AR5 VDD_095_USB3_DUAL_1 VDD_095_1 AG23 +0.95VS H11 VSS_59 VSS_121 W11 AL17 VSS_183 AM29
AU4 AG27 H13 W15 AL19 PSEN
VDD_095_USB3_DUAL_2 VDD_095_2 VSS_60 VSS_122 VSS_184
AV7 VDD_095_USB3_DUAL_3 VDD_095_3 AJ21 H23 VSS_61 VSS_123 W19 AL25 VSS_185
C937

C938

C216

C214

C221

C218

C220

C219

C217

C222

AW5 AJ27 H31 W25 AL29

VDD_095_USB3_DUAL_4 VDD_095_4 VSS_62 VSS_124 VSS_186
C160

C244

C250

C246

C248

C245

1 1 1 1 1 1 1 1 1 1 AL21
VDD_095_5
1 1 1 1 1 1 +0.95VALW AE11 VDD_095_ALW_1 VDD_095_6 AL23
AE13 AL27 FT3_BGA_769P-T_A39 FT3_BGA_769P-T_A39
VDD_095_ALW_2 VDD_095_7
10U_0603_6.3V6M

10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_0402_50V8J

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

AJ11 VDD_095_ALW_3 VDD_095_8 AM23 Part Number = Part Number =

2 2 2 2 2 2 2 2 2 2
4.7U_0603_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

180P_0402_50V8J

AJ13 AM25
2 2 2 2 2 2 VDD_095_ALW_4 VDD_095_9
U10
w

VDD_095_GFX_1 +0.95VS_APU_GFX
VDD_095_GFX_2 W10
+RTC_APU_R +RTC_APU_R AN4 VDDBT_RTC_G VDD_095_GFX_3 AA10

@ @ @ FT3_BGA_769P-T_A39
Part Number =
VDD_095_USB3_DUAL
VDD_095_ALW
VDD_18_ALW
w

VDDBT_RTC_G
+RTC_APU
w

+RTC_APU_R W=20mils R93 1 2 10K_0402_5%

4 RTC OF APU 4

1
1

C166 CLRP1 SP@

0.22U_0402_10V6K SHORT PADS
Need OPEN
2

2
for Clear CMOS

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title
FT3 PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 9 of 45
A B C D E
 A B C D E

+VREF_DQ +1.5V +1.5V DDRAB_SDQ[0..63]

DDRAB_SDQ[0..63] <11,5>
JDIMM1 DDRAB_SDM[0..7]
15mil 1 2
DDRAB_SDM[0..7] <11,5>
3 VREF_DQ VSS1 4 DDRAB_SDQ4 DDRAB_SMA[0..15]
DDRAB_SMA[0..15] <11,5>

.1U_0402_16V7K

1000P_0402_50V7K
DDRAB_SDQ0 5 VSS2 DQ4 6 DDRAB_SDQ5
2 1 DQ0 DQ5
DDRAB_SDQ1 7 8

C176

C142
9 DQ1 VSS3 10 DDRAB_SDQS0#
VSS4 DQS#0 DDRAB_SDQS0# <11,5>
DDRAB_SDM0 11 12 DDRAB_SDQS0
1 2 13 DM0 DQS0 14 DDRAB_SDQS0 <11,5>
DDRAB_SDQ2 15 VSS5 VSS6 16 DDRAB_SDQ6
DDRAB_SDQ3 17 DQ2 DQ6 18 DDRAB_SDQ7
19 DQ3 DQ7 20
DDRAB_SDQ8 21 VSS7 VSS8 22 DDRAB_SDQ12
DDRAB_SDQ9 23 DQ8 DQ12 24 DDRAB_SDQ13
1
DDRAB_SDQS1#
25
27
DQ9
VSS9
DQ13
VSS10
26
28 DDRAB_SDM1
+1.5V/+0.75VS OF DIMM1 1
<11,5> DDRAB_SDQS1# 29 DQS#1 DM1 30
DDRAB_SDQS1 MEM_MAB_RST#
<11,5> DDRAB_SDQS1 DQS1 RESET# MEM_MAB_RST# <11,5>
31 32 +1.5V +0.75VS
DDRAB_SDQ10 33 VSS11 VSS12 34 DDRAB_SDQ14
DDRAB_SDQ11 35 DQ10 DQ14 36 DDRAB_SDQ15
37 DQ11 DQ15 38
VSS13 VSS14

C114

C115

C116

C117

C118

C119

C120

C121

C122

C123

C129

C128

C126

C127
DDRAB_SDQ16 39 40 DDRAB_SDQ20

m
DQ16 DQ20

@ESD@

@ESD@
DDRAB_SDQ17 41 42 DDRAB_SDQ21 1 1 1 1 1 1 1 1 1 1 1 1 1 1
43 DQ17 DQ21 44
DDRAB_SDQS2# 45 VSS15 VSS16 46 DDRAB_SDM2
<11,5> DDRAB_SDQS2# DQS#2 DM2

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

4.7U_0603_6.3V6K
DDRAB_SDQS2 47 48
<11,5> DDRAB_SDQS2 49 DQS2 VSS17 50 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DDRAB_SDQ22
DDRAB_SDQ18 51 VSS18 DQ22 52 DDRAB_SDQ23
DDRAB_SDQ19 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDRAB_SDQ28
DDRAB_SDQ24 57 VSS20 DQ28 58 DDRAB_SDQ29
DDRAB_SDQ25 59 DQ24 DQ29 60

o
61 DQ25 VSS21 62 DDRAB_SDQS3#
63 VSS22 DQS#3 64 DDRAB_SDQS3# <11,5>
DDRAB_SDM3 DDRAB_SDQS3 @ @ @ @ @ @
DM3 DQS3 DDRAB_SDQS3 <11,5>
65 66
DDRAB_SDQ26 67 VSS23 VSS24 68 DDRAB_SDQ30
DDRAB_SDQ27 69 DQ26 DQ30 70 DDRAB_SDQ31
71 DQ27 DQ31 72
VSS25 VSS26

.c
DDRA_CKE0 73 74 DDRA_CKE1
<5> DDRA_CKE0 CKE0 CKE1 DDRA_CKE1 <5>
75 76
77 VDD1 VDD2 78 DDRAB_SMA15
DDRAB_SBS2# 79 NC1 A15 80 DDRAB_SMA14
<11,5> DDRAB_SBS2# BA2 A14
81 82
DDRAB_SMA12 83 VDD3 VDD4 84 DDRAB_SMA11
DDRAB_SMA9 85 A12/BC# A11 86 DDRAB_SMA7
87 A9 A7 88
DDRAB_SMA8 89 VDD5 VDD6 90 DDRAB_SMA6
DDRAB_SMA5 91 A8 A6 92 DDRAB_SMA4
93 A5 A4 94

x
DDRAB_SMA3 95 VDD7 VDD8 96 DDRAB_SMA2
2
DDRAB_SMA1 97
99
A3
A1
A2
A0
98
100
DDRAB_SMA0 VREF for DIMM1,2 2

DDRA_CLK0 101 VDD9 VDD10 102 DDRA_CLK1

<5> DDRA_CLK0 103 CK0 CK1 104 DDRA_CLK1 <5>
DDRA_CLK0# DDRA_CLK1#
<5> DDRA_CLK0# CK0# CK1# DDRA_CLK1# <5>
105 106
DDRAB_SMA10 107 VDD11 VDD12 108 DDRAB_SBS1#

fi
A10/AP BA1 DDRAB_SBS1# <11,5> +VREF_DQ +1.5V
DDRAB_SBS0# 109 110 DDRAB_SRAS#
<11,5> DDRAB_SBS0# BA0 RAS# DDRAB_SRAS# <11,5>
111 112 RP9
DDRAB_SWE# 113 VDD13 VDD14 114 DDRA_SCS0# 1 8
<11,5> DDRAB_SWE# WE# S0# DDRA_SCS0# <5> +VREF_CA
DDRAB_SCAS# 115 116 DDRA_ODT0 2 7
<11,5> DDRAB_SCAS# 117 CAS# ODT0 118 DDRA_ODT0 <5> 3 6
DDRAB_SMA13 119 VDD15 VDD16 120 DDRA_ODT1 4 5
A13 ODT1 DDRA_ODT1 <5>
DDRA_SCS1# 121 122 15mil
<5> DDRA_SCS1# 123 S1# NC2 124 1K_0804_8P4R_1%
125 VDD17 VDD18 126
NCTEST VREF_CA +VREF_CA

a
127 128
DDRAB_SDQ32 129 VSS27 VSS28 130 DDRAB_SDQ36

.1U_0402_16V7K
1000P_0402_50V7K

DDRAB_SDQ33 131 DQ32 DQ36 132 DDRAB_SDQ37

DQ33 DQ37 1 2
133 134
C134

C167
DDRAB_SDQS4# 135 VSS29 VSS30 136 DDRAB_SDM4 MEM_MAB_RST# 1 2
<11,5> DDRAB_SDQS4# 137 DQS#4 DM4 138
DDRAB_SDQS4 C1274 @ESD@
<11,5> DDRAB_SDQS4 DQS4 VSS31 2 1
139 140 DDRAB_SDQ38 100P_0402_50V8J
DDRAB_SDQ34 141 VSS32 DQ38 142 DDRAB_SDQ39

in
DDRAB_SDQ35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDRAB_SDQ44
DDRAB_SDQ40 147 VSS34 DQ44 148 DDRAB_SDQ45
DDRAB_SDQ41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDRAB_SDQS5#
153 VSS36 DQS#5 154 DDRAB_SDQS5# <11,5>
DDRAB_SDM5 DDRAB_SDQS5
DM5 DQS5 DDRAB_SDQS5 <11,5>
155 156
DDRAB_SDQ42 157 VSS37 VSS38 158 DDRAB_SDQ46
DDRAB_SDQ43 159 DQ42 DQ46 160 DDRAB_SDQ47
161 DQ43 DQ47 162
DDRAB_SDQ48 163 VSS39 VSS40 164 DDRAB_SDQ52
DDRAB_SDQ49 165 DQ48 DQ52 166 DDRAB_SDQ53

3 <11,5> DDRAB_SDQS6#
<11,5> DDRAB_SDQS6
DDRAB_SDQS6#
DDRAB_SDQS6

DDRAB_SDQ50
DDRAB_SDQ51

DDRAB_SDQ56
167
169
171
173
175
177
179
181
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
168
170
172
174
176
178
180
182
DDRAB_SDM6

DDRAB_SDQ54
DDRAB_SDQ55

DDRAB_SDQ60
DDRAB_SDQ61
h 3
.c
DDRAB_SDQ57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDRAB_SDQS7#
187 VSS48 DQS#7 188 DDRAB_SDQS7# <11,5>
DDRAB_SDM7 DDRAB_SDQS7
DM7 DQS7 DDRAB_SDQS7 <11,5>
189 190
DDRAB_SDQ58 191 VSS49 VSS50 192 DDRAB_SDQ62
DDRAB_SDQ59 193 DQ58 DQ62 194 DDRAB_SDQ63
195 DQ59 DQ63 196
197 VSS51 VSS52 198 MEM_MAB_EVENT#
<Address: 00> 199 SA0 EVENT# 200
MEM_MAB_EVENT# <11,5>
+3VS VDDSPD SDA APU_SDATA0 <11,26,7>
1 2 2 201 202
203 SA1 SCL 204 APU_SCLK0 <11,26,7>
VTT1 VTT2 +0.75VS
C136 C944 @ESD@ C945 @ESD@
w

.1U_0402_16V7K .1U_0402_16V7K .1U_0402_16V7K 205 206

2 1 1 G1 G2
FOX_AS0A621-U4R6-7H
CONN@
SP07000J510
w

DIMM_A H:4mm RVS

w

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3 SODIMM-I Socket
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 10 of 45
A B C D E
 A B C D E

+VREF_DQ +1.5V +1.5V

15mil JDIMM2
1 2
3 VREF_DQ VSS1 4 DDRAB_SDQ4 DDRAB_SDQ[0..63]
DDRAB_SDQ0 5 VSS2 DQ4 6 DDRAB_SDQ5 DDRAB_SDQ[0..63] <10,5>
.1U_0402_16V7K

1000P_0402_50V7K
DDRAB_SDQ1 7 DQ0 DQ5 8 DDRAB_SDM[0..7]
2 1 DQ1 VSS3 DDRAB_SDM[0..7] <10,5>
9 10 DDRAB_SDQS0#

C177

C143
VSS4 DQS#0 DDRAB_SDQS0# <10,5> DDRAB_SMA[0..15]
DDRAB_SDM0 11 12 DDRAB_SDQS0 DDRAB_SMA[0..15] <10,5>
13 DM0 DQS0 14 DDRAB_SDQS0 <10,5>
1 2 DDRAB_SDQ2 15 VSS5 VSS6 16 DDRAB_SDQ6
DDRAB_SDQ3 17 DQ2 DQ6 18 DDRAB_SDQ7
19 DQ3 DQ7 20
DDRAB_SDQ8 21 VSS7 VSS8 22 DDRAB_SDQ12
DDRAB_SDQ9 23 DQ8 DQ12 24 DDRAB_SDQ13
25 DQ9 DQ13 26
1
DDRAB_SDQS1# 27 VSS9 VSS10 28 DDRAB_SDM1 1
<10,5> DDRAB_SDQS1# 29 DQS#1 DM1 30
DDRAB_SDQS1 MEM_MAB_RST#
<10,5> DDRAB_SDQS1 DQS1 RESET# MEM_MAB_RST# <10,5>
31 32
DDRAB_SDQ10 33 VSS11
DQ10
VSS12
DQ14
34 DDRAB_SDQ14 +1.5V/+0.75VS OF DIMM2
DDRAB_SDQ11 35 36 DDRAB_SDQ15
37 DQ11 DQ15 38
DDRAB_SDQ16 39 VSS13 VSS14 40 DDRAB_SDQ20 +1.5V +0.75VS +1.5V

m
DDRAB_SDQ17 41 DQ16 DQ20 42 DDRAB_SDQ21
43 DQ17 DQ21 44
DDRAB_SDQS2# 45 VSS15 VSS16 46 DDRAB_SDM2

220U_6.3V_M
<10,5> DDRAB_SDQS2# DQS#2 DM2 1

C133

C155

C132

C162

C165

C168

C169

C170

C171

C172

C175

C158
DDRAB_SDQS2 47 48
<10,5> DDRAB_SDQS2 49 DQS2 VSS17 50 +
DDRAB_SDQ22

C644
VSS18 DQ22 1 1 1 1 1 1 1 1 1 1 1 1
DDRAB_SDQ18 51 52 DDRAB_SDQ23
DDRAB_SDQ19 53 DQ18 DQ23 54
DQ19 VSS19 2

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K

4.7U_0603_6.3V6K
55 56 DDRAB_SDQ28
DDRAB_SDQ24 57 VSS20 DQ28 58 DDRAB_SDQ29 2 2 2 2 2 2 2 2 2 2 2 2
DDRAB_SDQ25 59 DQ24 DQ29 60

o
61 DQ25 VSS21 62 DDRAB_SDQS3#
63 VSS22 DQS#3 64 DDRAB_SDQS3# <10,5>
DDRAB_SDM3 DDRAB_SDQS3
DM3 DQS3 DDRAB_SDQS3 <10,5>
65 66
DDRAB_SDQ26 67 VSS23 VSS24 68 DDRAB_SDQ30
DDRAB_SDQ27 69 DQ26 DQ30 70 DDRAB_SDQ31
71 DQ27 DQ31 72 @ @ @ @
VSS25 VSS26

.c
DDRB_CKE0 73 74 DDRB_CKE1
<5> DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 <5>
75 76 MEM_MAB_RST# 1 2
77 VDD1 VDD2 78 DDRAB_SMA15 C1275 @ESD@
DDRAB_SBS2# 79 NC1 A15 80 DDRAB_SMA14 100P_0402_50V8J
<10,5> DDRAB_SBS2# BA2 A14
81 82
DDRAB_SMA12 83 VDD3 VDD4 84 DDRAB_SMA11
DDRAB_SMA9 85 A12/BC# A11 86 DDRAB_SMA7
87 A9 A7 88
DDRAB_SMA8 89 VDD5 VDD6 90 DDRAB_SMA6
DDRAB_SMA5 91 A8 A6 92 DDRAB_SMA4
93 A5 A4 94

x
DDRAB_SMA3 95 VDD7 VDD8 96 DDRAB_SMA2
2 2
DDRAB_SMA1 97 A3 A2 98 DDRAB_SMA0
99 A1 A0 100
DDRB_CLK0 101 VDD9 VDD10 102 DDRB_CLK1
<5> DDRB_CLK0 103 CK0 CK1 104 DDRB_CLK1 <5>
DDRB_CLK0# DDRB_CLK1#
<5> DDRB_CLK0# CK0# CK1# DDRB_CLK1# <5>
105 106
DDRAB_SMA10 107 VDD11 VDD12 108 DDRAB_SBS1#

fi
A10/AP BA1 DDRAB_SBS1# <10,5>
DDRAB_SBS0# 109 110 DDRAB_SRAS#
<10,5> DDRAB_SBS0# BA0 RAS# DDRAB_SRAS# <10,5>
111 112
DDRAB_SWE# 113 VDD13 VDD14 114 DDRB_SCS0#
<10,5> DDRAB_SWE# WE# S0# DDRB_SCS0# <5>
DDRAB_SCAS# 115 116 DDRB_ODT0
<10,5> DDRAB_SCAS# 117 CAS# ODT0 118 DDRB_ODT0 <5>
DDRAB_SMA13 119 VDD15 VDD16 120 DDRB_ODT1
A13 ODT1 DDRB_ODT1 <5>
DDRB_SCS1# 121 122 15mil
<5> DDRB_SCS1# 123 S1# NC2 124
125 VDD17 VDD18 126
NCTEST VREF_CA +VREF_CA

a
127 128

.1U_0402_16V7K
1000P_0402_50V7K
DDRAB_SDQ32 129 VSS27 VSS28 130 DDRAB_SDQ36
DQ32 DQ36 1 2
DDRAB_SDQ33 131 132 DDRAB_SDQ37
C139

C174
133 DQ33 DQ37 134
DDRAB_SDQS4# 135 VSS29 VSS30 136 DDRAB_SDM4
<10,5> DDRAB_SDQS4# 137 DQS#4 DM4 138 2 1
DDRAB_SDQS4
<10,5> DDRAB_SDQS4 DQS4 VSS31
139 140 DDRAB_SDQ38
DDRAB_SDQ34 141 VSS32 DQ38 142 DDRAB_SDQ39

in
DDRAB_SDQ35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDRAB_SDQ44
DDRAB_SDQ40 147 VSS34 DQ44 148 DDRAB_SDQ45
DDRAB_SDQ41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDRAB_SDQS5#
153 VSS36 DQS#5 154 DDRAB_SDQS5# <10,5>
DDRAB_SDM5 DDRAB_SDQS5
DM5 DQS5 DDRAB_SDQS5 <10,5>
155 156
DDRAB_SDQ42 157 VSS37 VSS38 158 DDRAB_SDQ46
DDRAB_SDQ43 159 DQ42 DQ46 160 DDRAB_SDQ47
161 DQ43 DQ47 162
DDRAB_SDQ48 163 VSS39 VSS40 164 DDRAB_SDQ52
DDRAB_SDQ49 165 DQ48 DQ52 166 DDRAB_SDQ53

3 <10,5> DDRAB_SDQS6#
<10,5> DDRAB_SDQS6
DDRAB_SDQS6#
DDRAB_SDQS6

DDRAB_SDQ50
DDRAB_SDQ51

DDRAB_SDQ56
167
169
171
173
175
177
179
181
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
168
170
172
174
176
178
180
182
DDRAB_SDM6

DDRAB_SDQ54
DDRAB_SDQ55

DDRAB_SDQ60
DDRAB_SDQ61
h 3
.c
DDRAB_SDQ57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDRAB_SDQS7#
187 VSS48 DQS#7 188 DDRAB_SDQS7# <10,5>
DDRAB_SDM7 DDRAB_SDQS7
DM7 DQS7 DDRAB_SDQS7 <10,5>
189 190
DDRAB_SDQ58 191 VSS49 VSS50 192 DDRAB_SDQ62
DDRAB_SDQ59 193 DQ58 DQ62 194 DDRAB_SDQ63
195 DQ59 DQ63 196
1 2 DDRB_SA0 197 VSS51 VSS52 198 MEM_MAB_EVENT#
SA0 EVENT# MEM_MAB_EVENT# <10,5>
R690 10K_0402_5% 199 200
+3VS VDDSPD SDA APU_SDATA0 <10,26,7>
1 201 202
203 SA1 SCL 204 APU_SCLK0 <10,26,7>
C140 <Address: 01> VTT1 VTT2 +0.75VS
w

.1U_0402_16V7K 205 206

2 G1 G2
LCN_DAN06-K4406-0100
CONN@
w

DIMM_B H:4mm STD

w

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3 SODIMM-II Socket
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 11 of 45
A B C D E
 A B C D E

GFX PCIE LANE REVERSAL U75G

U75A
PEG_ATX_GRX_P[0..3] PEG_GTX_C_ARX_P[0..3] PART 7 0F 9
<5> PEG_ATX_GRX_P[0..3] PART 1 0F 9 PEG_GTX_C_ARX_P[0..3] <5>
PEG_ATX_GRX_N[0..3] PEG_GTX_C_ARX_N[0..3] AK27
<5> PEG_ATX_GRX_N[0..3] PEG_GTX_C_ARX_N[0..3] <5> RSVD/VARY_BL AJ27
RSVD/DIGON
LVDS CONTROL
1 1
PEG_ATX_GRX_P0 VGA@ C47 1 2 .1U_0402_16V7K PEG_ATX_C_GRX_P0 AA38 Y33 PEG_GTX_ARX_P0 VGA@ C65 1 2 .1U_0402_16V7K PEG_GTX_C_ARX_P0
PEG_ATX_GRX_N0 VGA@ C48 1 2 .1U_0402_16V7K PEG_ATX_C_GRX_N0 Y37 PCIE_RX0P PCIE_TX0P Y32 PEG_GTX_ARX_N0 VGA@ C66 1 2 .1U_0402_16V7K PEG_GTX_C_ARX_N0
PCIE_RX0N PCIE_TX0N AK35
TXCBP_DPB3P AL36
PEG_ATX_GRX_P1 VGA@ C49 1 2 .1U_0402_16V7K PEG_ATX_C_GRX_P1 Y35 W33 PEG_GTX_ARX_P1 VGA@ C67 1 2 .1U_0402_16V7K PEG_GTX_C_ARX_P1 TXCBM_DPB3N

m
PEG_ATX_GRX_N1 VGA@ C50 1 2 .1U_0402_16V7K PEG_ATX_C_GRX_N1 W36 PCIE_RX1P PCIE_TX1P W32 PEG_GTX_ARX_N1 VGA@ C68 1 2 .1U_0402_16V7K PEG_GTX_C_ARX_N1 AJ38
PCIE_RX1N PCIE_TX1N TX3P_DPB2P AK37
TX3M_DPB2N
PEG_ATX_GRX_P2 VGA@ C60 1 2 .1U_0402_16V7K PEG_ATX_C_GRX_P2 W38 U33 PEG_GTX_ARX_P2 VGA@ C70 1 2 .1U_0402_16V7K PEG_GTX_C_ARX_P2 AH35
PEG_ATX_GRX_N2 VGA@ C61 1 2 .1U_0402_16V7K PEG_ATX_C_GRX_N2 V37 PCIE_RX2P PCIE_TX2P U32 PEG_GTX_ARX_N2 VGA@ C69 1 2 .1U_0402_16V7K PEG_GTX_C_ARX_N2 TX4P_DPB1P AJ36
PCIE_RX2N PCIE_TX2N TX4M_DPB1N
AG38
PEG_ATX_GRX_P3 VGA@ C64 1 2 .1U_0402_16V7K PEG_ATX_C_GRX_P3 V35 U30 PEG_GTX_ARX_P3 VGA@ C71 1 2 .1U_0402_16V7K PEG_GTX_C_ARX_P3 TX5P_DPB0P AH37

o
PEG_ATX_GRX_N3 VGA@ C63 1 2 .1U_0402_16V7K PEG_ATX_C_GRX_N3 U36 PCIE_RX3P PCIE_TX3P U29 PEG_GTX_ARX_N3 VGA@ C72 1 2 .1U_0402_16V7K PEG_GTX_C_ARX_N3 TX5M_DPB0N
PCIE_RX3N PCIE_TX3N AF35

LVTMDP
NC#AF35 AG36
U38 T33 NC#AG36
T37 PCIE_RX4P PCIE_TX4P T32
PCIE_RX4N PCIE_TX4N

.c
T35 T30 AP34
R36 PCIE_RX5P PCIE_TX5P T29 TXCAP_DPA3P AR34
PCIE_RX5N PCIE_TX5N TXCAM_DPA3N
AW37
R38 P33 TX0P_DPA2P AU35
P37 PCIE_RX6P PCIE_TX6P P32 TX0M_DPA2N
PCIE_RX6N PCIE_TX6N AR37
TX1P_DPA1P AU39

x
2 P35 P30 TX1M_DPA1N 2
N36 PCIE_RX7P PCIE_TX7P P29 AP35
PCIE_RX7N PCIE_TX7N TX2P_DPA0P AR35
TX2M_DPA0N
N38 N33 AN36
NC#N38 NC#N33 NC#AN36

fi
M37 N32 AP37
NC#M37 NC#N32 NC#AP37

PCI EXPRESS INTERFACE

M35 N30
L36 NC#M35 NC#N30 N29
NC#L36 NC#N29 2160842006A0MARSXT_FCBGA962
@
L38 L33

a
K37 NC#L38 NC#L33 L32
NC#K37 NC#L32

K35 L30
J36 NC#K35 NC#L30 L29 R405
NC#J36 NC#L29

in
0_0402_5%
2 @ 1
J38 K33
H37 NC#J38 NC#K33 K32 +3VS
NC#H37 NC#K32

H35 J33
NC#H35 NC#J33

5
G36 J32
NC#G36 NC#J32

VCC
APU_PCIE_RST# 1
3
G38
F37 NC#G38

h
NC#K30
K30
K29
<23,26,7> APU_PCIE_RST#
PE_GPIO0 2
IN1
OUT
4 GPU_RST#
3

GND
NC#F37 NC#K29 <7> PE_GPIO0 IN2

1
2
F35 H33 R391

3
E37 NC#F35 NC#H33 H32 R1578 U37 100K_0402_5%
.c
NC#E37 NC#H32 2.2K_0402_5% MC74VHC1G08DFT2G_SC70-5 VGA@
VGA@ VGA@

2
1
CLOCK
AB35
<8> CLK_PEG_VGA PCIE_REFCLKP
AA36
<8> CLK_PEG_VGA# PCIE_REFCLKN

CALIBRATION
w

Y30 VGA_PCIE_CALRP R797 1 VGA@ 2 1.69K_0402_1% +0.95VSDGPU

PCIE_CALR_TX
2 VGA@ 1 AH16 Y29 VGA_PCIE_CALRN R796 1 VGA@ 2 1K_0402_1% +0.95VSDGPU
R795 1K_0402_5% TEST_PG PCIE_CALR_RX

GPU_RST# AA30
PERSTB
w

3.3-V tolerant
2160842006A0MARSXT_FCBGA962
@
w

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2014/03/27 2016/03/27 Title
Issued Date Deciphered Date MARS-Pro_PCIE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 12 of 45
A B C D E
 A B C D E

U75B U75I 130mA L64

MBK1608121YZF_0603
+3VSDGPU External VGA Thermal Sensor PART 2 0F 9

PART 9 0F 9
+MPLL_PVDD 2 1
+1.8VSDGPU
U52 @ MUTI GFX VGA@
1 8 VGA_SMB_CK2 AD29 AU24
VDD SCLK T109 GENLK_CLK NC#AU24
1 T110
AC29 AV23 VGA@ 1 VGA@ 1 SM010030010 200ma
GENLK_VSYNC NC#AV23
0.1U_0402_16V4Z
C824

1U_0402_6.3V6K
C825

10U_0603_6.3V6M
C826
@ GPU_THERM_D+ 2 7 VGA_SMB_DA2
2200P_0402_50V7K D+ SDATA AT25 120ohm@100mhz DCR 0.2
C827 1 2 3 6 THM_ALERT# AJ21 NC#AT25 AR24 AV33 XTALIN
2 @ D- ALERT# AK21 SWAPLOCKA DPA NC#AR24 XTALIN 2 2
GPU_THERM_D- 4 5 1 @ 2 SWAPLOCKB AU26
THERM# GND +3VSDGPU NC#AU26
R798 4.7K_0402_5% AV25
NC#AV25 L65
ADM1032ARMZ-2REEL_MSOP8 AR8 AT27
75mA
MBK1608121YZF_0603
AU8 NC#AR8 NC#AT27 AR26 +SPLL_PVDD 2 1
NC#AU8 NC#AR26 +1.8VSDGPU
T111
AP8 AU34 XTALOUT VGA@
+3VSDGPU AW8 DBG_CNTL0 AR30 XTALOUT
1 AR3 NC#AW8 NC#AR30 AT29 VGA@ 1 VGA@ 1 1
+3VSDGPU NC#AR3 NC#AT29

1U_0402_6.3V6K
C829

10U_0603_6.3V6M
C830
AR1
AU1 NC#AR1 AV31 +MPLL_PVDD H7
T112 DBG_DATA0 NC#AV31 MPLL_PVDD

2
AU3 AU30 H8
T113 DBG_DATA1 DPB NC#AU30 MPLL_PVDD 2 2
R800 R801 T114
AW3
4.7K_0402_5% 4.7K_0402_5% AP6 DBG_DATA2 AR32 AW34 XO_IN 1 @ 2
T115 DBG_DATA3 NC#AR32 XO_IN

5
VGA@ VGA@ Q54A VGA@ T118
AW5 AT31 0_0402_5% R799
DBG_DATA4 NC#AT31

m
DMN66D0LDW-7_SOT363-6 AU5 +SPLL_PVDD AM10

PLLS/XTAL
T117
1

VGA_SMB_CK2 1 4 3 EC_SMB_CK2 T119

AR6 DBG_DATA5 AT33 SPLL_PVDD
100mA L66
EC_SMB_CK2 <22,6> AW6 DBG_DATA6 NC#AT33 AU32

D
T121 MBK1608121YZF_0603
AU6 DBG_DATA7 NC#AU32 +SPLL_VDDC 2 1
T120 DBG_DATA8 +0.95VSDGPU

2
Q54B VGA@ T122
AT7 AU14 +SPLL_VDDC AN9 AW35 XO_IN2 2 @ 1 VGA@
DMN66D0LDW-7_SOT363-6 AV7 DBG_DATA9 NC#AU14 AV13 SPLL_VDDC XO_IN2 0_0402_5% R802

G
T124 DBG_DATA10 NC#AV13
VGA_SMB_DA2 1 6 EC_SMB_DA2 AN7 VGA@ 1 VGA@ 1
EC_SMB_DA2 <22,6> T123 DBG_DATA11

1U_0402_6.3V6K
C832

10U_0603_6.3V6M
C833
AV9 AT15

D
T125 DBG_DATA12 NC#AT15
AT9 AR14 AN10
T127 DBG_DATA13 NC#AR14 SPLL_PVSS
AR10
T126 DBG_DATA14

o
AW10 DPC AU16 2 2
T128 DBG_DATA15 NC#AU16
AU10 AV15
T130 DBG_DATA16 NC#AV15
T129
AP10 AK10 T137
AV11 DBG_DATA17 AT17 AF30 CLKTESTA AL10
T131 DBG_DATA18 NC#AT17 NC_XTAL_PVDD CLKTESTB T138
T133
AT11 AR16 AF31
DBG_DATA19 NC#AR16 NC_XTAL_PVSS

0.1U_0402_16V4Z 51.1_0402_1%

0.1U_0402_16V4Z 51.1_0402_1%
T132
AR12 1 1
DBG_DATA20

C892

C891
T134
AW12 AU20 @ @ Mars MLPS configuration
AU12 DBG_DATA21 NC#AU20 AT19

.c
T136 DBG_DATA22 NC#AT19
AP12
T135 DBG_DATA23 AT21 2 2 Bits[5:1] PU(1%) PD(1%) Cap
NC#AT21 AR20
R908 0_0402_5% NC#AR20 2160842006A0MARSXT_FCBGA962
xx000 NC 4.75k

1
VGA_SMB_CK2 1 RS@ 2VGA_SMB_CK2_R AJ23 DPD AU22 @
SMBCLK SMBus NC#AU22 xx001 8.45k 2.00k

R910

R841
VGA_SMB_DA2 1 RS@ 2VGA_SMB_DA2_R AH23 AV21 @ @
R909 0_0402_5% SMBDATA NC#AV21
AT23 xx010 4.53k 2.00k
+3VSDGPU NC#AT23 AR22
Slave ID: 0x41 xx011 6.98k 4.99k

2
AK26 NC#AR22
AJ26 SCL I2C
2 SDA xx100 4.53k 4.99k 2

x
2

R409 AD39
100K_0402_5% R AD37
T154 xx101 3.24k 5.62k
GENERAL PURPOSE I/O
VGA@ GPU_DPRSLPVR AH20 AVSSN
VGA@
<42> GPU_DPRSLPVR AH18 GPIO_0 AE36
xx110 3.40k 10.0k
GPIO_1 G T156
AN16 AD35
xx111 4.75k NC
1

1 2 GPU_ACIN_D GPIO_2 AVSSN

<22> GPU_ACIN AUD[1:0]:
AF37

fi
D7 00 - No audio function
RB751V-40 SOD-323 GPU_ACIN_D AH17 B AE38
T155 00xxx 680nF
GPU_VID4 AJ17 GPIO_5_AC_BATT AVSSN
<42> GPU_VID4 AK17 GPIO_6_TACH DAC1 AC36 AUD_1 R803 1 @ 2 10K_0402_5%
01xxx 82nF
AJ13 GPIO_7_BLON HSYNC AC38 AUD_0 R804 1 2 10K_0402_5%
AH15 GPIO_8_ROMSO VSYNC @
10xxx 10nF
GPU_VID5 AJ16 GPIO_9_ROMSI
<42> GPU_VID5 AK16 GPIO_10_ROMSCK AB34 RSET R805 1 MARS@ 2 499_0402_1%
10mil 11xxx NC
AL16 GPIO_11 RSET (SUN NC) L67
AM16 GPIO_12 AD34 +AVDD 2 1
70mA
+1.8VSDGPU

a
AM14 GPIO_13 AVDD AE34 (SUN NC) MARS@
GPIO_14_HPD2 AVSSQ

1U_0402_6.3V6K
C834

0.1U_0402_16V4Z
C835
GPU_VID1 AM13 1 1 0_0603_5%
<42> GPU_VID1 AK14 GPIO_15_PWRCNTL_0 AC33
GPU_VID3 +VDD1DI PS0_[1]=1 : same as GPIO_11 Since the frame buffer size is 512 MB
<42> GPU_VID3 AG30 GPIO_16 VDD1DI AC34
THM_ALERT# PS0_[2]=0 : same as GPIO_12 the aperture size is set to 256 MB.
AN14 GPIO_17_THERMAL_INT VSS1DI @ @
R806 10K_0402_5% 1 @ 2 GPIO_19_CTF AM17 GPIO_18_HPD3 (SUN NC) 2 2 PS0_[3]=0 : same as GPIO_13
GPU_VID2 AL13 GPIO_19_CTF V13 PS0_[4]=1 : Reserved for internal use only. Must be 1
<42> GPU_VID2 GPIO_20_PWRCNTL_1 NC#V13

in
AJ14 U13 PS0_[5]=1 : AUD_PORT_CONN_PINSTRAP[0]
AK13 GPIO_21 NC#U13 AF33
AN13 GPIO_22_ROMCSB NC#AF33 AF32
10mil
T140 CLKREQB NC#AF32
L68 100 - 512Kbit M25P05A (ST)
AA29 117mA 0_0603_5% 101 - 1Mbit M25P10A (ST)
(GPIO1, 2, 7, 11, 12, 13, 18, 21 is NC at SUN) NC#AA29 AG21 2 1
NC#AG21 +1.8VSDGPU 101 - 2Mbit M25P20 (ST)
AG32 AC32 MARS@
AG33 GPIO_29 NC#AC32 101 - 4Mbit M25P40 (ST)
GPIO_30 1 1@

0.1U_0402_16V4Z
C837

1U_0402_6.3V6K
C838
AC31 @ 101 - 8Mbit M25P80 (ST)
AJ19 NC_SVI2#AC31 AD30
GENERICA NC_SVI2#AD30 100 - 512Kbit Pm25LV512 (Chingis)
AK19 AD32
AJ20 GENERICB NC_SVI2#AD32 2 2 101 - 1Mbit Pm25LV010 (Chingis)
AK20 GENERICC
3 3
GENERICD

VREFG:Use a voltage divider to set

VREFG = 1.80 V / 3 (or 0.60-V nominal).
AJ24
AH26
AH24

AC30
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

CEC_1
h PS_0
AM34 PS_0
PS_1[1]
PS_1[2]
PS_1[3]
PS_1[4]
PS_1[5]
=
=
=
=
=
0
0
0
1
1
:
:
:
:
:
PCIeR GEN3 is not supported.
Reserved for internal use only
Reserved for internal use only
TX_PWRS_ENB: Full Tx output swing.
TX_DEEMPH_EN: Tx deemphasis enabled.
.c
+1.8VSDGPU R810 1 MARS@ 2 499_0402_1% AK24 AD31 PS_1
HPD1 MLPS PS_1
20mil PS_2[1] = 0 : Reserved.
R811 1 MARS@ 2 249_0402_1% PS_2[2] = 0 : Reserved.
C841 1 2 0.1U_0402_16V4Z +VGA_VREF AH13 AG31 PS_2 PS_2[3] = 0 : BIOS_ROM_EN :Disable the external BIOS ROM device.
MARS@ (SUN NC) DBG_VREFG PS_2 PS_2[4] = 0 : VGA_DIS : 0=VGA controller capacity enabled.
PS_2[5] = 1 : Reserved.
Place VREFG divider and cap close to ASIC BACO
AL21 AD33 PS_3
PX_EN PS_3
2

Pull high @ VGA side

R813
R814 +VDDC_CT +VDDC_CT +VDDC_CT +VDDC_CT PS_3[1] = x :
w

0_0402_5%
+3VSDGPU 5.11K_0402_1%
@ DEBUG DDC/AUX
PS_3[2] = x : VRAM ID
2 @ 1 AM26
PS_3[3] = x :
1

DDC1CLK

1
AN26
2 VGA@ 1 TESTEN AD28 DDC1DATA X76@ @ @ VGA@ PS_3[4] = 1 : AUD_PORT_CONN_PINSTRAP[1]
+3VSDGPU TESTEN AM27
VGA@ R817 1K_0402_5% R812 R822 R816 R808 PS_3[5] = 1 : AUD_PORT_CONN_PINSTRAP[2]
R824 AUX1P AL27 10K_0402_5% 10K_0402_5% 10K_0402_5% 8.45K_0402_1%
1M_0402_5% RP21 AUX1N

2
XTALOUT 2 1 XTALIN 1 8 JTAG_TRSTB AM23 AM19 PS_0 ======= VRAM ID for Jet =======
2 7 JTAG_TDI AN23 JTAG_TRSTB DDC2CLK AL19 PS_1
w

X2 3 6 JTAG_TCK AK23 JTAG_TDI DDC2DATA PS_2

VGA@ 4 5 JTAG_TMS AL24 JTAG_TCK AN20 PS_3 000 Hynix S IC D3 128M16 H5TC2G63FFR-11C*4(SA00006H430)
Crystal T18 @ AM24 JTAG_TMS AUX2P AM20 001 Micron S IC D3 128M16 MT41J128M16JT-093G:K*4(SA000067550)
3 4 JTAG_TDO AUX2N
OUT GND
10K_0804_8P4R_5% @ @ @ @ 010 Samsung S IC D3 128M16 K4W2G1646Q-BC1A*4(SA000068U90)

1
@ AL30 1 1 1 1 011 Hynix S IC D3 256M16 H5TC4G63AFR-11C*4(SA00006E840)
NC#AL30
.1U_0402_16V7K
C842

0.01U_0402_16V7K
C847

.1U_0402_16V7K
C843

.1U_0402_16V7K
C840
2 1 AM30 X76@
4 GND IN NC#AM30 R815 R823 R821 R809
100 Micron S IC D3 256M16 MT41J256M16HA-093G:E*4(SA000077K20) 4
2 2
THERMAL AL29 10K_0402_5% 4.75K_0402_1% 4.75K_0402_1% 2K_0402_1% 101 Samsung S IC D3 256M16 K4W4G1646D-BC1A*4(SA000076P20)
+3VSDGPU GPU_THERM_D+ AF29 NC#AL29 AM29 2 2 2 2
w

VGA@ C848 27MHZ_10PF_X3G027000BA1H-U C849 VGA@ VGA@ VGA@ VGA@

2
10P_0402_50V8J 10P_0402_50V8J GPU_THERM_D- AG29 DPLUS NC#AM29
1 1 1 @ 2 DMINUS AN21
R819 10K_0402_5% NC#AN21 AM21
1 VGA@ 2 MLPS_EN# AK32 NC#AM21
R820 10K_0402_5% GPIO_28_FDO AK30
AL31 NC#AK30 AK29
+1.8VSDGPU TS_A NC#AK29
L69 13mA 10mil AJ30 Security Classification Compal Secret Data Compal Electronics, Inc.
1 RS@ 2 0_0603_5% +TSVDD AJ32 DDCVGACLK AJ31 2014/03/27 2016/03/27 Title
Crystals must have a max ESR of 80 ohm AJ33 TSVDD
TSVSS
DDCVGADATA Issued Date Deciphered Date MARS-Pro_STRAP
10U_0603_6.3V6M 2 1 @ C844
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1U_0402_6.3V6K 2 1 @ C845 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.1U_0402_16V4Z 2 1 VGA@ C846 2160842006A0MARSXT_FCBGA962 Custom 1.0
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 13 of 45
A B C D E
 A B C D E

U75D MAA[0..15]
MAA[0..15] <17>
U75C
PART 4 0F 9 DQMA#[0..7]
PART 3 0F 9 MDB[0..63] DQMA#[0..7] <17>
MDA[0..63] <18> MDB[0..63] GDDR5/DDR3 QSA[0..7]
GDDR5/DDR3 MDB0 C5 P8 MAB0
<17> MDA[0..63] DQB0_0 MAB0_0/MAB_0 QSA[0..7] <17>
MDA0 C37 G24 MAA0 MDB1 C3 T9 MAB1
MDA1 C35 DQA0_0 MAA0_0/MAA_0 J23 MAA1 MDB2 E3 DQB0_1 MAB0_1/MAB_1 P9 MAB2 QSA#[0..7]
DQA0_1 MAA0_1/MAA_1 DQB0_2 MAB0_2/MAB_2 QSA#[0..7] <17>
(SUN 64 bin on at Channel B) MDA2 A35 H24 MAA2 MDB3 E1 N7 MAB3
MDA3 E34 DQA0_2 MAA0_2/MAA_2 J24 MAA3 MDB4 F1 DQB0_3 MAB0_3/MAB_3 N8 MAB4
MDA4 G32 DQA0_3 MAA0_3/MAA_3 H26 MAA4 MDB5 F3 DQB0_4 MAB0_4/MAB_4 N9 MAB5
DQA0_4 MAA0_4/MAA_4 DQB0_5 MAB0_5/MAB_5

MEMORY INTERFACE A
MDA5 D33 J26 MAA5 MDB6 F5 U9 MAB6
MDA6 F32 DQA0_5 MAA0_5/MAA_5 H21 MAA6 MDB7 G4 DQB0_6 MAB0_6/MAB_6 U8 MAB7 MAB[0..15]
DQA0_6 MAA0_6/MAA_6 DQB0_7 MAB0_7/MAB_7 MAB[0..15] <18>
MDA7 E32 G21 MAA7 MDB8 H5 Y9 MAB8
1
MDA8 D31 DQA0_7 MAA0_7/MAA_7 H19 MAA8 MDB9 H6 DQB0_8 MAB1_0/MAB_8 W9 MAB9 DQMB#[0..7] 1
DQA0_8 MAA1_0/MAA_8 DQB0_9 MAB1_1/MAB_9 DQMB#[0..7] <18>
MDA9 F30 H20 MAA9 MDB10 J4 AC8 MAB10
MDA10 C30 DQA0_9 MAA1_1/MAA_9 L13 MAA10 MDB11 K6 DQB0_10 MAB1_2/MAB_10 AC9 MAB11 QSB[0..7]
DQA0_10 MAA1_2/MAA_10 DQB0_11 MAB1_3/MAB_11 QSB[0..7] <18>
MDA11 A30 G16 MAA11 MDB12 K5 AA7 MAB12
MDA12 F28 DQA0_11 MAA1_3/MAA_11 J16 MAA12 MDB13 L4 DQB0_12 MAB1_4/MAB_12 AA8 B_BA2 QSB#[0..7]

MEMORY INTERFACE B
DQA0_12 MAA1_4/MAA_12 DQB0_13 MAB1_5/BA2 B_BA2 <18> QSB#[0..7] <18>

m
MDA13 C28 H16 A_BA2 MDB14 M6 Y8 B_BA0
+1.5VSDGPU DQA0_13 MAA1_5/MAA_BA2 A_BA2 <17> DQB0_14 MAB1_6/BA0 B_BA0 <18>
MDA14 A28 J17 A_BA0 MDB15 M1 AA9 B_BA1
DQA0_14 MAA1_6/MAA_BA0 A_BA0 <17> DQB0_15 MAB1_7/BA1 B_BA1 <18>
MDA15 E28 H17 A_BA1 MDB16 M3
DQA0_15 MAA1_7/MAA_BA1 A_BA1 <17> DQB0_16
MDA16 D27 MDB17 M5 H3 DQMB#0
MDA17 F26 DQA0_16 A32 DQMA#0 MDB18 N4 DQB0_17 W CKB0_0/DQMB_0 H1 DQMB#1
DQA0_17 W CKA0_0/DQMA_0 DQB0_18 W CKB0B_0/DQMB_1
1

MDA18 C26 C32 DQMA#1 MDB19 P6 T3 DQMB#2

R826 MDA19 A26 DQA0_18 W CKA0B_0/DQMA_1 D23 DQMA#2 MDB20 P5 DQB0_19 W CKB0_1/DQMB_2 T5 DQMB#3
MDA20 F24 DQA0_19 W CKA0_1/DQMA_2 E22 DQMA#3 MDB21 R4 DQB0_20 W CKB0B_1/DQMB_3 AE4 DQMB#4
DQA0_20 W CKA0B_1/DQMA_3 DQB0_21 W CKB1_0/DQMB_4

o
40.2_0402_1% 15mil MDA21 C24 C14 DQMA#4 MDB22 T6 AF5 DQMB#5
MARS@ MDA22 A24 DQA0_21 W CKA1_0/DQMA_4 A14 DQMA#5 MDB23 T1 DQB0_22 W CKB1B_0/DQMB_5 AK6 DQMB#6 +1.5VSDGPU
2

MVREFDA MDA23 E24 DQA0_22 W CKA1B_0/DQMA_5 E10 DQMA#6 MDB24 U4 DQB0_23 W CKB1_1/DQMB_6 AK5 DQMB#7
MDA24 C22 DQA0_23 W CKA1_1/DQMA_6 D9 DQMA#7 MDB25 V6 DQB0_24 W CKB1B_1/DQMB_7
DQA0_24 W CKA1B_1/DQMA_7 DQB0_25
1

1 MARS@ MDA25 A22 MDB26 V1 F6 QSB0

DQA0_25 DQB0_26 EDCB0_0/QSB_0

1
1U_0402_6.3V6K
C850

R828 MDA26 F22 C34 QSA0 MDB27 V3 K3 QSB1

DQA0_26 EDCA0_0/QSA_0 DQB0_27 EDCB0_1/QSB_1

.c
MDA27 D21 D29 QSA1 MDB28 Y6 P3 QSB2 R825
100_0402_1% MDA28 A20 DQA0_27 EDCA0_1/QSA_1 D25 QSA2 MDB29 Y1 DQB0_28 EDCB0_2/QSB_2 V5 QSB3 VGA@
MARS@ 2 MDA29 F20 DQA0_28 EDCA0_2/QSA_2 E20 QSA3 MDB30 Y3 DQB0_29 EDCB0_3/QSB_3 AB5 QSB4 40.2_0402_1% 15mil
2

MDA30 D19 DQA0_29 EDCA0_3/QSA_3 E16 QSA4 MDB31 Y5 DQB0_30 EDCB1_0/QSB_4 AH1 QSB5

2
MDA31 E18 DQA0_30 EDCA1_0/QSA_4 E12 QSA5 MDB32 AA4 DQB0_31 EDCB1_1/QSB_5 AJ9 QSB6 MVREFDB
MDA32 C18 DQA0_31 EDCA1_1/QSA_5 J10 QSA6 MDB33 AB6 DQB1_0 EDCB1_2/QSB_6 AM5 QSB7
DQA1_0 EDCA1_2/QSA_6 DQB1_1 EDCB1_3/QSB_7

1
MDA33 A18 D7 QSA7 MDB34 AB1
DQA1_1 EDCA1_3/QSA_7 DQB1_2
1

MDA34 F18 MDB35 AB3 G7 QSB#0 1 VGA@

+1.5VSDGPU DQA1_2 DQB1_3 DDBIB0_0/QSB_0B

1U_0402_6.3V6K
C851
R911 MDA35 D17 A34 QSA#0 MDB36 AD6 K1 QSB#1 R827 VGA@
0_0402_5% MDA36 A16 DQA1_3 DDBIA0_0/QSA_0B E30 QSA#1 MDB37 AD1 DQB1_4 DDBIB0_1/QSB_1B P1 QSB#2 100_0402_1%

x
@ MDA37 F16 DQA1_4 DDBIA0_1/QSA_1B E26 QSA#2 MDB38 AD3 DQB1_5 DDBIB0_2/QSB_2B W4 QSB#3
2 2

2
MDA38 D15 DQA1_5 DDBIA0_2/QSA_2B C20 QSA#3 MDB39 AD5 DQB1_6 DDBIB0_3/QSB_3B AC4 QSB#4 2
2

DQA1_6 DDBIA0_3/QSA_3B DQB1_7 DDBIB1_0/QSB_4B

1

MDA39 E14 C16 QSA#4 MDB40 AF1 AH3 QSB#5

R829 MDA40 F14 DQA1_7 DDBIA1_0/QSA_4B C12 QSA#5 MDB41 AF3 DQB1_8 DDBIB1_1/QSB_5B AJ8 QSB#6
MDA41 D13 DQA1_8 DDBIA1_1/QSA_5B J11 QSA#6 MDB42 AF6 DQB1_9 DDBIB1_2/QSB_6B AM3 QSB#7
DQA1_9 DDBIA1_2/QSA_6B DQB1_10 DDBIB1_3/QSB_7B

1
40.2_0402_1% 15mil MDA42 F12 F8 QSA#7 MDB43 AG4

fi
MARS@ MDA43 A12 DQA1_10 DDBIA1_3/QSA_7B MDB44 AH5 DQB1_11 T7 ODTB0 R912
ODTB0 <18>
2

MVREFSA MDA44 D11 DQA1_11 J21 ODTA0 MDB45 AH6 DQB1_12 ADBIB0/ODTB0 W7 ODTB1 0_0402_5%
DQA1_12 ADBIA0/ODTA0 ODTA0 <17> DQB1_13 ADBIB1/ODTB1 ODTB1 <18> +1.5VSDGPU
MDA45 F10 G19 ODTA1 MDB46 AJ4 @
DQA1_13 ADBIA1/ODTA1 ODTA1 <17> DQB1_14
1

1 MARS@ MDA46 A10 MDB47 AK3 L9 CLKB0

CLKB0 <18>

2
DQA1_14 DQB1_15 CLKB0
1U_0402_6.3V6K
C852

R830 MDA47 C10 H27 CLKA0 MDB48 AF8 L8 CLKB0#

DQA1_15 CLKA0 CLKA0 <17> DQB1_16 CLKB0B CLKB0# <18>
MDA48 G13 G27 CLKA0# MDB49 AF9
DQA1_16 CLKA0B CLKA0# <17> DQB1_17

1
100_0402_1% MDA49 H13 MDB50 AG8 AD8 CLKB1
2 DQA1_17 DQB1_18 CLKB1 CLKB1 <18>

a
MARS@ MDA50 J13 J14 CLKA1 MDB51 AG7 AD7 CLKB1# R832
CLKA1 <17> CLKB1# <18>
2

MDA51 H11 DQA1_18 CLKA1 H14 CLKA1# MDB52 AK9 DQB1_19 CLKB1B VGA@
DQA1_19 CLKA1B CLKA1# <17> DQB1_20
MDA52 G10 MDB53 AL7 T10 RASB0# 40.2_0402_1% 15mil
DQA1_20 DQB1_21 RASB0B RASB0# <18>
MDA53 G8 K23 RASA0# MDB54 AM8 Y10 RASB1#
RASA0# <17> RASB1# <18>

2
MDA54 K9 DQA1_21 RASA0B K19 RASA1# MDB55 AM7 DQB1_22 RASB1B MVREFSB
DQA1_22 RASA1B RASA1# <17> DQB1_23
MDA55 K10 MDB56 AK1 W 10 CASB0#
DQA1_23 DQB1_24 CASB0B CASB0# <18>

1
in
MDA56 G9 K20 CASA0# MDB57 AL4 AA10 CASB1# 1 VGA@
DQA1_24 CASA0B CASA0# <17> DQB1_25 CASB1B CASB1# <18>

1U_0402_6.3V6K
C853
MDA57 A8 K17 CASA1# MDB58 AM6 R831
DQA1_25 CASA1B CASA1# <17> DQB1_26
MDA58 C8 MDB59 AM1 P10 CSB0# VGA@
DQA1_26 DQB1_27 CSB0B_0 CSB0# <18>
MDA59 E8 K24 CSA0# MDB60 AN4 L10 100_0402_1%
DQA1_27 CSA0B_0 CSA0# <17> DQB1_28 CSB0B_1 2
MDA60 A6 K27 MDB61 AP3

2
MDA61 C6 DQA1_28 CSA0B_1 MDB62 AP1 DQB1_29 AD10 CSB1#
DQA1_29 DQB1_30 CSB1B_0 CSB1# <18>
MDA62 E6 M13 CSA1# MDB63 AP5 AC10
DQA1_30 CSA1B_0 CSA1# <17> DQB1_31 CSB1B_1
MDA63 A5 K16
DQA1_31 CSA1B_1 U10 CKEB0
CKEB0 CKEB0 <18>
MVREFDA L18 K21 CKEA0 MVREFDB Y12 AA11 CKEB1
3
MVREFSA L20

L27
N12
AG12
MVREFDA
MVREFSA

NC#L27
NC#N12
NC#AG12
CKEA0
CKEA1

W EA0B
W EA1B
J20

K26
L15
CKEA1

WEA0#
WEA1# h CKEA0 <17>
CKEA1 <17>

WEA0# <17>
WEA1# <17>
MVREFSB AA12 MVREFDB
MVREFSB
CKEB1

W EB0B
W EB1B
N10
AB11

T8
WEB0#
WEB1#

MAB13
CKEB1 <18>

WEB0# <18>
WEB1# <18>
3
.c
H23 MAA13 MAB0_8/MAB_13 W8 MAB14
R835 1 VGA@ 2 MEM_CALRP0 M27 MAA0_8/MAA_13 J19 MAA14 MAB1_8/MAB_14 U12 MAB15
120_0402_1% MEM_CALRP0 MAA1_8/MAA_14 M21 MAA15 MAB0_9/MAB_15 V12
M12 MAA0_9/MAA_15 M20 MAB1_9/RSVD
AH12 NC#M12 MAA1_9/RSVD AH11 1 2 1 2
NC#AH12 DRAM_RST VRAM_RST# <17,18>
VGA@ VGA@
R838 R839

2
10_0402_5% 1 VGA@ 51.1_0402_1%
2160842006A0MARSXT_FCBGA962 VGA@ C854
@ R840 120P_0402_50V8
w

2160842006A0MARSXT_FCBGA962 4.99K_0402_1%
@ 2

1
Place all these components very close
to GPU (Within 25mm) and
w

keep all component close to

each Other (within5mm) except Rser2

The suggested components are tested on the AMD

reference board only. Customers must measure the slew
on each memory part to ensure that the slew rate meets
w

4 the DRAM specification. 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2014/03/27 2016/03/27 Title
Issued Date Deciphered Date MARS-Pro_MEMORY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 14 of 45
A B C D E
 A B C D E

U75E
PART 5 0F 9

1.5A AC7
MEM I/O
AA31
+1.5VSDGPU
VGA@ @ VGA@ @ VGA@ AD11 VDDR1 NC#AA31 AA32
20mil
VDDR1 NC#AA32 +1.8VSDGPU

0.01U_0402_16V7K
C856

0.01U_0402_16V7K
C857

0.01U_0402_16V7K
C860

0.01U_0402_16V7K
C861

0.01U_0402_16V7K
C863
1 1 1 1 1 AF7 AA33 VGA@ @ @
AG10 VDDR1 NC#AA33 AA34
VDDR1 NC#AA34 1 1 1

1U_0402_6.3V6K
C871

1U_0402_6.3V6K
C862

10U_0603_6.3V6M
C866
AJ7 W30 NC For Mars
AK8 VDDR1 NC#W30 Y31
2 2 2 2 2 AL9 VDDR1 NC#Y31 V28
G11 VDDR1 NC_BIF_VDDC W29 2 2 2
1
G14 VDDR1 NC_BIF_VDDC AB37
100mA 1

PCIE
G17 VDDR1 PCIE_PVDD
G20 VDDR1 G30
VGA@ @ VGA@ @ VGA@ G23 VDDR1 PCIE_VDDC G31
VDDR1 PCIE_VDDC +0.95VSDGPU

0.1U_0402_16V4Z
C864

0.1U_0402_16V4Z
C865

0.1U_0402_16V4Z
C868

0.1U_0402_16V4Z
C867

0.1U_0402_16V4Z
C870
1 1 1 1 1 G26 H29 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
G29 VDDR1 PCIE_VDDC H30 2.5A 100mil 1 1 1 1 1 1

m
VDDR1 PCIE_VDDC

1U_0402_6.3V6K
C869

1U_0402_6.3V6K
C872

1U_0402_6.3V6K
C873

1U_0402_6.3V6K
C874

1U_0402_6.3V6K
C875

10U_0603_6.3V6M
C876
H10 J29
J7 VDDR1 PCIE_VDDC J30
2 2 2 2 2 J9 VDDR1 PCIE_VDDC L28
K11 VDDR1 PCIE_VDDC M28 2 2 2 2 2 2
K13 VDDR1 PCIE_VDDC N28
K8 VDDR1 PCIE_VDDC R28
L12 VDDR1 PCIE_VDDC T28
VGA@ VGA@ VGA@ @ @ VGA@ VGA@ VGA@ L16 VDDR1 PCIE_VDDC U28
VDDR1 PCIE_VDDC

2.2U_0402_6.3V6M
C880

2.2U_0402_6.3V6M
C881

2.2U_0402_6.3V6M
C882

2.2U_0402_6.3V6M
C883

2.2U_0402_6.3V6M
C884
1 1 1 1 1 1 1 1 L21
VDDR1
10U_0603_6.3V6M
C877

10U_0603_6.3V6M
C878

10U_0603_6.3V6M
C879

o
L23
L26 VDDR1 N27
L7 VDDR1 BACO BIF_VDDC T27
1.4A 60mil
2 2 2 2 2 2 2 2 VDDR1 BIF_VDDC +0.95VSDGPU
M11 VGA@ VGA@ VGA@
N11 VDDR1
VDDR1 1 1 1

1U_0402_6.3V6K
C890

1U_0402_6.3V6K
C889

10U_0603_6.3V6M
C888
P7 AA15 +VGA_CORE
R11 VDDR1 CORE VDDC AA17
VDDR1 VDDC

.c
U11 AA20 30A (TBD)
U7 VDDR1 VDDC AA22 2 2 2
Y11 VDDR1 VDDC AA24
Y7 VDDR1 VDDC AA27
VDDR1 VDDC AB16
VDDC AB18
VDDC AB21
VDDC AB23
+VDDC_CT VDDC AB26
20mil 13mA LEVEL VDDC
Must always be connected to PCIE_VDDC.
TRANSLATION AB28 0.95 V for "Mars" and
2 1 +VDDC_CT AF26 VDDC AC17
+1.8VSDGPU VDD_CT VDDC "Heathrow"/"Chelsea" on both BACO and
L72 VGA@ VGA@ AF27 AC20

x
2 VDD_CT VDDC non-BACO designs. 2

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V4Z
MBK1608121YZF_0603 1 1 1 AG26 AC22
VGA@ @ AG27 VDD_CT VDDC AC24
VDD_CT VDDC

C885

C886

C887
AC27
VDDC AD18
2 2 2 10mil 25mA VDDC AD21
I/O
+VDDR3 AF23 VDDC AD23
VDDR3 VDDC

fi
AF24 AD26
AG23 VDDR3 VDDC AF17
2 1 AG24 VDDR3 VDDC AF20
+3VSDGPU VDDR3 VDDC
L74 @ VGA@ VGA@ AF22
VDDC
1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z
MBK1608121YZF_0603 AG16
1 1 1 300mA DVP
VDDC
C896

C897

C898
VGA@ AD12 AG18
AF11 VDDR4 VDDC
AF12 VDDR4 AH22
2 2 2 AF13 VDDR4 VDDC AH27
VDDR4 VDDC

a
AH28
VDDC M26
AF15 VDDC N24
AG11 VDDR4 VDDC R18
20mil AG13 VDDR4 VDDC R21
2 1 +VDDR4 AG15 VDDR4 VDDC R23
+1.8VSDGPU VDDR4 VDDC
L73 MARS@ MARS@ R26
VDDC

in
0.1U_0402_16V4Z

MBK1608121YZF_0603 1 1 1 (SUN NC) T17

VDDC
10U_0603_6.3V6M
C907

1U_0402_6.3V6K
C908

C899

MARS@ @ T20
VDDC T22
VDDC T24
2 2 2 VDDC U16
VDDC U18
VDDC U21
VDDC U23
VDDC U26
VDDC V17
VDDC V20
VDDC V22
3

h VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
V24
V27
Y16
Y18
Y21
Y23
Y26
3
.c
VDDC Y28
VDDC
AA13 360mil
VDDCI AB13
VDDCI +VGA_CORE
AC12
VDDCI AC15 VGA@ VGA@ VGA@
VDDCI AD13
3.5A (DDR3)
VDDCI

0.1U_0402_16V4Z
C917

0.1U_0402_16V4Z
C918

0.1U_0402_16V4Z
C919
AD16 1 1 1
VDDCI M15
VDDCI M16
VDDCI M18
w

VOLTAGE VDDCI M23 2 2 2

ISOLATED

10mil SENESE VDDCI

CORE I/O

N13
VCC_GPU_SENSE AF28 VDDCI N15
<42> VCC_GPU_SENSE FB_VDDC VDDCI N17
VDDCI N20
AG28 VDDCI N22
T139 FB_VDDCI VDDCI R12
VDDCI R13
VDDCI
w

VSS_GPU_SENSE AH29 R16

<42> VSS_GPU_SENSE FB_GND VDDCI T12
VDDCI T15
VDDCI V15
VDDCI
1

Y13
@ VDDCI
R842
0_0402_5% 2160842006A0MARSXT_FCBGA962
@
w
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

2014/03/27 2016/03/27 Title
Issued Date Deciphered Date MARS-Pro_PWR/GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 15 of 45
A B C D E
 A B C D E

U75F
PART 6 0F 9
U75H
AB39 A3
E39 PCIE_VSS GND A37 PART 8 0F 9
F34 PCIE_VSS GND AA16
F39 PCIE_VSS GND AA18 DP_VDDR DP_VDDC
G33 PCIE_VSS GND AA2 AP31
20mil
G34 PCIE_VSS GND AA21 DP_VDDC AP32
PCIE_VSS GND DP_VDDC +0.95VSDGPU
H31 AA23 AN33
H34 PCIE_VSS GND AA26 DP_VDDC AP33
H39 PCIE_VSS GND AA28 AN24 DP_VDDC AL33
280mA
PCIE_VSS GND NC#AN24 DP_VDDC 1 VGA@ 1 VGA@ 1 VGA@

0.1U_0402_16V4Z
C955

1U_0402_6.3V6K
C952

10U_0603_6.3V6M
C953
J31 AA6 AP24 AM33
J34 PCIE_VSS GND AB12 AP25 NC#AP24 DP_VDDC AK33
1 K31 PCIE_VSS GND AB15 AP26 NC#AP25 DP_VDDC AK34 1
K34 PCIE_VSS GND AB17 AU28 NC#AP26 DP_VDDC AN31 2 2 2
K39 PCIE_VSS GND AB20 AV29 NC#AU28 DP_VDDC
L31 PCIE_VSS GND AB22 NC#AV29
L34 PCIE_VSS GND AB24
M34 PCIE_VSS GND AB27 AP20 AP13

m
M39 PCIE_VSS GND AC11 AP21 NC#AP20 NC#AP13 AT13
N31 PCIE_VSS GND AC13 AP22 NC#AP21 NC#AT13 AP14
N34 PCIE_VSS GND AC16 AP23 NC#AP22 NC#AP14 AP15
P31 PCIE_VSS GND AC18 AU18 NC#AP23 NC#AP15
P34 PCIE_VSS GND AC2 AV19 NC#AU18
P39 PCIE_VSS GND AC21 NC#AV19 DP GND
R34 PCIE_VSS GND AC23 AN27
T31 PCIE_VSS GND AC26 AH34 DP_VSSR AP27
T34 PCIE_VSS GND AC28 AJ34 DP_VDDR DP_VSSR AP28

o
T39 PCIE_VSS GND AC6 AF34 DP_VDDR DP_VSSR AW24
U31 PCIE_VSS GND AD15 AG34 DP_VDDR DP_VSSR AW26
U34 PCIE_VSS GND AD17 AM37 DP_VDDR DP_VSSR AN29
V34 PCIE_VSS GND AD20
237mA AL38 DP_VDDR DP_VSSR AP29
V39 PCIE_VSS GND AD22 AM32 DP_VDDR DP_VSSR AP30
PCIE_VSS GND +1.8VSDGPU DP_VDDR DP_VSSR
W31 AD24 @ VGA@ VGA@ AW30
PCIE_VSS GND DP_VSSR

.c
10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V4Z
W34 AD27 1 1 1 AW32
PCIE_VSS GND DP_VSSR

C956

C951

C954
Y34 AD9 AN17
Y39 PCIE_VSS GND AE2 DP_VSSR AP16
PCIE_VSS GND AE6 DP_VSSR AP17 R406
GND AF10 2 2 2 DP_VSSR AW14 0_0402_5%
GND AF16 DP_VSSR AW16 2 @ 1
GND AF18 DP_VSSR AN19
GND AF21 DP_VSSR AP18
GND GND DP_VSSR
AG17 AP19 +3VALW
F15 GND AG2 DP_VSSR AW20
F17 GND GND AG20 CALIBRATION DP_VSSR AW22

x
GND GND DP_VSSR

5
2 F19 AN34 2
F21 GND AG6 DP_VSSR AP39 R807

VCC
F23 GND GND AG9 AW28 DP_VSSR AR39 10K_0402_5% 1
F25 GND GND AH21 NC#AW28 DP_VSSR AU37 1 VGA@ 2 IN1 4 VGA_ON
F27 GND GND AJ10 DP_VSSR AF39 <7> PE_GPIO1 2 OUT

GND
GND GND DP_VSSR IN2

2
F29 AJ11 AH39

fi
GND GND DP_VSSR 1
F31 AJ2 AW18 AK39 @ R913
F33 GND GND AJ28 NC#AW18 DP_VSSR AL34 100K_0402_5% VGA@ C178

3
F7 GND GND AJ6 R845 DP_VSSR AV27 0.22U_0402_10V6K U38
F9 GND GND AK11 150_0402_1% DP_VSSR AR28 2 MC74VHC1G08DFT2G_SC70-5

1
G2 GND GND AK31 2 MARS@ 1 AM39 DP_VSSR AV17 VGA@
G6 GND GND AK7 DP_CALR DP_VSSR AR18
H9 GND GND AL11 DP_VSSR AN38
GND GND DP_VSSR
Delay 2ms
J2 AL14 AM35

a
J27 GND GND AL17 DP_VSSR AN32
J6 GND GND AL2 DP_VSSR +3VALW
J8 GND GND AL20
K14 GND GND
GND

5
K7 AL23
L11 GND GND AL26

VCC
GND GND

in
L17 AL32 R833 VGA_ON 1
L2 GND GND AL6 2160842006A0MARSXT_FCBGA962 33K_0402_5% IN1 4 VGA_ON_B
L22 GND GND AL8 1 VGA@ 2 2 OUT VGA_ON_B <42>
@

GND
GND GND +3VSDGPU IN2
L24 AM11 1
L6 GND GND AM31
M17 GND GND AM9 VGA@ C185

3
M22 GND GND AN11 0.22U_0402_10V6K U39
M24 GND GND AN2 2 MC74VHC1G08DFT2G_SC70-5
N16 GND GND AN30 VGA@
N18 GND GND AN6
N2 GND GND AN8

3
N21
N23
N26
N6
R15
R17
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AP11
AP7
AP9
AR5
B11
B13
h +1.8VALW TO +1.8VSDGPU
+0.95VALW TO +0.95VSDGPU
Load switch
+3VS TO +3VSDGPU
3
.c
R2 B15
R20 GND GND B17
R22 GND GND B19
R24 GND GND B21
GND GND
VIN 1.8V and 0.95V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
R27 B23
R6 GND GND B25
T11 GND GND B27 +1.8VALW +1.8VSDGPU
T13 GND GND B29 U1895 JP11JP@ +3VS +3VSDGPU
T16 GND GND B31 1 14 +1.8VSDGPU_LS U74 VGA@
T18 GND GND B33 2 VIN1 VOUT1 13 1
100mil(1.5A)
T21 GND GND B7 VIN1 VOUT1 JUMP_43X118 5 VOUT
w

T23 GND GND B9 R127 1 RS@ 2 0_0402_5% 3 12 VGA@ 1 2 VIN

GND GND <41,42,7> VGA_PWRGD ON1 CT1 2
T26 C1 2200P_0402_50V7K C35 2
U15 GND GND C39 4 11 4 GND C621
GND GND +5VALW VBIAS GND SS
U17 E35 2 VGA@
U2 GND GND E5 VGA_ON 1 VGA@ 2 5 10 VGA@ 1 2 C620 3 1 4.7U_0603_6.3V6K
U20 GND GND F11 R128 ON2 CT2 2200P_0402_50V7K C28 +0.95VSDGPU 4.7U_0603_6.3V6K EN
U22 GND GND F13 47K_0402_5% +0.95VALW 6 9 JP12JP@ VGA@ AP2821KTR-G1_SOT23-5
GND GND VIN2 VOUT2 1
w

U24 7 8 +0.95VSDGPU_LS
U27 GND VIN2 VOUT2
GND
Delay 4ms
U6 15 JUMP_43X118 2 C31 2 C32
V11 GND AG22 GPAD
GND NC#AG22 1 C39 1 C40 1 C29 1 C30 @ @

0.1U_0402_16V4Z
V16 @ VGA@ @ @ TPS22966DPUR_SON14_2X3 VGA_ON
GND
1U_0402_6.3V6K

0.22U_0402_10V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V4Z
V18 VGA@
V21 GND 1 1
V23 GND 2 2 2 2
GND
w

V26
4 W2 GND 4
W6 GND
Y15 GND
Y17 GND
Y20 GND
Y22 GND A39
GND VSS_MECH T116
Y24 AW1
GND VSS_MECH T141
Y27 AW39
GND VSS_MECH T142 Security Classification Compal Secret Data Compal Electronics, Inc.
2014/03/27 2016/03/27 Title
Issued Date Deciphered Date MARS-Pro_PWR/GND
2160842006A0MARSXT_FCBGA962
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
@ Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 16 of 45
A B C D E
 A B C D E

U54 U55 U58 U57

VREFCA_A1 M8 E3 MDA23 VREFDA_Q1 M8 E3 MDA25 VREFCA_A3 M8 E3 MDA35 VREFDA_Q3 M8 E3 MDA48

VREFDA_Q1 H1 VREFCA DQL0 F7 MDA19 VREFCA_A1 H1 VREFCA DQL0 F7 MDA30 VREFDA_Q3 H1 VREFCA DQL0 F7 MDA32 VREFCA_A3 H1 VREFCA DQL0 F7 MDA51
VREFDQ DQL1 F2 MDA22 VREFDQ DQL1 F2 MDA24 VREFDQ DQL1 F2 MDA38 VREFDQ DQL1 F2 MDA55
MAA0 N3 DQL2 F8 MDA18 MAA0 N3 DQL2 F8 MDA29 MAA0 N3 DQL2 F8 MDA34 MAA0 N3 DQL2 F8 MDA54
MAA1 P7 A0 DQL3 H3 MDA21 MAA1 P7 A0 DQL3 H3 MDA26 MAA1 P7 A0 DQL3 H3 MDA37 MAA1 P7 A0 DQL3 H3 MDA50
MAA2 P3 A1 DQL4 H8 MDA16 MAA2 P3 A1 DQL4 H8 MDA31 MAA2 P3 A1 DQL4 H8 MDA36 MAA2 P3 A1 DQL4 H8 MDA52
MAA3 N2 A2 DQL5 G2 MDA20 MAA3 N2 A2 DQL5 G2 MDA27 MAA3 N2 A2 DQL5 G2 MDA39 MAA3 N2 A2 DQL5 G2 MDA49
MAA4 P8 A3 DQL6 H7 MDA17 MAA4 P8 A3 DQL6 H7 MDA28 MAA4 P8 A3 DQL6 H7 MDA33 MAA4 P8 A3 DQL6 H7 MDA53
MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7 MAA5 P2 A4 DQL7
MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5 MAA6 R8 A5
MAA[0..15] MAA7 R2 A6 D7 MDA0 MAA7 R2 A6 D7 MDA14 MAA7 R2 A6 D7 MDA43 MAA7 R2 A6 D7 MDA63
<14> MAA[0..15] MAA8 T8 A7 DQU0 C3 MDA5 MAA8 T8 A7 DQU0 C3 MDA11 MAA8 T8 A7 DQU0 C3 MDA44 MAA8 T8 A7 DQU0 C3 MDA58
MDA[0..63] MAA9 R3 A8 DQU1 C8 MDA1 MAA9 R3 A8 DQU1 C8 MDA12 MAA9 R3 A8 DQU1 C8 MDA40 MAA9 R3 A8 DQU1 C8 MDA60
1 <14> MDA[0..63] MAA10 L7 A9 DQU2 C2 MDA7 MAA10 L7 A9 DQU2 C2 MDA10 MAA10 L7 A9 DQU2 C2 MDA45 MAA10 L7 A9 DQU2 C2 MDA59 1
DQMA#[0..7] MAA11 R7 A10/AP DQU3 A7 MDA3 MAA11 R7 A10/AP DQU3 A7 MDA13 MAA11 R7 A10/AP DQU3 A7 MDA42 MAA11 R7 A10/AP DQU3 A7 MDA61
<14> DQMA#[0..7] MAA12 N7 A11 DQU4 A2 MDA4 MAA12 N7 A11 DQU4 A2 MDA9 MAA12 N7 A11 DQU4 A2 MDA46 MAA12 N7 A11 DQU4 A2 MDA56
QSA[0..7] MAA13 T3 A12 DQU5 B8 MDA2 MAA13 T3 A12 DQU5 B8 MDA15 MAA13 T3 A12 DQU5 B8 MDA41 MAA13 T3 A12 DQU5 B8 MDA62
<14> QSA[0..7] MAA14 T7 A13 DQU6 A3 MDA6 MAA14 T7 A13 DQU6 A3 MDA8 MAA14 T7 A13 DQU6 A3 MDA47 MAA14 T7 A13 DQU6 A3 MDA57
QSA#[0..7] MAA15 M7 A14 DQU7 MAA15 M7 A14 DQU7 MAA15 M7 A14 DQU7 MAA15 M7 A14 DQU7

m
<14> QSA#[0..7] A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU

M2 B2 A_BA0 M2 B2 A_BA0 M2 B2 A_BA0 M2 B2

<14> A_BA0 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9 N8 BA0 VDD D9
A_BA1 A_BA1 A_BA1
<14> A_BA1 M3 BA1 VDD G7 A_BA2 M3 BA1 VDD G7 A_BA2 M3 BA1 VDD G7 A_BA2 M3 BA1 VDD G7
<14> A_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1
CLKA0 J7 VDD N9 CLKA0 J7 VDD N9 CLKA1 J7 VDD N9 CLKA1 J7 VDD N9

o
CLKA0# K7 CK VDD R1 CLKA0# K7 CK VDD R1 CLKA1# K7 CK VDD R1 CLKA1# K7 CK VDD R1
K9 CK VDD R9 CKEA0 K9 CK VDD R9 K9 CK VDD R9 CKEA1 K9 CK VDD R9
<14> CKEA0 CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU <14> CKEA1 CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU

ODTA0 K1 A1 ODTA0 K1 A1 ODTA1 K1 A1 ODTA1 K1 A1

<14> ODTA0 L2 ODT/ODT0 VDDQ A8 L2 ODT/ODT0 VDDQ A8 <14> ODTA1 L2 ODT/ODT0 VDDQ A8 L2 ODT/ODT0 VDDQ A8
CSA0# CSA1#
<14> CSA0# CS/CS0 VDDQ CS/CS0 VDDQ <14> CSA1# CS/CS0 VDDQ CS/CS0 VDDQ

.c
J3 C1 RASA0# J3 C1 J3 C1 RASA1# J3 C1
<14> RASA0# K3 RAS VDDQ C9 CASA0# K3 RAS VDDQ C9 <14> RASA1# K3 RAS VDDQ C9 CASA1# K3 RAS VDDQ C9
<14> CASA0# L3 CAS VDDQ D2 WEA0# L3 CAS VDDQ D2 <14> CASA1# L3 CAS VDDQ D2 WEA1# L3 CAS VDDQ D2
<14> WEA0# WE VDDQ E9 WE VDDQ E9 <14> WEA1# WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSA2 F3 VDDQ H2 QSA3 F3 VDDQ H2 QSA4 F3 VDDQ H2 QSA6 F3 VDDQ H2
QSA0 C7 DQSL VDDQ H9 QSA1 C7 DQSL VDDQ H9 QSA5 C7 DQSL VDDQ H9 QSA7 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

DQMA#2 E7 A9 DQMA#3 E7 A9 DQMA#4 E7 A9 DQMA#6 E7 A9

DQMA#0 D3 DML VSS B3 DQMA#1 D3 DML VSS B3 DQMA#5 D3 DML VSS B3 DQMA#7 D3 DML VSS B3

x
2 DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1 2
VSS G8 VSS G8 VSS G8 VSS G8
QSA#2 G3 VSS J2 QSA#3 G3 VSS J2 QSA#4 G3 VSS J2 QSA#6 G3 VSS J2
QSA#0 B7 DQSL VSS J8 QSA#1 B7 DQSL VSS J8 QSA#5 B7 DQSL VSS J8 QSA#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9

fi
VSS P1 VSS P1 VSS P1 VSS P1
VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9
<14,18> VRAM_RST# RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1
R846 L1 NC/ODT1 VSSQ B9 R847 L1 NC/ODT1 VSSQ B9 R848 L1 NC/ODT1 VSSQ B9 R849 L1 NC/ODT1 VSSQ B9

a
243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1 243_0402_1% J9 NC/CS1 VSSQ D1
128@ L9 NC/CE1 VSSQ D8 128@ L9 NC/CE1 VSSQ D8 128@ L9 NC/CE1 VSSQ D8 128@ L9 NC/CE1 VSSQ D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2

2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1 VSSQ G1 VSSQ G1
VSSQ VSSQ VSSQ VSSQ

in
G9 G9 G9 G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96
128X76@ 128X76@ 128X76@ 128X76@
+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU +1.5VSDGPU
1

1
R850 R851 R854 R855
3
4.99K_0402_1%
128@
15mil
4.99K_0402_1%
128@
15mil h 4.99K_0402_1%
128@
15mil
4.99K_0402_1%
128@
15mil
3
2

2
VREFCA_A1 VREFDA_Q1 VREFCA_A3 VREFDA_Q3
1

1
.c
1 1 1 1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
R858 C957 R859 R862 C962 R863 C977
4.99K_0402_1% 4.99K_0402_1% C984 4.99K_0402_1% 4.99K_0402_1% 128@
128@ 128@ 128@ 128@ 128@ 128@ 128@
2 2 2 2
2

2
+1.5VSDGPU
+1.5VSDGPU +1.5VSDGPU +1.5VSDGPU
w

128@ 128@ 128@ 128@ 128@

128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@ 1 1 1 1 1

1U_0402_6.3V6K
C965

1U_0402_6.3V6K
C963

1U_0402_6.3V6K
C964

1U_0402_6.3V6K
C982

1U_0402_6.3V6K
C988
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K
C968

1U_0402_6.3V6K
C960

1U_0402_6.3V6K
C987

1U_0402_6.3V6K
C958

1U_0402_6.3V6K
C967

1U_0402_6.3V6K
C976

1U_0402_6.3V6K
C972

1U_0402_6.3V6K
C983

1U_0402_6.3V6K
C961

1U_0402_6.3V6K
C959

1U_0402_6.3V6K
C979

1U_0402_6.3V6K
C986

1U_0402_6.3V6K
C981

1U_0402_6.3V6K
C966

1U_0402_6.3V6K
C980
128@
1 2
<14> CLKA0 2 2 2 2 2
R866 40.2_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
w

128@
1 2
<14> CLKA0#
R867 40.2_0402_1%
+1.5VSDGPU +1.5VSDGPU
1
+1.5VSDGPU +1.5VSDGPU
C395
0.01U_0402_16V7K 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@
2 128@ 128@ 128@ 128@ 128@ 128@ 128@ 128@
128@ 1 1 1 1 1 1 1 1
w

10U_0603_6.3V6M
C975

10U_0603_6.3V6M
C973

10U_0603_6.3V6M
C974

10U_0603_6.3V6M
C978

10U_0603_6.3V6M
C1029

10U_0603_6.3V6M
C1028

10U_0603_6.3V6M
C1027

10U_0603_6.3V6M
C1030
4
1 1 1 1 1 1 1 1 4
128@
10U_0603_6.3V6M
C969

10U_0603_6.3V6M
C985

10U_0603_6.3V6M
C970

10U_0603_6.3V6M
C971

10U_0603_6.3V6M
C1024

10U_0603_6.3V6M
C1026

10U_0603_6.3V6M
C1023

10U_0603_6.3V6M
C1025

1 2
<14> CLKA1 2 2 2 2 2 2 2 2
R868 40.2_0402_1%
2 2 2 2 2 2 2 2
128@
1 2
<14> CLKA1#
R869 40.2_0402_1%
1 Security Classification Compal Secret Data Compal Electronics, Inc.
C406 Issued Date 2014/03/27 2016/03/27 Title
Deciphered Date
2
0.01U_0402_16V7K
128@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3 / Channel A
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Z5WAE LA-B231P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 17 of 45
A B C D E
 A B C D E

U59 U62 U60 U61

VREFCB_A1 M8 E3 MDB31 VREFDB_Q1 M8 E3 MDB23 VREFCB_A3 M8 E3 MDB35 VREFDB_Q3 M8 E3 MDB55

VREFDB_Q1 H1 VREFCA DQL0 F7 MDB26 VREFCB_A1 H1 VREFCA DQL0 F7 MDB16 VREFDB_Q3 H1 VREFCA DQL0 F7 MDB37 VREFCB_A3 H1 VREFCA DQL0 F7 MDB49
VREFDQ DQL1 F2 MDB25 VREFDQ DQL1 F2 MDB22 VREFDQ DQL1 F2 MDB34 VREFDQ DQL1 F2 MDB52
MAB0 N3 DQL2 F8 MDB29 MAB0 N3 DQL2 F8 MDB18 MAB0 N3 DQL2 F8 MDB39 MAB0 N3 DQL2 F8 MDB50
MAB1 P7 A0 DQL3 H3 MDB28 MAB1 P7 A0 DQL3 H3 MDB21 MAB1 P7 A0 DQL3 H3 MDB33 MAB1 P7 A0 DQL3 H3 MDB53
MAB2 P3 A1 DQL4 H8 MDB30 MAB2 P3 A1 DQL4 H8 MDB19 MAB2 P3 A1 DQL4 H8 MDB38 MAB2 P3 A1 DQL4 H8 MDB48
MAB[0..15] MAB3 N2 A2 DQL5 G2 MDB24 MAB3 N2 A2 DQL5 G2 MDB20 MAB3 N2 A2 DQL5 G2 MDB32 MAB3 N2 A2 DQL5 G2 MDB54
<14> MAB[0..15] P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7 P8 A3 DQL6 H7
MAB4 MDB27 MAB4 MDB17 MAB4 MDB36 MAB4 MDB51
MDB[0..63] MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7 MAB5 P2 A4 DQL7
<14> MDB[0..63] MAB6 R8 A5 MAB6 R8 A5 MAB6 R8 A5 MAB6 R8 A5
DQMB#[0..7] MAB7 R2 A6 D7 MDB12 MAB7 R2 A6 D7 MDB2 MAB7 R2 A6 D7 MDB46 MAB7 R2 A6 D7 MDB59
<14> DQMB#[0..7] T8 A7 DQU0 C3 T8 A7 DQU0 C3 T8 A7 DQU0 C3 T8 A7 DQU0 C3
MAB8 MDB11 MAB8 MDB4 MAB8 MDB43 MAB8 MDB62
1 QSB[0..7] MAB9 R3 A8 DQU1 C8 MDB15 MAB9 R3 A8 DQU1 C8 MDB0 MAB9 R3 A8 DQU1 C8 MDB47 MAB9 R3 A8 DQU1 C8 MDB58 1
<14> QSB[0..7] MAB10 L7 A9 DQU2 C2 MDB9 MAB10 L7 A9 DQU2 C2 MDB6 MAB10 L7 A9 DQU2 C2 MDB41 MAB10 L7 A9 DQU2 C2 MDB63
QSB#[0..7] MAB11 R7 A10/AP DQU3 A7 MDB13 MAB11 R7 A10/AP DQU3 A7 MDB3 MAB11 R7 A10/AP DQU3 A7 MDB44 MAB11 R7 A10/AP DQU3 A7 MDB56
<14> QSB#[0..7] A11 DQU4 A11 DQU4 A11 DQU4 A11 DQU4
MAB12 N7 A2 MDB8 MAB12 N7 A2 MDB7 MAB12 N7 A2 MDB42 MAB12 N7 A2 MDB61
MAB13 T3 A12 DQU5 B8 MDB14 MAB13 T3 A12 DQU5 B8 MDB1 MAB13 T3 A12 DQU5 B8 MDB45 MAB13 T3 A12 DQU5 B8 MDB57
MAB14 T7 A13 DQU6 A3 MDB10 MAB14 T7 A13 DQU6 A3 MDB5 MAB14 T7 A13 DQU6 A3 MDB40 MAB14 T7 A13 DQU6 A3 MDB60

m
MAB15 M7 A14 DQU7 MAB15 M7 A14 DQU7 MAB15 M7 A14 DQU7 MAB15 M7 A14 DQU7
A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU A15/BA3 +1.5VSDGPU

M2 B2 B_BA0 M2 B2 B_BA0 M2 B2 B_BA0 M2 B2

<14> B_BA0 N8 BA0 VDD D9 B_BA1 N8 BA0 VDD D9 B_BA1 N8 BA0 VDD D9 B_BA1 N8 BA0 VDD D9
<14> B_BA1 M3 BA1 VDD G7 B_BA2 M3 BA1 VDD G7 B_BA2 M3 BA1 VDD G7 B_BA2 M3 BA1 VDD G7
<14> B_BA2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2 BA2 VDD K2
VDD K8 VDD K8 VDD K8 VDD K8
VDD N1 VDD N1 VDD N1 VDD N1

o
CLKB0 J7 VDD N9 CLKB0 J7 VDD N9 CLKB1 J7 VDD N9 CLKB1 J7 VDD N9
CLKB0# K7 CK VDD R1 CLKB0# K7 CK VDD R1 CLKB1# K7 CK VDD R1 CLKB1# K7 CK VDD R1
K9 CK VDD R9 CKEB0 K9 CK VDD R9 K9 CK VDD R9 CKEB1 K9 CK VDD R9
<14> CKEB0 CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU <14> CKEB1 CKE/CKE0 VDD +1.5VSDGPU CKE/CKE0 VDD +1.5VSDGPU

ODTB0 K1 A1 ODTB0 K1 A1 ODTB1 K1 A1 ODTB1 K1 A1

<14> ODTB0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ <14> ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ

.c
L2 A8 CSB0# L2 A8 L2 A8 CSB1# L2 A8
<14> CSB0# J3 CS/CS0 VDDQ C1 RASB0# J3 CS/CS0 VDDQ C1 <14> CSB1# J3 CS/CS0 VDDQ C1 RASB1# J3 CS/CS0 VDDQ C1
<14> RASB0# K3 RAS VDDQ C9 CASB0# K3 RAS VDDQ C9 <14> RASB1# K3 RAS VDDQ C9 CASB1# K3 RAS VDDQ C9
<14> CASB0# L3 CAS VDDQ D2 WEB0# L3 CAS VDDQ D2 <14> CASB1# L3 CAS VDDQ D2 WEB1# L3 CAS VDDQ D2
<14> WEB0# WE VDDQ E9 WE VDDQ E9 <14> WEB1# WE VDDQ E9 WE VDDQ E9
VDDQ F1 VDDQ F1 VDDQ F1 VDDQ F1
QSB3 F3 VDDQ H2 QSB2 F3 VDDQ H2 QSB4 F3 VDDQ H2 QSB6 F3 VDDQ H2
QSB1 C7 DQSL VDDQ H9 QSB0 C7 DQSL VDDQ H9 QSB5 C7 DQSL VDDQ H9 QSB7 C7 DQSL VDDQ H9
DQSU VDDQ DQSU VDDQ DQSU VDDQ DQSU VDDQ

DQMB#3 E7 A9 DQMB#2 E7 A9 DQMB#4 E7 A9 DQMB#6 E7 A9

x
2 DQMB#1 D3 DML VSS B3 DQMB#0 D3 DML VSS B3 DQMB#5 D3 DML VSS B3 DQMB#7 D3 DML VSS B3 2
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
QSB#3 G3 VSS J2 QSB#2 G3 VSS J2 QSB#4 G3 VSS J2 QSB#6 G3 VSS J2
QSB#1 B7 DQSL VSS J8 QSB#0 B7 DQSL VSS J8 QSB#5 B7 DQSL VSS J8 QSB#7 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1

fi
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9 VRAM_RST# T2 VSS P9
<14,17> VRAM_RST# RESET VSS T1 RESET VSS T1 RESET VSS T1 RESET VSS T1
L8 VSS T9 L8 VSS T9 L8 VSS T9 L8 VSS T9
ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS ZQ/ZQ0 VSS
1

1
J1 B1 J1 B1 J1 B1 J1 B1

a
R870 L1 NC/ODT1 VSSQ B9 R871 L1 NC/ODT1 VSSQ B9 R872 L1 NC/ODT1 VSSQ B9 R873 L1 NC/ODT1 VSSQ B9
VGA@ J9 NC/CS1 VSSQ D1 VGA@ J9 NC/CS1 VSSQ D1 VGA@ J9 NC/CS1 VSSQ D1 VGA@ J9 NC/CS1 VSSQ D1
243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ 243_0402_1% NC/CE1 VSSQ
L9 D8 L9 D8 L9 D8 L9 D8
NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2 NCZQ1 VSSQ E2
2

2
VSSQ E8 VSSQ E8 VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9 VSSQ F9 VSSQ F9
VSSQ VSSQ VSSQ VSSQ

in
G1 G1 G1 G1
VSSQ G9 VSSQ G9 VSSQ G9 VSSQ G9
VSSQ VSSQ VSSQ VSSQ
96-BALL 96-BALL 96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3 SDRAM DDR3 SDRAM DDR3
MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96 MT41K256M16HA-107G_FBGA96
X76@ X76@ X76@ X76@
+1.5VSDGPU +1.5VSDGPU
+1.5VSDGPU +1.5VSDGPU
1

1
R874 R875
3 4.99K_0402_1% 4.99K_0402_1% R878 R879 3
VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1%
VGA@ VGA@
2

2
VREFCB_A1 VREFDB_Q1
.c
VREFCB_A3 VREFDB_Q3
1

1 1 +1.5VSDGPU

1
0.1U_0402_16V4Z

0.1U_0402_16V4Z

R882 C1034 R883 C989 1 1

0.1U_0402_16V4Z

0.1U_0402_16V4Z
4.99K_0402_1% 4.99K_0402_1% R886 C1039 R887 C992
VGA@ VGA@ VGA@ VGA@ 4.99K_0402_1% 4.99K_0402_1% VGA@ VGA@ VGA@ VGA@ VGA@
2 2 VGA@ VGA@ VGA@ VGA@ 1 1 1 1 1
2

2 2

1U_0402_6.3V6K
C1041

1U_0402_6.3V6K
C1019

1U_0402_6.3V6K
C1020

1U_0402_6.3V6K
C1018

1U_0402_6.3V6K
C1033
2

2
R890 40.2_0402_1% 2 2 2 2 2
1 VGA@ 2 +1.5VSDGPU +1.5VSDGPU
w

<14> CLKB0
+1.5VSDGPU

R891 40.2_0402_1% VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1 VGA@ 2 1 1 1 1 1 1 1 1 1 1 VGA@ VGA@ VGA@ VGA@ VGA@
<14> CLKB0#
1U_0402_6.3V6K
C1043

1U_0402_6.3V6K
C1051

1U_0402_6.3V6K
C990

1U_0402_6.3V6K
C1040

1U_0402_6.3V6K
C1031

1U_0402_6.3V6K
C991

1U_0402_6.3V6K
C993

1U_0402_6.3V6K
C1042

1U_0402_6.3V6K
C994

1U_0402_6.3V6K
C995

1 1 1 1 1

1U_0402_6.3V6K
C996

1U_0402_6.3V6K
C997

1U_0402_6.3V6K
C998

1U_0402_6.3V6K
C1017

1U_0402_6.3V6K
C1022
1
2 2 2 2 2 2 2 2 2 2
w

C409
+1.5VSDGPU 2 2 2 2 2 +1.5VSDGPU
0.01U_0402_16V7K
2 +1.5VSDGPU
VGA@
R892
40.2_0402_1%
1 VGA@ 2 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@ 1 1 1 1
<14> CLKB1
10U_0603_6.3V6M
C1013

10U_0603_6.3V6M
C1021

10U_0603_6.3V6M
C1032

10U_0603_6.3V6M
C1046

1 1 1 1 VGA@ VGA@ VGA@ VGA@

10U_0603_6.3V6M
C1038

10U_0603_6.3V6M
C1036

10U_0603_6.3V6M
C1035

10U_0603_6.3V6M
C1037
R893 VGA@ VGA@ VGA@ VGA@
w

10U_0603_6.3V6M
C1044

10U_0603_6.3V6M
C1014

10U_0603_6.3V6M
C1012

10U_0603_6.3V6M
C1045
40.2_0402_1%
4 1 VGA@ 2 +1.5VSDGPU 2 2 2 2 2 2 2 2 4
<14> CLKB1# 2 2 2 2
1
C410 1 VGA@ 1 VGA@ 1 VGA@ 1 VGA@
10U_0603_6.3V6M
C1047

10U_0603_6.3V6M
C1048

10U_0603_6.3V6M
C1050

10U_0603_6.3V6M
C1049

0.01U_0402_16V7K
2
VGA@
2 2 2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3 / Channel B
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Z5WAE LA-B231P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 18 of 45
A B C D E
 5 4 3 2 1

LCD POWER CIRCUIT

INVTPWM
+LCDVDD BKOFF#
+3VS U72 W=60mils

1
W=60mils 1
5 VOUT @
VIN 1
C522 R653 R899
D 4 GND
2 4.7U_0603_6.3V6K 100K_0402_5% 10K_0402_5% eDP PANEL Conn. D

2
SS 2
1
3
C1278 EN
1U_0402_6.3V6K AP2821KTR-G1_SOT23-5
2 ENVDD <6>

m
1
JLVDS1
100K_0402_5% 1
R652 +INVPWR_B+ 1
2 41
3 2 G1 42

2
4 3 G2 43
5 4 G3 44
5 G4

o
INVTPWM 6 45
<6> INVTPWM 7 6 G5 46
BKOFF#
<22> BKOFF# 7 G6
EDP_HPD 8
<6> EDP_HPD 8
EDP_TXP0 C27 1 2 .1U_0402_16V7K EDP_TXP0_C +LCDVDD
9
<6> EDP_TXP0 9
EDP_TXN0 C33 1 2 .1U_0402_16V7K EDP_TXN0_C 10
+INVPWR_B+ B+ <6> EDP_TXN0 10
L11 EMI@ TS_EN 11

.c
<22> TS_EN 11
HCB2012KF-221T30_0805 EDP_TXP1 C34 1 2 .1U_0402_16V7K EDP_TXP1_C 12
<6> EDP_TXP1 12
W=40mils 2 1 W=40mils EDP_TXN1 C36 1 2 .1U_0402_16V7K EDP_TXN1_C 13
<6> EDP_TXN1 1 2 14 13
+3VS @ TS_EN
@EMI@ 1 C44 1 2 .1U_0402_16V7K EDP_AUXN_C 15 14
1 @EMI@ SM010014520 3000ma <6> EDP_AUXN R1540
15
C364 C365 <6> EDP_AUXP C45 1 2 .1U_0402_16V7K EDP_AUXP_C 4.7K_0402_5% 16
C
1000P_0402_50V7K 68P_0402_50V8J
220ohm@100mhz 17 16 C

DCR 0.04 18 17
2 2 19 18
19

x
R9001 2 100K_0402_5% EDP_HPD 20
21 20
22 21
23 22
24 23
24

fi
EDP_AUXN_C 25
EDP_AUXP_C 26 25
27 26
EDP_TXP0_C 28 27
EDP_TXN0_C 29 28
30 29
EDP_TXP1_C 31 30
31

a
<8> USB20_P3 R696 1 @EMI@ 2 0_0402_5% USB20_P3_R EDP_TXN1_C 32
R1666 1 @ 2 0_0603_5% 33 32
+3VS 33
L58 EMI@ +5VS R1664 1 2 0_0603_5% +5VS_TS 34
1 2 USB20_P5 35 34
1 2 <8> USB20_P5 35
Touch Screen <8> USB20_N5
USB20_N5 36
R1663 1 RS@ 2 0_0603_5% +3VS_CMOS 37 36

in
+3VS 37
4 3 USB20_P3_R 38
4 3 For Camera USB20_N3_R 39 38
DLW21HN900HQ2L_4P 40 39
B B
R695 1 @EMI@ 2 0_0402_5% USB20_N3_R 40
<8> USB20_N3
E-T_0871K-F40N-00L
CONN@

USB20_N3 R697 1 @EMI@ 2 0_0402_5%

1
L59 @EMI@
1 2
2 h
USB20_N3_RR

JCAM1
.c
4 3 1
4 3 +3VS 1
USB20_P3_RR 2
DLW21HN900HQ2L_4P For Camera USB20_N3_RR 3 2 5
USB20_P3 R702 1 @EMI@ 2 0_0402_5% USB20_P3_RR 4 3 G1 6
4 G2
ACES_88266-04001
CONN@
SP02000K200
w

A A
w

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP/Camera/TS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
w

B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 19 of 45
5 4 3 2 1
 A B C D E

+5VS_DISP

2
1 2

2
@ESD@ D20 D21 @ESD@ C936 ESD@

1
AZC199-02SPR7G_SOT23-3 AZC199-02SPR7G_SOT23-3 .1U_0402_16V7K
JCRT1

1
6
L36 EMI@ 11
T25
1 2 CRT_RED 1
<6> DAC_RED 7
BLM15BB470SN1D_2P
1 L37 EMI@ CRT_DDC_DAT_CONN 12 1
1 2 CRT_GREEN 2
<6> DAC_GRN 8
BLM15BB470SN1D_2P
L38 EMI@ CRT_HSYNC_CONN 13
1 2 CRT_BLUE 3
<6> DAC_BLU
BLM15BB470SN1D_2P 9

m
C1094
6P_0402_50V8D

C1103
6P_0402_50V8D

C1104
6P_0402_50V8D

C1105
6P_0402_50V8D

C1106
6P_0402_50V8D

C1107
6P_0402_50V8D
CRT_VSYNC_CONN 14

1
2
3
4
4
T27

1
RP22 10 G 16
150_0804_8P4R_1% CRT_DDC_CLK_CONN 15 G 17
5

2
8
7
6
5
CCM_070546HR015M25FZR

o
CONN@
EMI@ EMI@ EMI@ EMI@ EMI@ EMI@

.c
+5VS_DISP

@
U10
1 2 1 8 1 2
2 VCC_SYNC BYP 2

@
C529 C23
.1U_0402_16V7K 0.22U_0402_10V6K
2 3 CRT_RED
+3VS VCC_VIDEO VIDEO1

x
1 2 7 4 CRT_GREEN
VCC_DDC VIDEO2

@
C537
.1U_0402_16V7K

fi
10 5 CRT_BLUE
<6> DAC_DDC_DATA DDC_IN1 VIDEO3

11 9 CRT_DDC_DAT
<6> DAC_DDC_CLK DDC_IN2 DDC_OUT1 RP10 EMI@
22_0804_8P4R_5%
13 12 CRT_DDC_CLK 1 8 CRT_DDC_DAT_CONN
<6> DAC_VSYNC SYNC_IN1 DDC_OUT2

a
2 7 CRT_DDC_CLK_CONN
3 6 CRT_VSYNC_CONN
15 14 CRT_VSYNC 4 5 CRT_HSYNC_CONN
<6> DAC_HSYNC SYNC_IN2 SYNC_OUT1

18P_0402_50V8J
C411 @

18P_0402_50V8J
C412 @

18P_0402_50V8J
C413 @

18P_0402_50V8J
C414 @
1 1 1 1
6 16 CRT_HSYNC

in
GND SYNC_OUT2
TPD7S019-15DBQR_SSOP16
2 2 2 2
3 3
+3VS
+5VS_DISP
U23
1 5 1 2 C1182 @
OE Vcc

2
0.1U_0402_16V4Z

h
G
DAC_HSYNC 2 DAC_DDC_CLK 1 6 CRT_DDC_CLK_CONN
IN A

D
Q2506B
3 4 CRT_HSYNC DMN66D0LDW-7_SOT363-6
GND OUT Y

5
Q2506A
.c
DMN66D0LDW-7_SOT363-6

G
M74VHC1GT125DF2G_SC70-5 4
DAC_DDC_DATA 3 CRT_DDC_DAT_CONN
+5VS_DISP

D
U24
1 5
OE Vcc +3VS
RP18
DAC_VSYNC 2 DAC_DDC_CLK 1 8 +5VS_DISP
IN A
w

DAC_DDC_DATA 2 7
CRT_DDC_CLK_CONN3 6
3 4 CRT_VSYNC CRT_DDC_DAT_CONN4 5
GND OUT Y
4 4.7K_0804_8P4R_5% 4
M74VHC1GT125DF2G_SC70-5
w

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CRT CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
w

B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 20 of 45
A B C D E
 5 4 3 2 1

RP15
C56 1 2 .1U_0402_16V7K HDMI_TX0- 1 8 HDMI_GND
<6> APU_DP1_N2 1 2 2 7 +5VS_DISP
C55 .1U_0402_16V7K HDMI_TX0+
<6> APU_DP1_P2
C52 1 2 .1U_0402_16V7K HDMI_TX2- 3 6 U73
<6> APU_DP1_N0 1 2 4 5
C51 .1U_0402_16V7K HDMI_TX2+ W=40mils
<6> APU_DP1_P0

6
D +5VS 3 D
499_0804_8P4R_1% 2
D
Q86B OUT
1
G
+3VS
S DMN66D0LDW-7_SOT363-6 1 @
RP16 IN C543

1
C58 1 2 .1U_0402_16V7K HDMI_CLK- 1 8 2 .1U_0402_16V7K
<6> APU_DP1_N3 GND 2
C57 1 2 .1U_0402_16V7K HDMI_CLK+ 2 7
<6> APU_DP1_P3

m
C54 1 2 .1U_0402_16V7K HDMI_TX1- 3 6
<6> APU_DP1_N1 1 2 4 5
C53 .1U_0402_16V7K HDMI_TX1+ AP2330W-7_SC59-3
<6> APU_DP1_P1
499_0804_8P4R_1% +3VS

o
@
R618 Q86A

5
1M_0402_5% DMN66D0LDW-7_SOT363-6
1 2

G
2
1 @ 2 4 3 HDMI_HPD_CONN

.c
<6> HDMI_HPD

D
R153 C942 ESD@

1
0_0402_5% 1 .1U_0402_16V7K
@ EMI@
R898 C59 JHDMI1 CONN@
100K_0402_5% 220P_0402_50V7K HDMI_HPD_CONN 19
C 2 HP_DET C
18
+5VS_DISP

2
17 +5V
HDMIDAT_R 16 DDC/CEC_GND
SDA

x
R756 1 @EMI@ 2 0_0402_5% HDMICLK_R 15
+3VS 14 SCL
Reserved

2
L39 @EMI@ 13
HDMI_CLK- 1 2 HDMI_R_CLK- HDMI_R_CLK- 12 CEC
1 2 @ESD@ 11 CK-
CK_shield

fi
C D42 HDMI_R_CLK+ 10
HDMI_CLK+ 4 3 HDMI_R_CLK+ 2 1 2HDMI_HPD_CONN YSLC05CH_SOT23-3 HDMI_R_TX0- 9 CK+
4 3 B R281 150K_0402_5% SCA00000U10 8 D0-
DLW21HN900HQ2L_4P E Q18 HDMI_R_TX0+ 7 D0_shield

3
D0+

1
HDMI_HPD MMBT3904_NL_SOT23-3 HDMI_R_TX1- 6
R765 1 @EMI@ 2 0_0402_5% R283 5 D1-

1
D1_shield

1
@ 365K_0402_1% HDMI_R_TX1+ 4 20
D1+ GND

a
HDMI_R_TX2- 3 21
R915 2 D2- GND 22

2
R769 1 @EMI@ 2 0_0402_5% 100K_0402_5% HDMI_R_TX2+ 1 D2_shield GND 23
D2+ GND

2
L40 @EMI@ SUYIN_100042GR019M23MZR
HDMI_TX0- 1 2 HDMI_R_TX0-

in
1 2

B HDMI_TX0+ 4 3 HDMI_R_TX0+ +3VS B

4 3 RP1
DLW21HN900HQ2L_4P HDMI_CLK 1 8 +5VS_DISP
HDMI_DATA 2 7
R779 1 @EMI@ 2 0_0402_5% HDMICLK_R 3 6
HDMIDAT_R 4 5

HDMI_TX1-
R781 1 @EMI@ 2 0_0402_5%

1
L41 @EMI@
1 2
2 HDMI_R_TX1-
HDMI_R_CLK-

HDMI_R_CLK+
1
@EMI@ C2562
1
@EMI@ C2563
HDMI_R_TX0- 1
@EMI@ C2564
2

2
h
10P_0402_50V8J

10P_0402_50V8J

10P_0402_50V8J
4.7K_0804_8P4R_5%

+3VS
.c
HDMI_TX1+ 4 3 HDMI_R_TX1+ HDMI_R_TX0+ 1 2
4 3 @EMI@ C2565 10P_0402_50V8J

2
DLW21HN900HQ2L_4P HDMI_R_TX1- 1 2
@EMI@ C2568 10P_0402_50V8J

G
R782 1 @EMI@ 2 0_0402_5% HDMI_R_TX1+ 1 2 <6> HDMI_CLK 1 6 HDMICLK_R

D
@EMI@ C2569 10P_0402_50V8J
R783 1 @EMI@ 2 0_0402_5% HDMI_R_TX2- 1 2 Q75A Q75B

5
@EMI@ C2570 10P_0402_50V8J DMN66D0LDW-7_SOT363-6
w

L42 @EMI@ HDMI_R_TX2+ 1 2 DMN66D0LDW-7_SOT363-6

G
HDMI_TX2- 1 2 HDMI_R_TX2- @EMI@ C2571 10P_0402_50V8J <6> HDMI_DATA 4 3 HDMIDAT_R
1 2

D
A HDMI_TX2+ 4 3 HDMI_R_TX2+
EMI request 1pF. A
4 3
DLW21HN900HQ2L_4P
w

R794 1 @EMI@ 2 0_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI CONN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
w

B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 21 of 45
5 4 3 2 1
 5 4 3 2 1

+EC_VCC

1
+3VLP +EC_VCC L44 +EC_VCCA
FBM-11-160808-601-T_0603
1 RS@ 2 1 2 R1562
Ra 100K_0402_5%

.1U_0402_16V7K
C1255

.1U_0402_16V7K
C1256

.1U_0402_16V7K
C1257

.1U_0402_16V7K
C1258

1000P_0402_50V7K
C1261

1000P_0402_50V7K
C1259
R1665 1

2
0_0603_5% 1 1 1 1 1 1
C1262 AD_BID
.1U_0402_16V7K

1
@ @ 2
2 2 2 2 2 2 1
R1564
ECAGND Rb 15K_0402_5% C1269 @

111
125
.1U_0402_16V7K +RTC_APU_R

22
33
96

67
9
U44 2

2
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC

1
D D
D Q91
EC_RTCRST 2 2N7002K_SOT23-3
GATEA20 1 21 LAN_PWR_EN G
<7> GATEA20 GATEA20/GPIO00 GPIO0F LAN_PWR_EN <23>

1
KBRST# 2 23 EC_BEEP# S
<7> KBRST# KBRST#/GPIO01 BEEP#/GPIO10 EC_BEEP# <25>
SERIRQ 3 26

3
<27,8> SERIRQ LPC_FRAME# 4 SERIRQ GPIO12 27 EC_RTCRST R1563

m
<27,7,8> LPC_FRAME# LPC_FRAME# ACOFF/GPIO13
LPC_AD3 5 100K_0402_5%
<27,8> LPC_AD3 7 LPC_AD3
LPC_AD2 PWM Output
<27,8> LPC_AD2

2
LPC_AD1 8 LPC_AD2 63 BATT_TEMP
<27,8> LPC_AD1 LPC_AD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP <33>
1 2 1 2 LPC_CLK0_EC LPC_AD0 10 64
C1263 @EMI@ R1560 @EMI@
<27,8> LPC_AD0 LPC_AD0LPC & MISC AD1/GPIO39 65 ADP_I
VCIN1_BATT_DROP <33>
ADP_I/AD2/GPIO3A ADP_I <33,34>
22P_0402_50V8J 10_0402_5% LPC_CLK0_EC 12 AD Input 66 AD_BID
<7,8> LPC_CLK0_EC 13 CLK_PCI_EC AD3/GPIO3B 75
LPC_RST#
1 9012@ 2 EC_RST# <27,7> LPC_RST# EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76 +3VS
+EC_VCC EC_RST# IMON/AD5/GPIO43
R818 47K_0402_5% EC_SCI# 20
1 2 <7> EC_SCI# 38 EC_SCII#/GPIO0E

o
C819 1000P_0402_50V7K <26> WLAN_ON GPIO1D EC_MUTE# R1565 1 @ 2 10K_0402_5%
ESD@ 68
DAC_BRIG/GPIO3C 70 EN_DFAN KBL_EN# <29> EC_I2C_ALERT# R116 1 @ 2 1K_0402_5%
<29> KSI[0..7] DA Output EN_DFAN1/GPIO3D EN_DFAN <27>
1 @ 2 LPC_RST# KSI0 55 71
56 KSI0/GPIO30 IREF/GPIO3E 72 TP_SENOFF# <29>
R207 100K_0402_5% KSI1
1 2 @ESD@ KSI2 57 KSI1/GPIO31 CHGVADJ/GPIO3F +EC_VCC
C1279 100P_0402_50V8J KSI3 58 KSI2/GPIO32 83 EC_MUTE#
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# <25>

.c
KSI4 59 84 USB_EN# EC_SMB_DA1 R1577 1 2 2.2K_0402_5%
KSI4/GPIO34 USB_EN#/GPIO4B USB_EN# <28>
KSI5 60 85 EC_I2C_TPCLK R124 1 @ 2 0_0402_5%
61 KSI5/GPIO35 CAP_INT#/GPIO4C 86 TP_I2C_CLK <29>
KSI6 PS2 Interface EC_I2C_TPDAT R125 1 @ 2 0_0402_5% EC_SMB_CK1 R1574 1 2 2.2K_0402_5%
KSI6/GPIO36 EAPD/GPIO4D TP_I2C_DAT <29>
KSI7 62 87 TP_CLK
<29> KSO[0..17] 39 KSI7/GPIO37 TP_CLK/GPIO4E 88 TP_CLK <29>
KSO0 TP_DATA LID_SW# R344 1 2 47K_0402_5%
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <29>
KSO1 40
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 ENBKL
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 ENBKL <6>
KSO4 43 98 GPU_ACIN
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 GPU_ACIN <13>
KSO5 0.95VS_PWR_EN#
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 9012_PH1
0.95VS_PWR_EN# <30>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 9012_PH1 <33>
KSO7/GPIO27 SPI Device Interface
KSO8 47

x
KSO9 48 KSO8/GPIO28 119
C C
49 KSO9/GPIO29 SPIDI/GPIO5B 120 EC_SPI_MISO <8>
KSO10
KSO10/GPIO2A SPIDO/GPIO5C EC_SPI_MOSI <8>
KSO11 50 SPI Flash ROM 126
KSO11/GPIO2B SPICLK/GPIO58 EC_SPI_CLK <8>
KSO12 51 128
52 KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS1# <8>
KSO13
KSO14 53 KSO13/GPIO2D
KSO14/GPIO2E
For share ROM reserved
KSO15 54 73

fi
KSO16 81 KSO15/GPIO2F ENBKL/AD6/GPIO40 74 VGATE 0.95_1.8VALW_PWREN 1 @ 2
KSO16/GPIO48 PECI_KB930/AD7/GPIO41 VGATE <39>
KSO17 82 89 R1575 4.7K_0402_5%
KSO17/GPIO49 FSTCHG/GPIO50 90 BATT_BLUE_LED#
BATT_CHG_LED#/GPIO52 BATT_BLUE_LED# <29>
91 TP_3V_EN EC_RSMRST# 1 @ 2
77 CAPS_LED#/GPIO53 92 TP_3V_EN <29>
EC_SMB_CK1 GPIO PWR_LED R1576 4.7K_0402_5%
<33,34> EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54
EC_SMB_DA1 78 93 BATT_AMB_LED#
<33,34> EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_AMB_LED# <29>
EC_SMB_CK2 79 SM Bus 95 SYSON
<13,6> EC_SMB_CK2 80 EC_SMB_CK2/GPIO46 SYSON/GPIO56 121 SYSON <36>
EC_SMB_DA2 VR_ON
<13,6> EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON <39>
127 0.95_1.8VALW_PWREN BATT_TEMP 1 2
PM_SLP_S4#/GPIO59 0.95_1.8VALW_PWREN <37,38>

a
C1265 100P_0402_50V8J
ACIN 1 2
SLP_S3# 6 100 EC_RSMRST# C1266 100P_0402_50V8J
1 RS@ 2 <7> SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_RSMRST# <7>
EC_I2C_ALERT# EC_LID_OUT#
<29> TP_I2C_INT# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# <7>
EC_SMI# 15 102 9012_VCIN 9012_VCIN <33> SYSON 1 2
<7> EC_SMI# 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103
R1683 EC_THERM R1675 100K_0402_5%
0_0402_5% 17 GPIO0A H_PROCHOT#_EC/GPXIOA06 104 MAINPWON ENBKL 1 2
<26> WL_OFF# GPIO0B VCOUT0_PH/GPXIOA07 MAINPWON <33,35>
18 GPO 105 BKOFF# R206 100K_0402_5%

in
<26> WLAN_WAKE# 19 GPIO0C BKOFF#/GPXIOA08 106 LAN_GPO BKOFF# <19> 3V_EN 1 2
<19> TS_EN GPIO0D GPIO PBTN_OUT#/GPXIOA09 LAN_GPO <23>
1 2 EC_SPOK 25 107 3V_EN R940 1M_0402_5%
<35> SPOK R1682 FAN_SPEED 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108 3V_EN <35>
0_0402_5% <27> FAN_SPEED LAN_WAKE# 29 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11
<23> LAN_WAKE# EC_PME#/GPIO15
EC_TX 30
<26> EC_TX 31 EC_TX/GPIO16 110
EC_RX ACIN
<26> EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN <34>
SYS_PWRGD_EC@1.8VALW SYS_PWRGD_EC 32 112 EC_ON
<7> SYS_PWRGD_EC 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON <35>
EC can be OD pin <29> PWR_SUSP_LED# PWR_SUSP_LED# ON/OFFBTN#
SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 ON/OFFBTN# <29>
36 GPI 115 LID_SW# 1 2 PROCHOT# <39,6,7>
for reduce Level shifter NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116 SUSP#
LID_SW# <29>
R1690 9022@
SUSP#/GPXIOD05 117 SUSP# <30,36>
0_0402_5%
GPXIOD06

1
118
PECI_KB9012/GPXIOD07

h +EC_VCC
AGND/AGND

PBTN_OUT# 122 D Q89 9012@

<7> PBTN_OUT# SLP_S5# 123 XCLKI/GPIO5D 124 V18R R16 1 9022@ 2 0_0603_5% EC_THERM 2 2N7002K_SOT23-3
GND/GND
GND/GND
GND/GND
GND/GND

B <7> SLP_S5# XCLKO/GPIO5E V18R B

1 G
GND0

S
C823 9012@

3
4.7U_0603_6.3V6K
KB9012QF-A4_LQFP128_14X14 2
11
24
35
94
113

69

Part Number = SA00004OB30 L43

.c
FBM-11-160808-601-T_0603
2 1

ECAGND
20mil
PWR_LED# <29>

1
D Q88
PWR_LED 2 2N7002K_SOT23-3
G

1
S
R208
w

3
100K_0402_5%

2
w
w

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB9012
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 22 of 45
5 4 3 2 1
 5 4 3 2 1

+3VALW +3V_LAN
JP@
JP14

JUMP_43X79
W=60mil W=60mil +LAN_VDD +3V_LAN
IDC=1200mA W=60mil
60mil U76
60mil L2506
300mA 1.4A
1 +REGOUT 1 2
5 VOUT 2.2UH_NLC252018T-2R2J-N_5%
VIN

4.7U_0603_6.3V6K
C2538

.1U_0402_16V7K
C2539

.1U_0402_16V7K
C2540

.1U_0402_16V7K
C2541

.1U_0402_16V7K
C2542

.1U_0402_16V7K
C2543

.1U_0402_16V7K
C2544

1U_0402_6.3V6K
C2545

.1U_0402_16V7K
C2546

4.7U_0603_6.3V6K
C2547

.1U_0402_16V7K
C2548

.1U_0402_16V7K
C2549

.1U_0402_16V7K
C2550
2 1 1 1 1 1 1 1 1 1 1 1 1 1
D GND D
4
SS
2
3 LAN_PWR_EN LAN_PWR_EN <22>
C2551 EN 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0402_6.3V6K AP2821KTR-G1_SOT23-5
1

m
Using for Switch mode
Place near Pin 3,8,33,46 Place near Pin 20 Using for Switch mode Place near Pin 11,32,48
From EC The trace length from Lx to
PIN48 (REGOUT) and from C to Lx Place near Pin 35
High active. must < 200mils.
EN threshold voltage min:1.2V typ:1.6V max:2.0V

o
Current limit threshold 1.5~2.8A

+3V_LAN Rising time must >0.5ms and <100ms

.c
EC_PME# pull high 10K to +3VALW on EC side
U2505
<7> APU_PCIE_WAKE# R2532 1 @ 2 0_0402_5% Power Manahement/Isolation
+3V_LAN ISOLATEB 31
R121 1 RS@ 2 0_0402_5% LAN_PME# 39 ISOLATEBPIN
<22> LAN_WAKE# LANWAKEB Card Reader
2

15 SD_D0 R2533 1 RS@ 2 0_0402_5% SD_D0_R

SD_D0/MS_D1 SD_D0_R <24>
R1566 PCI-Express 14 SD_D1 R2534 1 RS@ 2 0_0402_5% SD_D1_R
SD_D1 SD_D1_R <24>
10K_0402_5% <8> CLK_PCIE_LAN CLK_PCIE_LAN 23 16 SD_CLK R2538 1 EMI@ 2 10_0402_5% SD_CLK_R SD_CLK_R <24>
CLK_PCIE_LAN# 24 REFCLK_P SD_CLK/MS_D0 17 SD_CMD R2535 1 RS@ 2 0_0402_5% SD_CMD_R
<8> CLK_PCIE_LAN# REFCLK_N SD_CMD/MS_D2 SD_CMD_R <24>
18 SD_D3 R2536 1 RS@ 2 0_0402_5% SD_D3_R 2
SD_D3_R <24>
1

SD_D3/MS_D3

x
LAN_WAKE# APU_PCIE_RST# 30 19 SD_D2 R2537 1 RS@ 2 0_0402_5% SD_D2_R
<12,26,7> APU_PCIE_RST# SD_D2_R <24>
C LAN_CLKREQ# 29 PERSTBPIN SD_D2/MS_CLK 28 SD_WP SD_WP <24> C2554Reserve for EMI please close to IC C
<7> LAN_CLKREQ# CLKREQBPIN MS_BS/SD_WP#
5P_0402_50V8C
C2552 1 2 .1U_0402_16V7K PCIE_ARX_C_DTX_P1 25 1
C788,C791 <5> PCIE_ARX_DTX_P1
C2553 1 2 .1U_0402_16V7K PCIE_ARX_C_DTX_N1 26 HSOP @EMI@
<5> PCIE_ARX_DTX_N1 HSON
Place near Pin 25,26 <5> PCIE_ATX_C_DRX_P1 21 42 SD_CD# SD_CD# <24>
HSIP SD_CD#

fi
<5> PCIE_ATX_C_DRX_N1 22 43
+3VS HSIN MS_CD#
Transceiver Interface
1

LAN_MIDI0+ 1
<24> LAN_MIDI0+ MDIP0
R2540 LAN_MIDI0- 2
<24> LAN_MIDI0- MDIN0
10K_0402_5% LAN_MIDI1+ 4
<24> LAN_MIDI1+ MDIP1 +3V_LAN
@ LAN_MIDI1- 5 48
<24> LAN_MIDI1- MDIN1 HV_GIGA
LAN_MIDI2+ 6 11
<24> LAN_MIDI2+
2

LAN_CLKREQ# LAN_MIDI2- 7 MDIP2 HV_GIGA 12 1400mA

a
<24> LAN_MIDI2- MDIN2 VDD33
LAN_MIDI3+ 9 32
<24> LAN_MIDI3+ MDIP3 VDD33
LAN_MIDI3- 10
+3V_LAN <24> LAN_MIDI3- MDIN3
1

XTLI 44 33
R2541 XTLO R619 1 2 0_0402_5% XTLO_R 45 CKXTAL1 Clock VDD10 3
+LAN_VDD Protect cotact Card contact
CKXTAL2 AVDD10 8 300mA

in
10K_0402_5%
AVDD10
@
Regulator and Reference Write protect Write Enable
2

GPO 1 @ 2 +REGOUT 36 20
R620
LAN_GPO <22>
+3V_LAN 35 REG_OUT VDDTX (Lock) (Unlock)
0_0402_5% 34 VDDREG
SWR mode 800mA
+LAN_VDD 46 ENSWREG 13 +CARD_3V3
Card Uninsert Open Open Open
LV_GEN Card_3V3
LAN_RST 47 Card insert Open Close Close
RSET
1

27 +VDD33_18
R2542 DV33/18

h
.1U_0402_16V7K
C2555

4.7U_0603_6.3V6K
C2556

.1U_0402_16V7K
C2557
2.49K_0402_1% T22 41
Y2500 GPO 38 LED0
LED1/GPO 1 1 1
B 25MHZ_10PF_7V25000014 T23 37 LEDs B
2

40 LED2
T15 LED_CR
XTLI 1 3 XTLO 49 @
1 3 E_Pad 2 2 2
GND GND
2 2
.c
C99 2 4 C100
10P_0402_50V8J 10P_0402_50V8J Place near Pin 27
1 1
RTL8411B-CGT_QFN48_6X6
w

+3VS
1

R2543
1K_0402_5%
w
2

ISOLATEB
2

R2544
15K_0402_5%
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RTL8411-CG
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 23 of 45
5 4 3 2 1
 5 4 3 2 1

D D

LAN Connector

m
JRJ1 CONN@

T2500

o
LAN_TERMAL1 24 RJ45_MIDI0+ 1 9
LAN_MIDI3- 2 TCT1 MCT1 23 RJ45_MIDI3- PR1+ SHLD1 10
<23> LAN_MIDI3- TD1+ MX1+ SHLD2
<23> LAN_MIDI3+ LAN_MIDI3+ 3 22 RJ45_MIDI3+ RJ45_MIDI0- 2
TD1- MX1- PR1-
4 21 RJ45_MIDI1+ 3
TCT2 MCT2 PR2+

.c
<23> LAN_MIDI2- LAN_MIDI2- 5 20 RJ45_MIDI2- L2501 @EMI@
LAN_MIDI2+ 6 TD2+ MX2+ 19 RJ45_MIDI2+ RJ45_MIDI2+ 4 B88069X9231T203_4P5X3P2-2
<23> LAN_MIDI2+ TD2- MX2- PR3+ 2 1
7 18 RJ45_MIDI2- 5 40mil
LAN_MIDI1- 8 TCT3 MCT3 17 RJ45_MIDI1- PR3-
<23> LAN_MIDI1- TD3+ MX3+
<23> LAN_MIDI1+ LAN_MIDI1+ 9 16 RJ45_MIDI1+ RJ45_MIDI1- 6 RJ45_GND 1 2 LANGND
TD3- MX3- PR2- C2560
10 15 RJ45_MIDI3+ 7 40mil 10P_0402_50V8J
LAN_MIDI0- 11 TCT4 MCT4 14 RJ45_MIDI0- PR4+
<23> LAN_MIDI0- TD4+ MX4+
<23> LAN_MIDI0+ LAN_MIDI0+ 12 13 RJ45_MIDI0+ RJ45_MIDI3- 8 LANGND

1
TD4- MX4- PR4- JP@

L30ESDL5V0C3-2_SOT23-3
D8 ESD@
JUMP_43X118
C C

75_0402_1%

75_0402_1%

75_0402_1%

75_0402_1%
JP2502 L2500

1
GST5009-E @EMI@
SP050006B10 B88069X9231T203_4P5X3P2-2

R2545

R2546

R2547

R2548
1 SANTA_130452-0B

2
fi
C2561

2
.1U_0402_16V7K

1
2
Place close to TCT pin

RJ45_GND

a
in
Card Reader Connector
B

h <23> SD_D3_R SD_D3_R 1

JREAD1
CD/DAT3
B
.c
+CARD_3V3 <23> SD_CMD_R SD_CMD_R 2
CMD
3
VSS1
Close to Card Reader CONN 4
VDD

4.7U_0603_6.3V6K
C2567

.1U_0402_16V7K
C2566
<23> SD_CLK_R SD_CLK_R 5
CLK
1 1
6
VSS2
SD_D0_R 7
w

2 2 <23> SD_D0_R DAT0

<23> SD_D1_R SD_D1_R 8 12
DAT1 G1
<23> SD_D2_R SD_D2_R 9 13
DAT2 G2
SD_CD# 10 14
<23> SD_CD# CD G3
SD_WP 11 15
w

<23> SD_WP WP G4
TAITW_PSDAT4-11GLBS1NN4H2
CONN@
w

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN RJ45/CR SD Connector
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 24 of 45
5 4 3 2 1
 A B C D E

HD Audio Codec
+5VS +VDDA
JP56
Reserved for ESD 40mil 1 2 40mil
+PVDD_HDA 1
SM01000EJ00 3000ma 220ohm@100mhz DCR 0.04 C554 JUMP_43X118 4.75V
40mil JP@
L33 2 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
+VDDA
HCB2012KF-221T30_0805 +AVDD1_HDA @ESD@ 2
(output = 300 mA)
1 1

1
10U_0603_6.3V6M
C608
C558 C559
R11
@ 0.1U_0402_16V4Z 20mil 1 RS@ 2
+VDDA

2
2 2

C567
10U_0603_6.3V6M
1 1

1
0_0603_5% GND
+1.5VS_DVDDIO C562 C561
1 GND GND 1
R17 Place near Pin41 Place near Pin46 @

2
1 RS@ 2 2 2
+1.5VS
0_0603_5% C565
1
C638
1 0.1U_0402_16V4Z Int. Speaker Conn.
GNDA 40mil JSPK1
10U_0603_6.3V6M Place near Pin26 SPKR+ R15 1 2 0_0603_5% SPK_R+ 1

m
2 2 SPKR- R10 1 2 0_0603_5% SPK_R- 2 1
0.1U_0402_16V4Z +3VS_DVDD SPKL+ R12 1 2 0_0603_5% SPK_L+ 3 2 5
R8 GND SPKL- R14 1 2 0_0603_5% SPK_L- 4 3 G1 6
1 RS@ 2 20mil +3VS_DVDD R7 4 G2
+3VS
1 1 1 +1.5VS_VDDA 0.1U_0402_16V4Z 1 RS@ 2 1 1 1 1 ACES_88266-04001
+1.5VS

3
EMI@ C366

EMI@ C367

EMI@ C368

EMI@ C369
0_0603_5% C564 C637 C582 @ CONN@ GND

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
1

1
C605
10U_0603_6.3V6M

MESC5V02BD03_SOT23-3
D2 @ESD@

MESC5V02BD03_SOT23-3
D4 @ESD@
C604 0_0603_5% SP02000K200
10U_0603_6.3V6M 0.1U_0402_16V4Z
2 2 2 2 2 2 2

o
2
0.1U_0402_16V4Z 2

GNDA
Place near Pin1 GND Place near Pin40

41

46

26

40
1

9
U36

1
DVDD-IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD

.c
GND GND GND
LINE1-L 22
LINE1-R 21 LINE1-L(PORT-C-L) 43 SPKL-
LINE1-R(PORT-C-R) SPK-OUT-L- 42 SPKL+
24 SPK-OUT-L+
23 LINE2-L(PORT-E-L) 45 SPKR+

RING2 17
LINE2-R(PORT-E-R) SPK-OUT-R+
SPK-OUT-R-
44 SPKR- Digital MIC +3VS @
SLEEVE 18 MIC2-L(PORT-F-L) /RING2 MIC2
Combo MIC MIC2-R(PORT-F-R) /SLEEVE

x
32 HP_LEFT +3VS @ 6 5 DMIC_DATA
2 40mil +MICBIAS 31 HPOUT-L(PORT-I-L) 33 HP_RIGHT MIC1 VDD DATA 2
+MICBIAS LINE1-VREFO-L HPOUT-R(PORT-I-R)
30 6 5 DMIC_DATA_S 2 4 DMIC_CLK
LINE1-VREFO-R 10 HDA_SYNC_AUDIO VDD DATA CS CLK
HDA_SYNC_AUDIO <7>

3
DMIC_DATA 2 SYNC 6 HDA_BITCLK_AUDIO 2 4 DMIC_CLK 2 2DMIC@ 1 1 3
GPIO0/DMIC-DATA BCLK HDA_BITCLK_AUDIO <7> CS CLK ENHANCE GND
DMIC_CLK 3 R130
GPIO1/DMIC-CLK

2
MESC5V02BD03_SOT23-3
fi
1 @EMI@ 2 1 2 C573 @EMI@ GND 1 3 0_0402_5% S MIC ST MP45DT02TR
ENHANCE GND

D5 @ESD@
R548 0_0402_5% 22P_0402_50V8J

2
EC_MUTE# 47 5 HDA_SDOUT_AUDIO S MIC ST MP45DT02TR
PDB ALC283-CG SDATA-OUT HDA_SDOUT_AUDIO <7> 1

0_0402_5%
R129 1DMIC@

0.1U_0402_16V4Z
C606

0_0402_5%
R131 1DMIC@
HDA_RST#_AUDIO 11 8 HDA_SDIN0_AUDIO 1 R547 2 HDA_SDIN0 <7>
RESETB SDATA-IN 33_0402_5% D2009
48 @ MESC5V02BD03_SOT23-3
SPDIF-OUT/GPIO2 +MIC2_VREFO 2
MONO_IN 12 @ESD@

1
PCBEEP 16
Close codec MONO-OUT
HP_PLUG# R545 2 1 39.2K_0402_1% SENSE_A 13 10U_0603_6.3V6M 2 1 C583 GND

1
14 SENSE A
10mil SENSE B 29
1 MIC2-VREFO
37 10U_0603_6.3V6M 2 1 C574 GNDA
C570 35 CBP 7 +MIC2_VREFO
2.2U_0402_6.3V6M CBN LDO3-CAP 39
2 LDO2-CAP 27 10U_0603_6.3V6M 2 1 C584 R526 Realtek add request HPOUT_L_2
LDO1-CAP GNDA
36 HPOUT_R_2

in
+3VS_DVDD CPVDD 1 R526 2 10mil

1
28 CODEC_VREF 100K_0402_5%
VREF

D9 @ESD@
MESC5V02BD03_SOT23-3
20 1 1 1 R540 R539
CPVREF

2.2U_0402_6.3V6M
C577

@
15 20K_0402_1% 1 2 R546 GNDA @ 2.2K_0402_5% 2.2K_0402_5%
JDREF

0.1U_0402_16V4Z
C576

10U_0603_6.3V6M
C578
10U_0603_6.3V6M 2 1 C585 19 34 CPVEE
GNDA MIC-CAP CPVEE
Close codec

2
2 2 2
1
4 RING2_L L76 1 2 ESD@ RING2
49 DVSS 25 C575 SLEEVE_L L77 1 2 ESD@ SLEEVE
Thermal PAD AVSS1 38 2.2U_0402_6.3V6M

2
AVSS2 2

D10 ESD@
MESC5V02BD03_SOT23-3
3 ALC283-CG_MQFN48_6X6 Place next pin27 2 2 3
GND GND C2142 C2140
ESD@ ESD@ +MIC2_VREFO
GND
GNDA GNDA 680P_0402_50V7K 680P_0402_50V7K
1 1
1
.c
R529 C607 @ESD@
47K_0402_5% 0.1U_0402_16V4Z

1
2 @ 1 BEEP#_R 1 2 MONO_IN GND GND
<22> EC_BEEP# +3VALW +3VS +3VLP 2
C555
2

R530 1 1U_0402_6.3V6K GND

47K_0402_5% @EMI@
100P_0402_50V8J
C556

4.7K_0402_5%
R531

2 1
<7> APU_SPKR Headphone Out
2

RING2
2

2 @ @ R550
1

R552 R551 R238 JHP1

w

100K_0402_5% 100K_0402_5% 100K_0402_5% 0_0603_5% 60.4_0603_1% RING2_L 3

HP_LEFT 1 2 HPOUT_L_1 R9 1 2 HPOUT_L_2 1
1

1
1

D
2 HP_PLUG# 5
GND G
Q90 S R237 6
2N7002K_SOT23-3 0_0603_5% 60.4_0603_1%
w

@ HP_RIGHT 1 2 HPOUT_R_1 R13 1 2 HPOUT_R_2 2

1

EC_MUTE# 2 R553 1 D
<22> EC_MUTE#
10K_0402_5% 2 SLEEVE_L 4
HDA_RST#_AUDIO 2 R554 1 G Q9 7
<7> HDA_RST#_AUDIO
10K_0402_5% S MESS138W-G_SOT323-3 LINE1-L 1 2 2 2
3

GNDA C557 4.7U_0603_6.3V6K C444 C445

1 2 LINE1-R 1 2 @EMI@ @EMI@ SINGA_2SJ3080-001111F
+MICBIAS C560 4.7U_0603_6.3V6K 330P_0402_50V7K 330P_0402_50V7K GNDA CONN@
w

@ C563 D6 1 1
GND
4 1U_0402_6.3V6K 2 2 R533 1 4
4.7K_0402_5%
GND 1
JP50 JP52 JP54
JUMP_43X39 JUMP_43X39 JUMP_43X39 3 2 R535 1
1 2 1 2 1 2 4.7K_0402_5%
JP@ 1 2 JP@ 1 2 JP@ 1 2
To solve the background noise while combo jack BAT54A-7-F_SOT23-3 GNDA
connecting to an active
JP51 JP53
JUMP_43X39 JUMP_43X39 GND GNDA
speaker and system entry into S3/S4/S5 without analog Security Classification Compal Secret Data Compal Electronics, Inc.
1 2 1 2 power 2014/03/27 2016/03/27 Title
JP@ 1 2 JP@ 1 2 Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio Codec ALC283
GND GNDA GND GNDA Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 25 of 45
A B C D E
 A B C D E

+3VALW +3VS_WLAN Mini-Express Card(WLAN/WiMAX) H=4mm

U77 @ W=60mils
1
5 VOUT
VIN
2 +3VS_WLAN
4 GND +1.5VS +3VS_WLAN +3VS
SS 1 @ 2 JP@
1 3 R1681 10K_0402_5% JMINI1 JP5
1 @ EN WLAN_ON <22> R1680 1 @ 2 0_0402_5% WLAN_WAKE#_R 1 2 1
<22> WLAN_WAKE# 3 WAKE# 3.3V 4
C173 AP2821KTR-G1_SOT23-5
1U_0402_6.3V6K 5 NC GND 6 JUMP_43X79
2 7 NC 1.5V 8 1 2
<7> WLAN_CLKREQ# 9 CLKREQ# NC 10 C164 4.7U_0603_6.3V6K
11 GND NC 12 1 2
<8> CLK_PCIE_WLAN# REFCLK- NC

m
13 14 C941 .1U_0402_16V7K
<8> CLK_PCIE_WLAN 15 REFCLK+ NC 16
17 GND NC 18
+3VS 19 NC GND 20
NC NC WL_OFF# <22>
21 22
GND PERST# APU_PCIE_RST# <12,23,7>
R622 1 @ 2 8.2K_0402_5% WLAN_CLKREQ# 23 24
<5> PCIE_ARX_DTX_N2 25 PERn0 +3.3Vaux 26
<5> PCIE_ARX_DTX_P2 PERp0 GND

o
27 28 0_0402_5%
29 GND +1.5V 30 APU_SCLK0_R R1496 1 @ 2
GND SMB_CLK APU_SCLK0 <10,11,7>
31 32 APU_SDATA0_R R1497 1 @ 2
<5> PCIE_ATX_C_DRX_N2 33 PETn0 SMB_DATA 34 APU_SDATA0 <10,11,7>
0_0402_5%
<5> PCIE_ATX_C_DRX_P2 35 PETp0 GND 36
+3VS_WLAN GND USB_D- USB20_N2 <8>
37 38

.c
39 NC USB_D+ 40 USB20_P2 <8>
41 NC GND 42
43 NC LED_WWAN# 44
45 NC LED_WLAN# 46
47 NC LED_WPAN# 48
2 NC +1.5V 2
R1498 1 RS@ 2 0_0402_5% 49 50
<22> EC_TX NC GND
R1499 1 RS@ 2 0_0402_5% 51 52
<22> EC_RX NC +3.3V
Use RX for BT off function

x
53 54
GND GND

1
ACES_50709-0524W-P01
R1501

fi
100K_0402_5% CONN@

2
For EC to detect
debug card insert.

a
in
H3 H4 H5 H6 H9 H10 H11 H17 H21
H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_6P5 H_3P0
3 3
1

@ @ @ @ @ @ @ @ @

H13 H14 H15 H16 H20

H_4P0 H_4P0 H_4P0 H_4P0 H_4P0 h
.c
1

FD1 FD2

@ @ @ @ @ @ @

1
H27 FIDUCIAL_C40M80 FIDUCIAL_C40M80
H_3P7
w

FD3 FD4
1

@ @

1
4 4
FIDUCIAL_C40M80 FIDUCIAL_C40M80
@
w

Security Classification Compal Secret Data Compal Electronics, Inc.

H23 H25 2014/03/27 2016/03/27 Title
H_3P5X3P0N H_3P0N
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MINI CARD (WLAN)/Screw
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
w

@ @ B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Z5WAE LA-B231P
1

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 26 of 45
A B C D E
 A B C D E F G H

SATA HDD Conn. SATA ODD Conn.

JHDD1 JODD1

1 1
SATA_FTX_DRX_P0 C137 1 2 0.01U_0402_16V7K SATA_FTX_C_DRX_P0 2 GND C619 1 2 0.01U_0402_16V7K SATA_FTX_C_DRX_P1 2 GND
<8> SATA_FTX_DRX_P0 A+ <8> SATA_FTX_DRX_P1 A+
<8> SATA_FTX_DRX_N0 SATA_FTX_DRX_N0 C138 1 2 0.01U_0402_16V7K SATA_FTX_C_DRX_N0 3
<8> SATA_FTX_DRX_N1 C616 1 2 0.01U_0402_16V7K SATA_FTX_C_DRX_N1 3
4 A- 4 A-
SATA_FRX_DTX_N0 C596 1 2 0.01U_0402_16V7K SATA_FRX_C_DTX_N0 5 GND C614 1 2 0.01U_0402_16V7K SATA_FRX_C_DTX_N1 5 GND
<8> SATA_FRX_DTX_N0 SATA_FRX_DTX_P0 C597 1 2 0.01U_0402_16V7K SATA_FRX_C_DTX_P0 6 B- <8> SATA_FRX_DTX_N1 C613 1 2 0.01U_0402_16V7K SATA_FRX_C_DTX_P1 6 B-
1 <8> SATA_FRX_DTX_P0 7 B+ <8> SATA_FRX_DTX_P1 7 B+ 1
GND GND

8 8
9 V33 1 RS@ 2 +5VS_ODD 9 DP
V33 +5VS +5V
10 10
<7> DEVSLP0 V33 +5V

m
11 R556 11
GND T24 MD
12 0_0805_5% 12 14
13 GND 13 GND GND 15
GND 1 1 GND GND
1 RS@ 2 +5VS_HDD 14
+5VS V5
15 C641 C642
R555 16 V5 10U_0603_6.3V6M .1U_0402_16V7K SANTA_201902-1
0_0805_5% 17 V5 2 2 CONN@
GND

o
18
19 Reserved 23
1 1 1 GND GND
@ 20 24
C602 C599 C598 21 V12 GND 25
10U_0603_6.3V6M .1U_0402_16V7K 1000P_0402_50V7K 22 V12 GND 26
2 2 2 V12 GND

.c
CCM_C127043HR022M27FZR
CONN@

2
TPM FAN Conn 2

x
+3VALW +3VALW_TPM +3VS +3VS_TPM
R2600 R2601 close to EC +5VS
1 2 1 2
10U_0603_6.3V6M

0.1U_0402_16V4Z

10U_0603_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z
0_0603_5% 0_0603_5% 1 2
C2600 TPM@

C2601 TPM@

C2602 TPM@

C2603 TPM@

C2604 TPM@

C2605 TPM@
TPM@ 1 1 TPM@ 1 1 1 1 LPC_AD3_R R1684 1 TPM@ 2 0_0402_5% LPC_AD3 C632
LPC_AD3 <22,8>

fi
LPC_AD2_R R1685 1 TPM@ 2 0_0402_5% LPC_AD2 4.7U_0603_6.3V6K
LPC_AD2 <22,8>
LPC_FRAME#_R R1686 1 TPM@ 2 0_0402_5% LPC_FRAME# U31
1 2 LPC_FRAME# <22,7,8> +VCC_FAN 1 8
LPC_AD1_R R1687 TPM@ 0_0402_5% LPC_AD1
LPC_AD1 <22,8>
2 2 2 2 2 2 LPC_AD0_R R1688 1 TPM@ 2 0_0402_5% LPC_AD0 2 EN GND 7
1 2 LPC_AD0 <22,8> 3 VIN GND 6
SERIRQ_R R1689 TPM@ 0_0402_5% SERIRQ SERIRQ <22,8>
4 VOUT GND 5
<22> EN_DFAN VSET GND

a
near pin5 near pin10, 19, 24 1 NCT3942S_SO8
@
BADD SELECTION C626
.1U_0402_16V7K
2
0 EEh - EFh U2600 TPM@

in
5
* 1 7Eh - 7Fh 1
GPIO0/XOR_OUT
VSB
VDD
10
+3VALW_TPM
+3VS_TPM
3 GPIO3/BADD with Internal PH (default) 2 19 3
6 GPIO1 VDD 24
0_0402_5% 1 2 R2602 TPM_BADD
@ 9 GPIO2/GPX VDD +VCC_FAN
CLKRUN# 15 GPIO3/BADD 8
<8> CLKRUN# GPIO4/CLKRUN# TEST 1 2
AMD CLKRUN# no need PH (DG1.1) LPC_AD0_R 26 C627
LAD0/MISO
LPC_AD1_R
LPC_AD2_R
LPC_AD3_R
23
20
17
h
LAD1/MOSI
LAD2/SPI_IRQ#
LAD3
NC
NC
3
12
+3VS 4.7U_0603_6.3V6K

C631
1 2
@

1
13 1000P_0402_50V7K
NC 14 R516
R447 1 @ 2 0_0402_5% 28 NC 10K_0402_5%
.c
LPCPD# had internal PH <8> LPCPD#
LPC_CLK1 21 LPCPD#
<7,8> LPC_CLK1 LCLK/SCLK 40mil JFAN1 0118 modify
LPC_FRAME#_R 22 1

2
LPC_RST# 16 LRFAME#/SCS# 4 2 1 4
<22,7> LPC_RST# LRSET#/SPI_RST# GND <22> FAN_SPEED 2 GND
SERIRQ no need PH SERIRQ_R 27 11 1 3 5
7 SERIRQ GND 18 C630 3 GND
PP GND 25 1000P_0402_50V7K
GND @EMI@ ACES_88231-03041
2 CONN@
w

NPCT650AA0WX_TSSOP28 SP020020710
+3VS_TPM
1 @ 2 CLKRUN#
SA00007IO00
10K_0402_5%
4 R2604 4

CLKRUN# PH request by TPM chip DG 1/22

w

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title
LPC_CLK1 R2603 1 2 33_0402_5% C2606 1 2 22P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD/FAN/TPM
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
@EMI@ @EMI@ Document Number Rev
w

B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 27 of 45
A B C D E F G H
 5 4 3 2 1

+USB3_VCCA
+5VALW +USB3_VCCA

1 @EMI@ 2 U35 W=80mils

R566 0_0402_5% 2 6 1
3 IN OUT 7
1 IN OUT 1
L51 EMI@ @ USB_EN# 4 8 C736 + EMI@
1 2 USB20_N8_R C704 1 EN/ENB OUT 5 C735
<8> USB20_N8 1 2 GND OCB USB_OC0# <7>
.1U_0402_16V7K 150U_6.3V_M_D2 470P_0402_50V7K
D 2 SY6288D10CAC_MSOP8 2 2 D
4 3 USB20_P8_R 2A/Active Low
<8> USB20_P8 4 3
DLW21HN900HQ2L_4P

1 2

m
R562 @EMI@ 0_0402_5% W=80mils
+USB3_VCCA

1 @EMI@ 2 1 2
USB3.0 Port0
R567 0_0402_5%
C943 ESD@

o
.1U_0402_16V7K JUSB1
L50 EMI@ 1
1 2 USB3_FRX_L_DTX_P0 USB20_N8_R 2 VBUS
<8> USB3_FRX_DTX_P0 1 2 3 D-
USB20_P8_R
4 D+
4 3 USB3_FRX_L_DTX_N0 USB3_FRX_L_DTX_N0 5 GND

.c
<8> USB3_FRX_DTX_N0 4 3 6 StdA-SSRX- 10
D27 USB3_FRX_L_DTX_P0
DLW21HN900HQ2L_4P @ESD@ 7 StdA-SSRX+ GND 11
USB3_FRX_L_DTX_N0 9 10 1 USB3_FRX_L_DTX_N0 USB3_FTX_L_DRX_N0 8 GND-DRAIN GND 12
1 StdA-SSTX- GND
1 2 USB3_FTX_L_DRX_P0 9 13
R563 @EMI@ 0_0402_5% USB3_FRX_L_DTX_P0 8 2 USB3_FRX_L_DTX_P0 StdA-SSTX+ GND
C 9 2 C
ACON_TARAC-9V1391
USB3_FTX_L_DRX_N0 7 7 4 4 USB3_FTX_L_DRX_N0 CONN@
1 @EMI@ 2

x
R568 0_0402_5% USB3_FTX_L_DRX_P0 6 6 5 5 USB3_FTX_L_DRX_P0

3 3
L49 EMI@
1 2 USB3_FTX_C_DRX_P0 1 2 USB3_FTX_L_DRX_P0 8
<8> USB3_FTX_DRX_P0 1 2

fi
C859 .1U_0402_16V7K
YSCLAMP0524P_SLP2510P8-10-9
1 2 USB3_FTX_C_DRX_N0 4 3 USB3_FTX_L_DRX_N0
<8> USB3_FTX_DRX_N0 4 3
C858 .1U_0402_16V7K
DLW21HN900HQ2L_4P

1 2

a
R564 @EMI@ 0_0402_5%

1 @EMI@ 2
USB/B(USB Port 0, Port1)
R569 0_0402_5%

in
+5VALW
DLW21HN900HQ2L_4P JUSB2
B 4 3 USB20_N0_R 1 B
<8> USB20_N0 4 3 1
2
3 2
1 2 USB20_P0_R 4 3
<8> USB20_P0 1 2 5 4
L52 EMI@ <22> USB_EN# 5
6
6

h R565
1

1 @EMI@ 2
R570
2
@EMI@ 0_0402_5%

0_0402_5%
USB20_N0_R
USB20_P0_R

USB20_N1_R
USB20_P1_R
7
8
9
10
11
12
7
8
9
10
11
.c
13 12
DLW21HN900HQ2L_4P 14 13
4 3 USB20_N1_R 14
<8> USB20_N1 4 3 ACES_88514-01201-071
CONN@
1 2 USB20_P1_R SP01001BF00
<8> USB20_P1 1 2
L53 EMI@
w

1 2
R571 @EMI@ 0_0402_5%

A A
w

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB2.0 / USB3.0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
w

B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 28 of 45
5 4 3 2 1
 JKB1 +TP_VCC 1 @ 2 +TPUSB_VCC 2 @ 1
KB Conn. To TP/B Conn. R132 0_0402_5%
+3VS
R151 0_0603_5%
+3VALW +VDDD +VBUS
KSO0 1 C663 @ 1 @ 2 2 TPUSB@1
1 +3VALW +3VS
KSO1 2 0.1U_0402_16V4Z R133 0_0402_5% R152 0_0603_5%
KSO2 3 2 1 2 +TPUSB_VCC
3

0.1U_0402_16V4Z
C665 TPUSB@

4.7U_0603_6.3V6K
C828 TPUSB@

0.1U_0402_16V4Z
C666 TPUSB@

4.7U_0603_6.3V6K
C831 TPUSB@
KSO3 4 JTP1 R146 U69 TPUSB@ 2 2 2 2
KSO4 5 4 8 +TP_VCC 0_0402_5% 1 24 +VDDD 2 RS@ 1
KSO5 6 5 10 8 7 TP_CLK +VDDD_M_M 1 @ 2 +VDDD_M 2 SCB_0/GPIO_6 VDDD 23 R137 0_0402_5%
7 6 9 G2 7 6 TP_CLK <22> 3 SCB_5/GPIO_7 SCB_4/GPIO_5 22
KSO6 TP_DATA TP_I2C_DAT
7 G1 6 TP_DATA <22> VSSD SCB_3/GPIO_4 1 1 1 1

100P_0402_50V8J

100P_0402_50V8J
@EMI@ C553

@EMI@ C551
KSO7 8 5 1 1 TP_I2C_INT#_D 4 21 TP_I2C_CLK
KSO8 9 8 5 4 I2C_DAT_R 5 GPIO_8 SCB_2/GPIO_3 20 TPUSB_X2
KSO9 10 9 4 3 I2C_CLK_R @ C668 1 2 .1U_0402_16V7K 6 GPIO_9 SCB_1/GPIO_2 19 TPUSB_X1
KSO10 11 10 3 2 TP_I2C_INT# 2 1 +VDDD_M_M 7 GPIO_10 GPIO_1 18 1 @ 2
12 11 2 1 TP_I2C_INT# <22> 2 2 8 GPIO_11 GPIO_0 17 +5VS
KSO11 TP_SENOFF# @C836
@ C836 4.7U_0603_6.3V6K R148
12 1 TP_SENOFF# <22> SUSPEND VSSA
KSO12 13 9 16 0_0402_5%
KSO13 14 13 E-T_6916K-Q08N-00L 10 WAKEUP VSSD 15 +VBUS 2 1
14 1 <8> USB20_P6 USBDP VBUS

0.1U_0402_16V4Z
C667 @
KSO14 15 CONN@ 11 14 R138 @
16 15 <8> USB20_N6 12 USBDM nXRES 13
KSO15 0_0603_5%
16 VCCD VSSD

m
KSO16 17 +3VALW +TP_VCC +VDDD_M 1 @ 2 25 T26 2 1
17 2 thermal pad +TPUSB_VCC
KSO17 18 U78 R139 R149 TPUSB@
KSI0 19 18 1 0_0402_5% CY7C65211-24LTXI_QFN24_4X4 0_0603_5%
19 VOUT 1
KSI1 20 5 C523 @ +TPUSB_VCC 1 @ 2
KSI2 21 20 VIN 4.7U_0603_6.3V6K R147
21 1
KSI3 22 2 0_0402_5%
KSI4 23 22 4 GND 2 +3VS C43 TPUSB@
23 SS

o
KSI5 24 1 1U_0402_6.3V6K
24

2
KSI6 25 27 @ C1280 3 2
25 G1 EN TP_3V_EN <22> +3VS

G
KSI7 26 28 1U_0402_6.3V6K
26 G2 AP2821KTR-G1_SOT23-5
2 TP_I2C_INT#_D 3 1 TP_I2C_INT#

2
E-T_6905-E26N-01R TP I2C to bridge & EC

.c
CONN@ +TP_VCC TPUSB@ Q87 2N7002K_SOT23-3

G
SP01000IJ00 RP19 R126 1 @ 2 0_0402_5% TP_I2C_CLK 1 6 I2C_CLK
1 8 +3VALW <22> TP_I2C_CLK

D
TP_CLK Q2505B TPUSB@
KSI[0..7] TP_DATA 2 7 +TP_VCC DMN66D0LDW-7_SOT363-6
KSI[0..7] <22>

5
APU_SCLK1 3 6 Q2505A TPUSB@

2
KSO[0..17] APU_SDATA1 4 5 DMN66D0LDW-7_SOT363-6

G
KSO[0..17] <22> 4 3
TP_I2C_DAT I2C_DAT

G
<22> TP_I2C_DAT

D
4.7K_0804_8P4R_5%

x
1 3 TP_I2C_INT# R122 1 @ 2 0_0402_5%
+TP_VCC <7> TP_I2C_INT#_APU
R123 1 @ 2 0_0402_5%

S
RP20 @ Q92 2N7002K_SOT23-3
I2C_DAT 1 8 R150 1 @ 2 0_0402_5%
I2C_CLK 2 7 TP SMBus to CPU
KB BackLight Conn. Reserve

fi
TP_I2C_INT# 3 6
4 5 TPUSB_X1 APU_SCLK1 R135 1 TPSM@ 2 0_0402_5% I2C_CLK
+5VS <7> APU_SCLK1
Y9 @ APU_SDATA1 R136 1 TPSM@ 2 0_0402_5% I2C_DAT
4 1 <7> APU_SDATA1
JBL1 2.2K_0804_8P4R_5%
S

3 1 +5VS_BL 4 6
+5VALW 3 4 G2 5 +3VS USB20_P6 R140 1 @ 2 0_0402_5% USB20_P6_R
BL@ 2 3 G1 RP24 @ USB20_N6 R141 1 @ 2 0_0402_5% USB20_N6_R
2

a
R451 Q44 1 TP_I2C_CLK 1 8 +3VALW 1 R939 2 TPUSB_X2 3 2
G
2

100K_0402_5% DMG2301U-7_SOT23-3 1 TP_I2C_DAT 2 7 1M_0402_5% USB20_P6_R R143 1 @ 2 0_0402_5% I2C_DAT_R

33P_0402_50V8J
C62

33P_0402_50V8J
C73
1 BL@ 2 KBL_EN_R ACES_50504-0040N-001 TP_I2C_INT#_D 3 6 12MHZ_18PF_7V12000001 USB20_N6_R R142 1 @ 2 0_0402_5% I2C_CLK_R

1
10K_0402_5%
R452
CONN@ TP_I2C_INT#_APU4 5 Part Number = SJ10000C210
1 RS@ 2 SP01000Z300 @ @ PCB Footprint = Y_CRG3201212_4P I2C_DAT R144 1 TPUSB@2 0_0402_5% I2C_DAT_R
R592 2.2K_0804_8P4R_5% @ I2C_CLK R145 1 TPUSB@2 0_0402_5% I2C_CLK_R

in 2

2
1

0_0402_5% 1

1
D
<22> KBL_EN# 2 C524
G 0.1U_0603_25V7K
Q85 @ S 2
@
2N7002K_SOT23-3
3

PWR/B
JPWR1
1
2
1
2
3
+3VALW
+3VLP
h
<22> BATT_BLUE_LED# BATT_BLUE_LED# 1
LED6

B
2 1
R699
2
+3VALW

200_0402_5%
.c
3 LID_SW# <22>
4 PWR_LED# <22> BATT_AMB_LED# BATT_AMB_LED# 3 4 1 2
7 4 5 ON/OFFBTN# A R698 390_0402_5%
8 G1 5 6
G2 6 LTST-C295TBKF-CA_AMBER-BLUE
ACES_51524-0060N-001 LED7
CONN@
PWR_LED# 1 2 1 2
+3VLP <22> PWR_LED# B R700 200_0402_5%
ON/OFF BTN
w
2

<22> PWR_SUSP_LED# PWR_SUSP_LED# 3 4 1 2

R534 A R701 390_0402_5%
100K_0402_5%
SW3 LTST-C295TBKF-CA_AMBER-BLUE
TJE-532QR5_6P
1

3 1 ON/OFFBTN#
w

ON/OFFBTN# <22> Security Classification Compal Secret Data Compal Electronics, Inc.
4 2 2014/03/27 2016/03/27 Title
Issued Date Deciphered Date
P21-PBTN/LIDSW/LED/KB/TP
6
5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Z5WAE LA-B231P
w

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 29 of 45
 A B C D E

VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm

+3VS
U2 JP7 JP@
1 14 +3VS_LS
+3VALW VIN1 VOUT1
1 2 2 13 2
C12 @ VIN1 VOUT1 JUMP_43X118 @
1 RS@ 2 3VS_ON 1U_0402_6.3V6K 3 12 1 2 C13
+5VALW TO +5VS <22,36> SUSP#
R1667 4
ON1 CT1
11
C10
560P_0402_50V7K 1
.1U_0402_16V7K
1 +5VALW VBIAS GND 1
+3VALW TO +3VS 0_0402_5%
1 RS@ 2 5VS_ON 5
ON2 CT2
10
C9
1 2
+5VS

Load switch R1668

0_0402_5% 1 1
+5VALW
1 2
6
7 VIN2
VIN2
VOUT2
VOUT2
9
8
330P_0402_50V7K JP8 JP@
+5VS_LS
@ @ C11 @ 2

m
C37 C38 1U_0402_6.3V6K 15 JUMP_43X118 @
.1U_0402_16V7K .1U_0402_16V7K GPAD C14
2 2 TPS22966DPUR_SON14_2X3 .1U_0402_16V7K
1

o
VIN 1.8V and 1.5V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm
+1.8VS

.c
U3 JP9 JP@
+1.8VALW 1 14 +1.8VS_LS
1 2 2 VIN1 VOUT1 13
VIN1 VOUT1 2
C24 @ JUMP_43X118 @
SUSP# 1 RS@ 2 1.8VS_ON 1U_0402_6.3V6K 3 12 1 2 C26
2
+1.8VALW TO +1.8VS R1669 4
ON1 CT1
11
C21
330P_0402_50V7K 1
.1U_0402_16V7K
2

+5VALW VBIAS GND

+1.5V TO +1.5VS 0_0402_5%

x
1 RS@ 2 1.5VS_ON 5 10 1 2
ON2 CT2 C15 +1.5VS

Load switch R1670

0_0402_5% 1 1
+1.5V
1 2
6
7 VIN2
VIN2
VOUT2
VOUT2
9
8
330P_0402_50V7K
+1.5VS_LS
JP10JP@

@ @ C22 @ 2

fi
C42 C41 1U_0402_6.3V6K 15 JUMP_43X79 @
.1U_0402_16V7K .1U_0402_16V7K GPAD C25
2 2 TPS22966DPUR_SON14_2X3 .1U_0402_16V7K
1

a
+0.95VALW U4 +0.95VS
AO4304L_SO8
8 1
1 7 2
+0.95VS

4.7U_0603_6.3V6K
C939

1U_0402_6.3V6K
C46
C940 6 3

in
1 1
4.7U_0603_6.3V6K 5
2
3 3

1
2 @2
R1671 @
470_0603_5%
+5VALW

1 2
+0.95VALW to +0.95VS
h 1
R1674
2

4.7K_0402_5%

2
0.95VS_GATE

1 D
1

2
C16
.1U_0402_16V7K 0.95VS_PWR_EN# 2
G
D Q83 @
2N7002K_SOT23-3
.c
<22> 0.95VS_PWR_EN# S
G

3
S Q84
2N7002K_SOT23-3
3
w

4 4
w

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P22-DC INTERFACE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
w

B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 30 of 45
A B C D E
 5 4 3 2 1

0.2
1. Add R693 for UMA/DIS select
2. Change R756,R765,R769,R779,R781,R782,R783 and R794 to Rshort for EMI request
3. Change BID to 1 for DVT
4. Change LAN_WAKE# PU to +3V_LAN
5. Add L76,L77,C2142 and C2140 for ESD request
6. Change R238 and R237 to 59ohm
D D
7. Add L52,L53,R565,R569,R570 and R571 for EMI request.
8. Add R140,R141,R142,R143,R144 and R145 for reserve USB TP
9. Pop Q89, unpop R1690

m
10. Change D10 to SCA00001B00
11. Change L11 to SM01000EJ00
12. Add U39,R833,C185,R1578 for VGA power sequence issue
13. Remove APU_ALERT#_R
14. Add C668 and C836 for vendor request

o
0.3
1. Change JTP1

.c
2. Add U78 for TP +3V power plane
3. Change C849, C849 to 10p
4. Change C736 to 150u D2 type.
5. Change R699, R700 to 330ohm; R698, R701 to 560ohm
6. Change U69 +3VALW to +3VS

x
C
7. Add C366, C367, C368, C369 for EMI request C

8. Add on board TPM

9. Add R619

fi
a
in
B

h B
.c
w
w
w

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW-PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Z5WAE LA-B231P
Date: Thursday, March 27, 2014 Sheet 31 of 45
5 4 3 2 1
 A B C D

1 VIN 1

@ PJP101 EMI@ PL101

ACES_50305-00441-001_4P HCB2012KF-121T50_0805
DC_IN_S1 1 2
1
2
3

m
4
GND

1
GND EMI@ PC102 EMI@ PC103
100P_0603_50V8 1000P_0603_50V7K

o
.c
x
2 2

fi
+RTC_APU Vo=1.5V +RTCVCC
PD101

a
BAS40-04_SOT23-3
3
Vout 1 3
2 Vin
GND 1
1 1 +RTCBATT

in
PU101
PC111 PC110 2
0.1U_0603_25V7K AP2138N-1.5TRG1_SOT23-3 680P_0603_50V8J
2 2
+CHGRTC

@PR111
@ PR111
0_0402_5%
h 3
.c
1 2
+3VLP +CHGRTC
w

- PBJ101 @ + PR112
560_0603_5%
PR113
560_0603_5%
2 1 1 2 1 2
+RTCBATT
w

ML1220T13RE

4 4
w

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DCIN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 32 of 45
A B C D
 A B C D

+3VLP

@ PJP201
SUYIN_200275GR008G13GZR
10
GND 9
GND 8

1
8 7 @ PC202
7 6

1
0.1U_0603_25V7K

2
6 5 100_0402_1% PR209
1
5 4 EC_SMDA 1 2 @ PR204 @ PR205
1

4 3 EC_SMB_DA1 <22,34> 10K_0402_1% 10K_0402_1%

3 2 100_0402_1% PR208

2
2 1 EC_SMCK 1 2
1 EC_SMB_CK1 <22,34>

1
@ PU201
@ PR206 1 8
VCC TMSNS1

m
2 1 100K_0402_1%
+3VLP
PR201 2 7 2 1
6.49K_0402_1% GND RHYST1

1
TH 1 2 MAINPWON 3 6 @ PR207
PR210
BATT_TEMP<22> <22,35> MAINPWON OT1 TMSNS2 47K_0402_1% @ PH201
1K_0402_1% 4 5 100K_0402_1%_B25/50 4250K
OT2 RHYST2
PR211 G718TM1U_SOT23-8

2
BI 1 2

o
0_0402_5%

EMI@ PL201
HCB2012KF-121T50_0805
BATT_S1 1 2 BATT+ <45,47>

.c
EMI@ PL202
1 HCB2012KF-121T50_0805
1 2
EMI@ PC201
1000P_0402_50V7K
2

2014/01/02 update
For KB9012 For KB9022 For KB9022
Active Recovery

x
2 2

OTP OTP sense 20mΩ

---Battery_pin define---
PIN1 GND
---Battery Con_pin define---
PIN8 GND 92℃ 1.0V

56℃
PIN2 GND PIN7 GND

fi
PIN3 SMD PIN6 SMD
2.0V 65W 70W,0.73V 55.9W,0.59V
PIN4 SMC PIN5 SMC
PIN5 TS PIN4 TS
PIN6 B/I PIN3 B/I
PR216 16.9K ohm

a
PIN7 Batt+ PIN2 Batt+
PIN8 Batt+ PIN1 Batt+
2013/10/22 Modify
PH201,PH202 change to common part.

in
PH201 under CPU botten side :
2013/12/16 Modify
CPU thermal protection at 92 degree C ( shutdown )
2013/10/02 Delete PR223.(remove HW hysteresis)
Recovery at 56 degree C +EC_VCCA
Add for ENE9022 Battery Voltage drop detection.
Connect to ENE9022 pin64 AD1.
3

Battery is 3-cell design.

h ADP_I <22,34> 3

1
B+=9V PR216
16.9K_0402_1% PR202
.c
10K_0402_1%
B+

2
9022@
1

PR230
80.6K_0402_1%
<22> 9012_PH1 9012_VCIN <22>
w

@ PR229
2

1
0_0402_5%
1 2 2013/10/25 Modify PH202
VCIN1_BATT_DROP<22>
PR227(9012@) change to 26.1K ohm. 100K_0402_1%_B25/50 4250K
B value:4250K±1%
2014/02/07 Modify

2
1

Delete @PR227.(remove HW hysteresis)

2

@9022@ PC203 9022@ PR228

1
0.1U_0402_25V6 10K_0402_1%
For 65W adapter==>action 70W , Recovery 55.9W
1

1_0402_1%
PR226
PR203
2

0_0402_5%
PR225
10K_0402_1%

2
@
@
w

2
2
4 4

ECAGND
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CONN / OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 33 of 45
A B C D
 A B C D

Protection for reverse input 2013/10/16 Modify

2013/10/14 PQ305,PQ306 change to AON7408L.
Vgs = 20V PR303 10m ohm chang -->20m ohm 2013/10/22 Modify

1
PQ201 D
Vds = 60V
2
G Id = 250mA SD00000S120 B+
PL302 change to common part.
2013/11/29 Modify
S 2N7002KW _SOT323-3
PL301 change to common part.

3
PR302
PR301 Rds(on) = 15.8mohm max
1 2 1 2
Vgs = 20V
Rds(on) = 15.8mohm max
1M_0402_5% 3M_0402_5% Vds = 30V
1
Vgs = 20V 1

Need check the SOA for inrush ID = 10.5A (Ta=70C)

Vds = 30V
VIN
P1 P2
ID = 10.5A (Ta=70C)
1 1 PR303 EMI@ PL301 CHG_B+
2 2 0.02_1206_1% 1UH_2.8A_30%_4X4X2_F 1

m
5 3 3 5 1 4 1 2 2
5 3

2200P_0402_25V7K
10U_0805_25V6K

10U_0805_25V6K
2 3
2200P_0402_50V7K

0.1U_0402_25V6
0.1U_0402_25V6
PQ303
4

@EMI@ PC306
1

1
PC303

PC304

EMI@ PC305
PQ302 0_0402_5% AON7506_DFN33-8-5

0.01U_0402_50V7K
PC301

@ PR304

4
1

1
AON6414AL_DFN8-5 VIN PQ304

PC302

PC307
AON7506_DFN33-8-5

2
2

o
VF = 0.5V
2

2
3

2
PD301
BQ24725A_ACDRV_1 BAS40CW _SOT323-3

0.1U_0402_25V6
BQ24725A_BATDRV 1 2BQ24725A_BATDRV_1

0.1U_0402_25V6
Rds(on) = 30mohm max

1
1
PC308

.c
PR305

PC310
Vgs = 20V

1 1
1 2

10_1206_1%
PC311 4.12K_0603_1%
0.047U_0402_25V7K Vds = 30V

PR306
2
PC309 1 2
0.1U_0402_25V6
ID = 7A (Ta=70C)
VF = 0.37V

5
2.2_0603_5%

AON7408L_DFN8-5
PR307
PD302

BQ24725A_VCC2
RB751V-40_SOD323-2

PQ305
PR308 Power loss: 0.32W for 3.5A

BQ24725A_ACP
0_0402_5% 7X7X3

BQ24725A_REGN
CSR rating: 1W

BQ24725A_BST2

2
DH_CHG 1 2 4

x
Isat: 3.5A

BQ24725A_LX
VSRP-VSRN spec < 81.28mV
4.12K_0603_1%

4.12K_0603_1%

2 2
1

PC312 BATT+
PR309

PR310

DH_CHG
1 2 PL302
10UH_3.5A_20%_7X7X3_M PR311

3
2
1
1U_0603_25V6K 1 2 0.01_1206_1%

BQ24725A_ACN

fi
BQ24725A_LX 1 2 CHG 1 4
2

PC313
1U_0603_25V6K 2 3

20

19

18

17

16

5
PU301

AON7408L_DFN8-5

CSON1
CSOP1
1

680P_0402_50V7K 4.7_1206_5%
VCC

PHASE

HIDRV

BTST

REGN

10U_0805_25V6K

10U_0805_25V6K
21

@EMI@ PC319 @EMI@ PR312

PAD

0.1U_0402_25V6

0.1U_0402_25V6
PQ306

PC314

PC315
1

1
1 15 DL_CHG
ACN LODRV

a
4

PC316

PC317
2

2
2 14
ACP GND PR313

2
1
BQ24725ARGRR_QFN20_3P5X3P5 10_0603_1%

3
2
1
BQ24725A_CMSRC 3 13 SRP1 2 CSOP1
CMSRC SRP

1
PR314

in

2
6.8_0603_1%
BQ24725A_ACDRV 4 12 SRN1 2 CSON1

2
ACDRV SRN PC318
0.1U_0603_16V7K
1 2 5 11 BQ24725A_BATDRV **Design Notes**
+3VLP ACOK BATDRV
PR315 100K_0402_1%
ACDET
#For 65 /90W system, 3S1P/3S2P battery

IOUT

SDA

SCL

ILIM
Maximum Charging current 3.5A
<22> ACIN Maximum Battery discharge power 55W.

h #Register Setting
6

10
+3VALW
3
1. 0X12 bit8 set 0 (default 1) to disable IFAULT HI if add ISN choke 3
BQ24725A_ACDET

BQ24725A_ILIM 1 2 #Circuit Design

BQ24725A_IOUT

PR316
1. ACOK,ILIM pull high voltage need base on 3/5V enable control

100K_0402_1%
316K_0402_1%

0.01U_0402_25V7K
1
2. Use 10X10 choke and 3X3 H/L Side MOSFET

PC320
PR317
.c
1
PR318 Charge current 3.5A
422K_0402_1%
VIN
1 2 Power loss : 1.82W

2
Power density : 0.81 (15X15)
2

3. If use 4S per cell 4.35V battery, need additional circuit

for ACDET(PR218/PR220/PR222 change to 0.1%, parallel resistors
with PR222 for ACDET setting)
4. PC223 0.22U can't be changed. (Wrong adapter concern)
w

5. For the design, need double confirm PQ202,PQ203,PQ204 rating

#Protect function
0.22U_0402_16V7K

66.5K_0402_1%

EC_SMB_CK1 <22,33> 1. ACOVP : ACDET voltage > 3.14V

100P_0402_50V8J
1

2. Charger timeout : No communication within 175s(default)

PC321

1
PC322
PR319

3. ACOC : 3.33 X Input current DAC setting(default)

EC_SMB_DA1 <22,33> 4. CHGOCP : 3/4.5/6A based on current current setting
2
w
2

@ PR320 5. BATOVP : 103-106%

2

0_0402_5% 6. BATLOWV : 2.5V

1 2
ADP_I <22,33> 7. TSHUT : 155C
1

8. IFAULT HI : 750mV (default)

@ PC323
9. IFAULT LOW : 150mV (default)
2014/01/24 update 100P_0402_50V8J
2
w

Close EC chip
4 4

Vin Dectector
Min. Typ Max.
L-->H 17.16V 17.63V 18.12V
H-->L 16.76V 17.22V 17.70V
Security Classification Compal Secret Data Compal Electronics, Inc.
VILIM = 20*ILIM*Rsr Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title
ILIM = 3.3*100/(100+316)/20/0.01
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
= 3.966 A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 34 of 45
A B C D
 A B C D E

Module model information

SY8208B_V2.mdd
SY8208C_V2.mdd

1 1

EN1 and EN2 dont't floating

PR402

m
499K_0402_1%
ENLDO_3V5V 1 2
B+

1
150K_0402_1%
PU401 PC402 PR403
B+

PR404
EMI@ PL401 7 1 0.01U_0402_25V7K 1K_0402_5%
EN2 EN1 3V_EN <22>
HCB2012KF-121T50_0805 1 2 1 2

2200P_0402_50V7K
1 2 3V_VIN 8 3 3V_FB
IN FB PR401 PC403

2
10U_0805_25V6K

10U_0805_25V6K
@EMI@ PC401

EMI@ PC404
0.1U_0402_25V6
6 1
BST_3V 2 1 2

o
BS
1

1
PC406
2.2_0603_5%

PC405
0.1U_0603_25V7K
PL402
2

2
10 LX_3V 1 2
@ LX +3VALWP
9 4 1.5UH_PCMB053T-1R5MS_6A_20%
GND OUT

.c
@EMI@

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
PR405
1

1
680P_0603_50V7K 4.7_1206_5%
2 5
+3VALWP PG LDO +3VLP

PC407

PC408

PC409

PC410
22u Capacitor change to 0603 size.

1
SY8208BQNC_QFN10_3X3

2
PC411 2013/10/16 modify.

1 3V_SN
4.7U_0603_6.3V6M

2
1

Check pull up resistor of SPOK at HW side

PR412
100K_0402_5%

@EMI@

PC412
3.3V LDO 150mA~300mA

x
2

2
2 2
Vout is 3.234V~3.366V
<22> SPOK

TDC=6A

fi
@ PJ401
+3VALWP 1 2 +3VALW
1 2
JUMP_43X118
B+ EMI@ PL403 EN1 and EN2 dont't floating
HCB2012KF-121T50_0805
1 2 5V_VIN

a
@ PJ402
Vout is 4.998V~5.202V +5VALWP 1 2 +5VALW
1 2
2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

PU402 PC413 PR406 JUMP_43X118

8 1 3V5V_EN 6800P_0402_25V7K 1K_0402_5%
TDC=6A
IN EN

in
1 2 1 2
1

1
PC414

PC415

EMI@ PC417

@EMI@ PC418

3 5V_FB PR407 PC416

FB 2.2_0603_5% 0.1U_0603_25V7K
6 BST_5V 1 2 1 2
2

BS
@
PL404
9 10 LX_5V 1 2 +5VALWP
GND LX
VCC_3V 5 4 1.5UH_PCMB053T-1R5MS_6A_20%
VCC OUT

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
PR408

680P_0603_50V7K 4.7_1206_5%
h

1
@EMI@
2 7
VL
SPOK_5V

PG LDO
1

PC419

PC420

PC421

PC422

PC423

@ PC427

@ PC428
3 3
4.7U_0603_6.3V6M

SY8208CQNC_QFN10_3X3

2
1 5V_SN
2

2
1

PC424
4.7U_0603_6.3V6M
1

.c
0_0402_5%
@ PR413

PC425
@EMI@

2
2

PR409
22u Capacitor change to 0603 size.
SPOK

2.2K_0402_5%

<22> EC_ON
1 2 5V LDO 150mA~300mA 2013/10/16 modify.
reserve PC427,PC428 for IC Application.
w

@PR410
@ PR410
1 2 Add non-pop PR413 for Test. 2013/11/29 modify.
<22,33> MAINPWON 0_0402_5% 2013/11/04 modify.
3V5V_EN
1M_0402_1%

w
4.7U_0402_6.3V6M
1

EC VDD0 is +3VL, PC13 UNPOP

1
PR411

PC426

EC VDD0 is +3VALW, PC13 POP

2
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+3VALW/+5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 35 of 45
A B C D E
 5 4 3 2 1

Module model information

RT8207M_V1.mdd For Single layer
RT8207M_V2.mdd For Dual layer

D D

m
Pin19 need pull separate from +1.5VP.
If you have +1.5V and +0.75V sequence question, 0.75Volt +/- 5%

o
EMI@ PL501 you can change from +1.5VP to +1.5VS. TDC 1.4A
HCB2012KF-121T50_0805
B+ 1 2 1.5V_B+ PR501 Peak Current 2A
2.2_0603_5%
BST_1.5V 1 2 BOOT_1.5V

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
+1.5VP

.c
1

1
@EMI@ PC502

EMI@ PC503

PC504

PC505
DH_1.5V +0.75VSP
2

2
SW _1.5V

10U_0805_6.3V6K

10U_0805_6.3V6K
1

1
PC501

PC506

PC507
5
0.1U_0603_25V7K

16

17

18

19

20
x
2
C PU501 C

AON7408L_DFN8-5

2
2013/10/22 Modify

VLDOIN
PHASE

UGATE

BOOT

VTT
21
PAD
PL502,PC509 change to common part.

PQ501
4 DL_1.5V 15 1
LGATE VTTGND

fi
14 2
PL502 PR502 PGND VTTSNS

1
2
3
1UH_11A_20%_7X7X3_M 22.6K_0402_1%
1 2 1 2 CS_1.5V 13 3
+1.5VP PC508 CS RT8207MZQW _W QFN20_3X3 GND
1

1U_0603_10V6K

a
330U_2.5V_ESR17M_6.3X4.5

5
1 2 12 4 VTTREF_1.5V
VDDP VTTREF
ESR=17m ohm

@EMI@ PR503 PR504

AON7506_DFN33-8-5

1 4.7_1206_5% 5.1_0603_5%
1 2 VDD_1.5V 11 5
+5VALW +1.5VP
1 2

VDD VDDQ

1
+

PGOOD
PQ502
PC509

in
4 PC510

TON
1
@EMI@ PC512 0.033U_0402_16V7K

FB
S5

S3

2
2 680P_0402_50V7K PC513
+5VALW
2

1U_0603_10V6K

10

6
1
2
3

FB_1.5V
EN_0.75VSP
TON_1.5V
PR506

EN_1.5V
10K_0402_1%
2013/10/14 update PR507 1 2 +1.5VP
B
PQ502__AON7702A EOL chang
h 1.5V_B+
887K_0402_1%
1 2 B

1
-->AON7506_SB000010A00
@ PR509 PR508
.c
0_0402_5% 10K_0402_1%
MOSFET: 3x3 DFN 1 2
<22> SYSON

2
Mode Level +0.75VSP VTTREF_1.5V H/S Rds(on): 27mohm(Typ), 34mohm(Max)
S5 L off off

1
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C @ PC514
S3 L off on 0.1U_0402_10V7K
S0 H on on

2
L/S Rds(on): 13mohm(Typ), 15.8mohm(Max)
Idsm: 12A@Ta=25C, 10.5A@Ta=70C
w

Note: S3 - sleep ; S5 - power off @ PR510

0_0402_5%
Choke: 7x7x3 1 2 @ PJ501
<22,30> SUSP# +1.5VP 1 2 +1.5V
Rdc=8.3mohm(Typ), 10mohm(Max) 1 2

1
JUMP_43X118
@ PC515 @ PJ502
for this project
w

0.1U_0402_10V7K 1 2

2
Switching Frequency: 285kHz 1 2
Ipeak=11A JUMP_43X118

OCP:15.939A~13.371A PJ503
@
OVP: 110%~120% 1 2
+0.75VSP 1 2 +0.75VS
VFB=0.75V, Vout=1.515V
w

A
JUMP_43X39 A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2014/03/27 Deciphered Date 2016/03/27
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VP/+0.75VSP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 36 of 45
5 4 3 2 1
 5 4 3 2 1

Module model information

SY8033_V1.mdd
D D

m
o
22u Capacitor change to 0603 size.
2013/10/16 modify.

.c
2013/10/22 Modify FB=0.6V
PL601 change to common part. Note:Iload(max)=3.5A

x
C @ PJ601 PU601 PL601 C

4
1UH_2.8A_30%_4X4X2_F
+3VALW 1 2 10 2 LX_1.8V 1 2

PG
1 2 PVIN LX +1.8VALWP
9 3
Rup

68P_0402_50V8J
22U_0603_6.3V6M

fi
JUMP_43X79 PVIN LX

1
PC601

@EMI@ PR603
4.7_0603_5%

1
8

PC602

22U_0603_6.3V6M

22U_0603_6.3V6M
SVIN

1
PR604

2
6

PC603

PC604
20K_0402_1%
22u Capacitor change to 0603 size.

2
5 FB

2
EN
2013/10/16 modify.

NC

NC
@ PR601

TP
0_0402_1% FB_1.8V
1 2 +1.8VSP_ON

a
<22,38> 0.95_1.8VALW_PWREN

11

1
Rdown

1
0.1U_0402_16V7K

1
PC605

@EMI@ PC606
680P_0402_50V7K
1
SY8033BDBC_DFN10_3X3 PR606
10K_0402_1%

2
2

2
in
Note: Vout=0.6V* (1+Rup/Rdown)

B
When design Vin=5V, please stuff snubber
to prevent Vin damage

Delete PR605,because same net name have two PD resister in circuit.

h @ PJ602
B
.c
1 2
2013/11/29 modify. +1.8VALWP 1 2 +1.8VALW
JUMP_43X79
w
w
w

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.8VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 37 of 45
5 4 3 2 1
 5 4 3 2 1

D D

m
Module model information
SY8208D_V1.mdd

o
.c
EN pin don't floating
If have pull down resistor at HW side, pls delete PR2
@ PR702
0_0402_5%
1 2
for this project

x
0.95_1.8VALW_PWREN <22,37>
C C
Ipeak=8A

1
1M_0402_1%
@ PC702 Add 22u*2 capacitor,
0.22U_0402_10V6K
Chock change to 0.68u.

2
PR703
meet DC-DC design check form.

fi
2
2013/10/02 Modify.
@EMI@ PR704 @EMI@ PC703
4.7_1206_5% 680P_0603_50V7K
EMI@ PL701 1 2SNB_0.95V 1 2
HCB2012KF-121T50_0805 PU701
B+ 1 2 B+_0.95V 8
IN EN
1 PR705
0_0603_5%
PC706
0.1U_0603_25V7K
10U_0805_25V6K

10U_0805_25V6K

a
6 1
BST_0.95V 2 1 2 PL702 TDC 8A
0.1U_0402_25V6
2200P_0402_50V7K

BS
1

0.68UH_PCMC063T-R68MN_15.5A_20%
@EMI@ PC704

PC707

PC705

LDO_3V 9 10 LX_0.95V 1 2
+0.95VALWP
EMI@ PC701

GND LX
2

11.8K_0402_1%

47U_0805_6.3V6M

47U_0805_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
1

330P_0402_50V7K
1

1
@ PR706 4

PR707
FB

PC708

PC709

PC710

PC711

PC712

PC716

PC715
0_0402_5% Rup

in
ILMT_0.95V3 7
+3VALW 22u Capacitor change to 0603 size.

2
ILMT BYP

2
4.7U_0603_6.3V6K
2

ILMT_0.95V 2 5 LDO_3V 2013/10/16 modify.

4.7U_0603_6.3V6K
PG LDO
1

PC714
1

SY8208DQNC_QFN10_3X3
PC713

FB = 0.6V
2

1
@ PR708
2

0_0402_5% PR709
Rdown
2

20K_0402_1%

2
@ PJ701

B
The current limit is set to 8A, 12A or 16A when this pin
is pull low, floating or pull high
Pin 7 BYP is for CS.
Common NB can delete
h +3VALW and PC714

VFB=0.6V
+0.95VALWP 1
1
JUMP_43X118
2
2 +0.95VALW B
.c
Vout=0.6V* (1+Rup/Rdown)
Vout=0.954V
w
w
w

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+0.95VALWP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 38 of 45
5 4 3 2 1
 5 4 3 2 1

2013/10/16 Modify
PQ801,PQ803 change to AON6552.
<6> APU_VDD_RUN_FB_L APU_VDD_SEN <6> PQ802,PQ804,PQ805 change to AON6554.
Module model information

1
PC802
0.01U_0402_50V7K CPU_B+
10_0402_5% 10_0402_5% RT8880A_V1A.mdd for IC portion EMI@ PL801

2
1 2 1 2 HCB2012KF-121T50_0805
+APU_CORE
1 2
D PR802 PR803 RT8880A_V1B.mdd for SW portion B+ D

680P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
AON6552_DFN5X6-8-5
1

@ PC803

1
PQ801

PC804

PC801
2
PR801 0_0603_5%
UGATE_NB1 1 2 4

m
2

2
1
1 2

2K_0402_1%
@ PR804
@ PC805 PR805 PL802
330P_0402_50V7K 2.2_0603_1% PC806 0.36UH_PDME064T-R36MS_24A_20%

3
2
1
PR806 PR807 1
BOOT_NB1 2 1 2
BOOT_NB1-1 1 4
+APU_CORE_NB

2
10K_0402_1% 64.9K_0402_1%
1 2 1 2 PR808 0.22U_0603_25V7K 2 3

4.7_1206_5%
CPU_B+

1
1 2 PR810

@EMI@ PC810 @EMI@ PR809

AON6554_DFN5X6-8-5
PHASE_NB1 2.61K_0402_1%
PC809 PC807 110K_0402_1% 1 2 1 2

o
560P_0402_50V7K 68P_0402_50V8J

PQ802
1 2 1 2 PC808

2
LGATE_NB1 4 .1U_0402_16V7K
SNB_APU_NB

1
+5VS

680P_0603_50V7K
@ PR811
0_0402_5%

3
2
1

.c
1 2

TONSET
COMP

FB

ISEN1N
ISEN1P
+5VS

ISENA1N-1
ISENA1P
PR812
PU801 910_0402_1%

13

12

11

10

1
RT8880BGQW_WQFN52_6X6 ISENA1N 1 2
2013/10/22 Modify

PWM3

BOOT2

UGATE2
VSEN

ISEN3N

ISEN1N

ISEN2N

TONSET
COMP

FB

ISEN3P

ISEN1P

ISEN2P
APU_CORE_NB

0.1U_0402_25V6
1
53
PH801,PH802 change to common part.

PC811
GND +5VS TDC 13A

x
C 14 52 @ PR813 C

2
RGND PHASE2 0_0402_1% @ Peak Current 17 A
IMON 15 51 PVCC 1 2
IMON LGATE2 OCP current > 33A
VREF 16 50 PVCC
V064 PVCC VCC 1 2
Load line -4mV/A
PC812 IMONA 17 49 LGATE1 FSW=450kHz

fi
1U_0402_6.3V6K +1.5VS IMONA LGATE1 PR814

2.2U_0603_10V7K

2.2U_0603_10V7K
DCR 1.4mohm +/-5%

1
1 2 VDDIO 18 48 PHASE1 10_0603_5%

PC813

PC814
VDDIO PHASE1

<6> APU_PWRGD
19 47 UGATE1 TYP MAX

2
PWROK UGATE1
20 46 BOOT1
H/S Rds(on) :6.7mohm , 8.5mohm
<6> APU_SVC SVC BOOT1
21 45 LGATE_NB1
L/S Rds(on) :3mohm , 3.8mohm
<6> APU_SVD SVD LGATEA1

a
22 44 PHASE_NB1
<6> APU_SVT SVT PHASEA1 CPU_B+
16K_0402_1%
24.9K_0402_1%

OFS 23 43 UGATE_NB1
OFS UGATEA1
PR815

PR816

OFSA 24 42 BOOT_NB1
OFSA BOOTA1

5
1

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

2200P_0402_50V7K
AON6552_DFN5X6-8-5
1

SET1 25 41

@EMI@ PC818

EMI@ PC819
68U_25V_M
0_0402_5%

0_0402_5%

+5VS
2

SET1 PWMA2

1
PR819 +
@ PR817

@ PR818

in

1
SET2 26 40 1 2 CPU_B+

PQ803

PC816

PC817

PC815
SET2 PGOODA TONSETA PR820 0_0603_5%
ISENA2N

ISENA1N
ISENA2P

ISENA1P

2
2
PGOOD
1 2 4
COMPA

110K_0402_1% UGATE1
VSENA
OCP_L
2

2
IBIAS
VCC

FBA

PR821 PR822 PHASE1

EN
100K_0402_1%_B25/50 4250K

4.99K_0402_1% 7.68K_0402_1% PR823 PL803

100K_0402_1%_B25/50 4250K

1 2 1 2 2.2_0603_1% 0.36UH_PDME064T-R36MS_24A_20%
27

28

29

30

31

32

33

34

35

36

37

38

39

3
2
1
BOOT11 2 1
BOOT1-1 2 1 4
19.6K_0402_1%
1

PR825 VGATE <22> +APU_CORE

PC820 2 3
ISENA1N
PH801

PR824

PH802

@EMI@ PR828
ISENA1P
COMPA

4.7_1206_5%
5

5
VCC

16.9K_0402_1% 0.22U_0603_25V7K
FBA
1 IBIAS

AON6554_DFN5X6-8-5

AON6554_DFN5X6-8-5
1
PR829
<22,6,7> PROCHOT# 1

h 2
+3VS 2.61K_0402_1%
2

VREF 1 2 1 2

PQ804

PQ805
B Pull high at HW side PR826
B
100K_0402_1%

+5VS 100K_0402_5% LGATE1 4 4 PC821

PR827

1 2
VR_ON <22> SNB_APU .1U_0402_16V7K
0.1U_0402_25V6

0.1U_0402_25V6
1

1
PC822

PC823

@EMI@ PC824
680P_0603_50V7K
2

.c
2

3
2
1

3
2
1

2
1

PC831 @ PR831
0.1U_0402_25V4K 4.12K_0402_1%
2

PC825 68P_0402_50V8J PC826 1 2

1 2 1 2

560P_0402_50V7K ISEN1P

ISEN1N-1
PR832 PR833
1 2 1 2 PR838
1

@ 910_0402_1%
97.6K_0402_1% 10K_0402_1%
PC827 APU_core ISEN1N 1 2
w

@ PR837
1 2 TDC 20A

0.1U_0402_25V6
Peak Current 25A

1
2K_0402_1% 330P_0402_50V7K

@ PC828
2

OCP current > 35A

2
1

@ PC829
Load line -4mV/A
APU_VDD_RUN_FB_L
APU_VDDNB_SEN

<6>

680P_0402_50V7K FSW=450kHz
2
w

PR842 DCR 1.4mohm +/-5%

SET1

1 2
PR843 PR844 PR845
+APU_CORE_NB TYP MAX
1

20.5K_0402_1% 1K_0402_1% 124K_0402_1% 10_0402_5%

1 2 1 2 1 2 PC830
H/S Rds(on) :6.7mohm , 8.5mohm
0.01U_0402_50V7K L/S Rds(on) :3mohm , 3.8mohm
2

PR846 PR847 PR848 +5VS

470_0402_1% 1K_0402_1% 124K_0402_1%
1 2 1 2 1 2
w
SET2

A A

Delete PR834.PR835.PR836.PR839.PR840.PR841,
follow vender FAE suggest.
2013/11/29 modify. Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
APU_CORE/APU_CORE_NB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 39 of 45
5 4 3 2 1
 A
B
C
D

5
5

PC932
560U_D2_2VM_R4.5M

2
1
+
@
PC929 PC901
0.22U_0402_16V7K 10U_0805_6.3V6M

+APU_CORE
2 1 2 1 2 1 2 1
1U_0402_6.3V6K 1U_0402_6.3V6K
PC930 PC918 PC908 PC905
180P_0402_50V8J 2 1 2 1 10U_0805_6.3V6M
+APU_CORE

2 1 2 1

2
1
1U_0402_6.3V6K 1U_0402_6.3V6K

+
PC933 PC919 PC909 PC906
330U_D2_2V_Y 2 1 2 1
10U_0805_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 2 1
PC920 PC910
2 1 2 1
1U_0402_6.3V6K 1U_0402_6.3V6K
PC921 PC911
2 1 2 1

2
1
+
w @ PC934
330U_D2_2V_Y
1U_0402_6.3V6K

2
PC922
1
1U_0402_6.3V6K
PC912

4
4

1U_0402_6.3V6K
w PC923

w
+APU_CORE (36.4)

.c
h

Issued Date
Security Classification

3
3

in
PC935
560U_D2_2VM_R4.5M
a
2014/03/27
2
1
+

PC931 PC902
180P_0402_50V8J 10U_0805_6.3V6M
2 1 2 1 2 1 2 1
1U_0402_6.3V6K 1U_0402_6.3V6K PC903
PC924 PC913 10U_0805_6.3V6M
+APU_CORE_NB

2 1 2 1 2 1
fi
1U_0402_6.3V6K 1U_0402_6.3V6K PC904
2
1
+

PC925 PC914 10U_0805_6.3V6M

@ PC936 2 1 2 1 2 1
330U_D2_2V_Y
1U_0402_6.3V6K
x 1U_0402_6.3V6K
+APU_CORE_NB

PC907
PC926 PC915 10U_0805_6.3V6M
2 1 2 1 2 1
Compal Secret Data
Deciphered Date
1U_0402_6.3V6K 1U_0402_6.3V6K
PC927 PC916
2 1 2 1
.c
1U_0402_6.3V6K 1U_0402_6.3V6K
2
2

@ PC928 PC917

o
2016/03/27

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

m
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
+APU_CORE_NB (36.5)

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Title

Date:
Custom
Size Document Number

Thursday, March 27, 2014

1
1

Sheet
40
Compal Electronics, Inc.

of
45
APU_CORE/APU_CORE capacitor
Rev
1.0
A
B
C
D
 5 4 3 2 1

Module model information

TPS51212_V1.mdd for Single layer
TPS51212_V2.mdd for Dual layer
D D
VGA_EMI@ PL1001
HCB2012KF-121T50_0805
+1.5VSDGPUP_B+ 1 2
2013/10/16 Modify B+

m
2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
PQ1001 change to AON7408L.

PC1005
1

1
@EMI@ PC1002

VGA_EMI@ PC1003

VGA@ PC1004
PQ1002 change to AON7506.

2
@

o
AON7408L_DFN8-5
VGA@ PQ1001
2013/10/22 Modify
4
PL1002,PC1009 change to common part.
2013/10/18 Modify

.c
VGA@ VGA@ PR1001 VGA@ PC1001
PR1004 change to 0 ohm. VGA@ PR1003 1
PU1001
10 1
2.2_0603_5%
BST_+1.5VSDGPUP 2
0.1U_0603_25V7K
1 2 VRAM

3
2
1
66.5K_0402_1% PGOOD VBST
@ PR1004 1 2TRIP_+1.5VSDGPUP2 9 UG_+1.5VSDGPUP VGA@ PL1002
0_0402_5% TRIP DRVH 2.2UH_7.8A_20%_7X7X3_M
<16,42,7> VGA_PW RGD 1 2 EN_+1.5VSDGPUP 3 8 SW _+1.5VSDGPUP 1 2
EN SW +1.5VSDGPUP
FB_+1.5VSDGPUP 4 7
VFB V5IN +5VALW

1
x
0.1U_0402_16V7K

AON7506_DFN33-8-5
C RF_+1.5VSDGPUP 5 6 LG_+1.5VSDGPUP @EMI@ C
TST DRVL
1

PR1005

VGA@ PQ1002
PC1006

330U_2.5V_ESR17M_6.3X4.5
1
11 4.7_1206_5%
TP

1
VGA@ VGA@ +

VGA@ PC1009
2

2
PR1006 TPS51212DSCR_SON10_3X3 PC1007 4 ESR=17m ohm

fi
@ 470K_0402_1% 1U_0603_6.3V6M

1
PC1010 @EMI@ 2
2 680P_0402_50V7K

3
2
1

2
a
VGA@ PR1007
11.5K_0402_1%
1 2

in
1

VGA@
PR1008
10K_0402_1%
2

B MOSFET: 3x3 DFN

H/S Rds(on): 27mohm(Typ), 34mohm(Max)
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C
h +1.5VSDGPUP 1
@ PJ1001
1 2
JUMP_43X118
2 +1.5VSDGPU
B
.c
@ PJ1002
L/S Rds(on): 13mohm(Typ), 15.8mohm(Max) 1
1 2
2
Idsm: 12A@Ta=25C, 10.5A@Ta=70C JUMP_43X118

Choke: 7x7x3
Rdc=15.5mohm +/-15%
w

Vout PR1007 PR1008 PR1003 +1.5V(for this project)

w

Switching Frequency: 290kHz

+1.2V 7.15K 10k 105K Ipeak=4.7A
OCP:6.884A~5.751A
OVP: 120%~130%
+1.05V 4.99k 10k 93.1k VFB=0.704V, Vout=1.514V
w

A PR1003=66.5K Ohm A

+1.5V 11.5K 10k 105K

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.5VSDGPUP
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 41 of 45
5 4 3 2 1
 A B C D E

GPIO21 GPIO29 GPIO30 GPIO20 GPIO15 AMD MARS series LP: DDR3 AMD SUN series UL: DDR3 Description
Pro/XT/XTX: GDDR5 Pro/XT/XTX: GDDR5
VID5 VID4 VID3 VID2 VID1 VDDC
0 1 1 1 1 1.125V GPU MARS XTX MARS XT MARS PRO MARS LP SUN UL SUN PRO SUN XT NA
1 0 0 0 0 1.100V
VDDC 0.775~1.175V 0.775~1.125V 0.775~1.050V 0.775~1.000V 0.775~1.125V 0.800~1.075V 0.800~1.150V NA
1 0 0 0 1 1.075V
2013/10/16 Modify 1 0 0 1 0 1.050V TDC 32A (TDC) 25A (TDC) 21A (TDC) 17A (TDC) 16A (TDC) 19A (TDC) 25A (TDC) NA
PQ1201,PQ1203 change to AON6552. 1 0 0 1 1 1.025V
PQ1202,PQ1204 change to AON6554. EDC 48A 37.5A 31.5A 26A 24A 28.5A 37.5A NA
1 0 1 0 0 1.000V
1 0 1 0 1 0.975V OCP 57.6A 45A 37.8A 31.2A 28.8A 34.2A 45A NA
1
1 0 1 1 0 0.950V 1

Vboot 0.85V 0.85V 0.85V 0.85V 0.9V 0.9V 0.9V NA

1 0 1 1 1 0.925V
"Jet Type" 1 1 0 0 0 0.900V Vboot(merge) Load line 1mohm 1mohm 1mohm --------- --------- --------- 1mohm NA MOS
Remark: TYP MAX
1 1 0 0 1 0.875V
1. PWM3 (Pin24) tie to 5V & CLK# (Pin40) external pull high Ri for OCP and H/S Rds(on) :6.7mohm , 8.5mohm
1.13K Ohm 887 Ohm 750 Ohm --------- --------- --------- 887 Ohm

m
1 1 0 1 0 0.850V PR1248 LoadLine Setting L/S Rds(on) :3mohm , 3.8mohm
=> 2 phase CPU VR config
PWM3 (Pin24) tie to 5V & CLK# (Pin40) tie to GND or floating 1 1 0 1 1 0.825V
=> 2 phase GPU VR config Rdroop for LoadLine Choke: 0.22uH (Size:7*7*4)
1 1 1 0 0 0.800V PR1229 1.43K Ohm 1.13K Ohm 953 Ohm --------- --------- --------- 1.13K Ohm Setting Rdc=0.98mohm +-5%
1 1 1 0 1 0.775V Heat Rating Current=28A
2. When 2 Phase GPU config PR1233 187K Ohm 147K Ohm 124K Ohm --------- --------- --------- 147K Ohm for Compensation Saturation Current=28A
a. DPSLPVR (Pin39)=0 PSI# (Pin2)=0
=>1 phase CCM operation mode 2013/10/18 Modify 2013/11/29 Modify
b. DPSLPVR (Pin39)=0 PSI# (Pin2)=1 EN Signal change to VGA_ON. Delay Time follow HW request. PR1236 51.1K Ohm 51.1K Ohm 51.1K Ohm --------- --------- --------- 51.1K Ohm for Positive offset

o
=>2 phase CCM operation mode Delay Time follow HW request. Add PD Resister(PR1250)
c. DPSLPVR (Pin39)=1 PSI# (Pin2)=0 or 1
=>1 phase DE operation mode 2013/12/16 Modify Remark: MARS LP/ SUN UL/ SUN PRO
Delay Time follow HW request. don't use this 2-phase solution
3. Rbias=147K =>overshoot reduction function disable @ PR1201

.c
0_0402_5% +3VSDGPU Vboot regulation
Rbias=47k =>overshoot reduction function enable 1 2 +VGA_B+ VGA_EMI@
PL1201

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
1

<16> VGA_ON_B 1 2
@ PR1250

33P_0402_50V8J
1 B+
1M_0402_1%

VGA@ PC1201

4. Thermal throttling:

1
FBMA-L11-453215800LMA90T_2P

2200P_0402_50V7K

VGA@ 10U_0805_25V6K

VGA@ 10U_0805_25V6K
0.1U_0402_25V6
Protect: (6.98K+Rth)*60uA=1.2V @ PR1249
2

=> Rth=13.02K

@EMI@ PC1202

VGA_EMI@ PC1203
0_0402_5%
2

1
1 2

PC1204

PC1205
=>Tp=110C (+-3C) <13> GPU_DPRSLPVR

VGA@ PR1202

VGA@ PR1203

PR1204

@ PR1205

PR1206

PR1207

PR1208

PR1209

VGA@ PR1210

VGA@ PR1211

VGA@ PR1212

VGA@ PR1213
GPU_VID5 2

GPU_VID4 2

GPU_VID3 2

GPU_VID2 2

GPU_VID1 2

GPU_VID0 2

GPU_VID5 2

GPU_VID4 2

GPU_VID3 2

GPU_VID2 2

GPU_VID1 2

GPU_VID0 2
Recovery:(6.98K+Rth)*56uA=1.24V

2
=> Rth=15.16K VGA@ PR1214
Module model information:

5
1 2 DPRSLPVR_VGA-1

AON6552_DFN5X6-8-5
=> Tr=105C (+-3C) @ @ @ @ @ ISL62883C_V1A for IC

x
VGA@ PQ1201
10K_0402_1% VGA@
2
PR1226=6.98K PR1226=1.5K PR1216 ISL62883C_V1B for SW Choke/MOS on BTN 2

VGA@ PR1215 0_0603_5%

protect T protect T +3VSDGPU 1 2 UGATE2_VGA 1 2 4 ISL62883C_V2B for SW Choke on BTN, MOS on TOP
110C +-3 100C +-3 1.91K_0402_1% VGA@ PR1217 VGA@ PC1206
GPU_VID5

GPU_VID4

GPU_VID3

GPU_VID2

GPU_VID1
<13>

<13>

<13>

<13>

<13>
2.2_0603_5% 0.22U_0603_25V7K
Recovery T Recovery T BOOT2_VGA 1 2
BOOT2_2_VGA 1 2

3
2
1

fi
VGA@ PL1202
105C +-3 96C +-3 <16,41,7> VGA_PWRGD
0.22UH_PCME064T-R22MS_28A_20% +VGA_CORE
PHASE2_VGA 1 4

GPU_VID0
5. Switching frequency set : +3VSDGPU 1 2 2 3

5
VRON_VGA

VGA@ PR1218
GPU_VID6

Rfset(kohm)=[period(us)-0.29]*2.65

1
@EMI@ PR1219
100K_0402_5%

4.7_1206_5%
Rsum

AON6554_DFN5X6-8-5
=5.9Kohm

VGA@ PQ1202
Rbias VGA@ PR1220
fsw=1/period(us)=400KHZ 147K_0402_1% Ro

3.65K_0402_1%
a
PSI#_VGA

1
1 2 LGATE2_VGA 4

1_0402_1%
VGA@ PR1222
10K_0402_1%

10K_0402_1%
SNUB2_VGA
2

VGA@ PR1221

VGA@ PR1224
VGA@ PR1223
RBIAS_VGA

3
2
1

2
VGA@ PR1225

680P_0603_50V7K
Layout Note:
40
39
38
37
36
35
34
33
32
31

@EMI@ PC1210
100K_0402_5% PU1201
PH1201 should place near 1 2
CLK_EN#

VID6
VID5
VID4
VID3
VID2
VID1
VID0
DPRSLPVR
VR_ON

+3VSDGPU

1
in
phase1 H-side MOS
30 VSUM+_VGA ISEN2_VGA ISEN1_VGA VSUM-_VGA
BOOT2 29
Rth

2
1 UGATE2 28
2 PGOOD PHASE2 27
6.98K_0402_1% 470K_0402_5%_B25/50 4700K 3 PSI# VSSP2 26
1 2 1 2 4 RBIAS LGATE2 25
5 VR_TT# VCCP 24 VGA@
+5VS 2013/11/29 Modify
VGA@ PR1226 VGA@ PH1201 VW_VGA 6 NTC PWM3 23
PL1202.PL1203 change to common part.

1U_0603_10V6K

1U_0603_10V6K
VW LGATE1

1
7 22

PC1212

PC1213
COMP_VGA
FB_VGA 8 COMP VSSP1 21
1 2ISEN3_VGA 9 FB PHASE1
Rfset
2

2
UGATE1

10 ISEN3
1000P_0402_50V7K

BOOT1

VGA@
ISUM+

ISEN2
1

ISEN1

ISUM-
VSEN

IMON

VGA@ PC1211
5.9K_0402_1%

VDD
RTN

h
VIN

41 +VGA_B+
VGA@ PR1227

VGA@ PC1214

22P_0402_50V8J
AGND
1

VGA@ ISL62883CHRTZ-T_TQFN40_5X5
11
12
13
14
15
16
17
18
19
20

3 3
PR1228 VGA@ PC1215 VGA@
2

499_0402_1% 390P_0402_50V7K TDC 28A

1 2FB1_VGA
1 2
ISUM-_VGA

VDD_VGA
RTN_VGA

Peak Current = 42A

OCP Current = 48.6A

10U_0805_25V6K

10U_0805_25V6K
VGA@ PC1217

VGA@ PC1218
VGA@ PR1229
BOOT1_VGA
.c
Load line=mohm

5
1.24K_0402_1% 1 2

AON6552_DFN5X6-8-5
+5VS

1
VGA@ PC1216 1 2 VSEN_VGA @ PR1230

VGA@ PQ1203
33P_0402_50V8J @ PR12310_0402_5% 10K_0402_1%
1 2 VIN_VGA 1 2 VGA@ PR1232
Rdroop

2
ISEN2_VGA +VGA_B+ 0_0603_5%
VGA@ PC1219 VGA@ PR1233 VGA@ PR1234 PR1230 Pop: UGATE1_VGA 1 2 4
150P_0402_50V8J 147K_0402_1% ISEN1_VGA 1_0402_5%
1 2FB2_VGA1 2 1 2 for Loadline disable
0.22U_0402_16V7K

0.22U_0402_16V7K

PR1230 @: 1 2 BOOT1_1_VGA 1 2
VGA@ PC1221

VGA@ PC1222

VGA@ PC1223

0.22U_0603_25V7K

+5VS
1

1
VGA@ PR1236

VGA@ PC1224

VGA@ PR1235
51.1K_0402_1%

for Loadline enable

3
2
1
1

2.2_0603_5% VGA@ PC1220 VGA@ PL1203

1U_0603_10V6K

and LL=1mohm 0.22U_0603_25V7K 0.22UH_PCME064T-R22MS_28A_20% +VGA_CORE

2

PHASE1_VGA 1 4
for positive offset
2

2 3

AON6554_DFN5X6-8-5

1
VGA@ PQ1204
VSUM-_VGA

4.7_1206_5%
@EMI@
PR1238
1 2
+VGA_CORE
LGATE1_VGA 4

SNUB1_VGA
VSUM+_VGA

2 PR1242 1
1_0402_1%
VGA@ PR1237

10K_0402_1%

10K_0402_1%
3.65K_0402_1%
2
w

VGA@ PR1239

VGA@ PR1240
10_0402_1%

VGA@ PR1241
Cn
3
2
1
VGA@ PR1244

@ PR1243
2.61K_0402_1%

2
1

1 2
1

<15> VCC_GPU_SENSE

VGA@
@EMI@
PC1229
680P_0603_50V7K
0_0402_5%

1
VGA@ PC1228
Rp Rntcs
0.033U_0402_16V7K

1000P_0402_50V7K
0.15U_0603_16V7K
2

330P_0402_50V7K

2
1
VGA@ PC1231

VGA@ PC1232

VGA@ PR1245
11K_0402_1%
1

VSUM+_VGA ISEN1_VGA ISEN2_VGA

@ PC1230

w
1NTC_VGA

Transient response : VSUM-_VGA

Rntcnet=(Rntcs+Rntc)*Rp/(Rntcs+Rntc+Rp)
2

4 4
2

Cn=L*(Rntcnet+Rsum/N)/[Rntcnet*DCR*(Rsum/N)]
1

@ PR1246 VGA@ PC1233

1 2 1000P_0402_50V7K VGA@ PH1202 N is the number of phases
<15> VSS_GPU_SENSE 10K_0402_1%_B25/50 3370K 2013/10/22 Modify
2

0_0402_5%
Rntc Rdroop=Io*LL/Idroop
PH1201,PH1202 change to common part.
2

VGA@ PR1248
976_0402_1%
1 2 1 2
VSUM-_VGA
2013/10/25 Modify VGA@ PR1247
Ri
PR1229 change to 1.24K ohm. 10_0402_1% Layout Note:
1

VGA@ PC1234
PR1248 change to 976 ohm. .1U_0402_16V7K PH1202 should place near Security Classification Compal Secret Data Compal Electronics, Inc.
Phase1 Choke Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title
2

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ISL62883C
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 42 of 45
A B C D E
 A
B
C
D

5
5

2 1 2 1

VGA@ PC1339 VGA@ PC1328

+VGA_CORE
22U_0603_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1 2 1
+VGA_CORE

VGA@ PC1340 VGA@ PC1329 VGA@ PC1319 VGA@ PC1309 VGA@ PC1301
22U_0603_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M
2 1 2 1 2 1 2 1 2 1

VGA@ PC1341 VGA@ PC1330 VGA@ PC1320 VGA@ PC1310 VGA@ PC1302
22U_0603_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1 2 1

VGA@ PC1342 VGA@ PC1331 VGA@ PC1321 VGA@ PC1311 VGA@ PC1303
22U_0603_6.3V6M 2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1 2 1

VGA@ PC1343 VGA@ PC1332 VGA@ PC1322 VGA@ PC1312 VGA@ PC1304
22U_0603_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M
w 2 1 2 1 2 1 2 1

VGA@ PC1333 VGA@ PC1323 VGA@ PC1313 VGA@ PC1305

10U_0402_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1 2 1

4
4

VGA@ PC1334 VGA@ PC1324 VGA@ PC1314 VGA@ PC1306

10U_0402_6.3V6M 2.2U_0402_6.3V6M 10U_0402_6.3V6M 2.2U_0402_6.3V6M
w 2 1 2 1 2 1
2
1
+

VGA@ PC1335 VGA@ PC1325 VGA@ PC1315 VGA@ PC1307

2.2U_0402_6.3V6M 560U_2.5V_M 2.2U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1
2
1
+

Issued Date
w VGA@ PC1336
10U_0402_6.3V6M
2 1
VGA@ PC1326
560U_2.5V_M
VGA@ PC1316
2.2U_0402_6.3V6M
2 1
VGA@ PC1308
2.2U_0402_6.3V6M

Security Classification
1
+

2@

VGA@ PC1337 PC1327 VGA@ PC1317

10U_0402_6.3V6M 330U_D2_2.5VY_R9M 2.2U_0402_6.3V6M
2 1 2 1

VGA@ PC1338 VGA@ PC1318

.c
10U_0402_6.3V6M 10U_0402_6.3V6M

2014/03/27

3
3

meet ripple

in
AMD MARS
AMD MARS
GPU_CORE

22uF*5+10uF*11
10uF*8+2.2uF*16

a
560uF*2+330uF*1

Compal Secret Data

Deciphered Date
fi
2016/03/27
x
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
.c
2
2

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

o
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Title

Date:

m
Custom
Size Document Number

Thursday, March 27, 2014

VGA_CORE CAP

1
Sheet
1

43
Compal Electronics, Inc.

of
45
Rev
1.0
A
B
C
D
 5 4 3 2 1

Version change list (P.I.R. List) Page 1of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

Design Change. Design Change of Diode Application. 0.2 32 Change PD101 to SCSS4004010(S SCH DIO BAS40-04 SOT23). 2013/11/29 DVT
D 1 D

Design Change. Design Change of IC Application. 0.2 35 Add non-pop component PC427,PC428. 2013/11/29 DVT
2

m
Design Change. reduce part count. 0.2 37 Delete PR605 PD resister. 2013/11/29 DVT
3

o
Design Change. reduce part count. 0.2 39 Delete @PR834.@PR835.@PR836.@PR839.@PR840.@PR841. 2013/11/29 DVT
4

.c
Design Change. Design Change of VGA Type Application. 0.2 42 PR1205 change to non-pop. 2013/11/29 DVT
5 PR1211 change to pop.

Design Change. Design Change of common part. 0.2 34 Change PL301 to SH00000YG00 2013/11/29 DVT
6 (S COIL 1UH +-30% 2.8A 4X4X2 FERRITE).

x
C C

Design Change. Design Change of common part. 0.2 42 Change PL1202.PL1203 to SH000011H00 2013/11/29 DVT
7

fi
(S COIL .22UH +-20% 24A 7X7X4 MOLDING).

Design Change. Design Change of Delay Time. 0.2 42 Change PR1201 to SD028000080(S RES 1/16W 0 +-5% 0402). 2013/11/29 DVT
8 Change PC1201 to non-pop.

a
Design Change. Design Change of EC Type Application. 0.2 35 Add PD401 SCS00000Z00(S SCH DIO RB751V-40 SOD-323). 2013/11/29 DVT
9

in
Design Change. Design Change of Circuit Application. 0.2 42 Add PR1250 SD034100480(S RES 1/16W 1M +-1% 0402). 2013/11/29 DVT
10
B

11 Design Change. Design Change of Delay Time.h 0.2 42 Change PR1201 to SD028000080(S RES 1/16W 0 +-5% 0402).
Change PC1201 to SE071330J80(S CER CAP 33P 50V J NPO 0402)
2013/12/16 DVT
B
.c
Design Change. Design Change of Circuit Application. 0.2 33 Delete PR223.(remove HW hysteresis) 2013/12/16 DVT
12
w

Design Change. Design Change of Circuit Application. 0.2 42 Change PR1250 to non-pop. 2013/12/16 DVT
13

Design Change. Design Change of Circuit Application. 0.2 34 Change PQ303,PQ304 to SB000010A00(S TR AON7506 1N DFN). 2013/12/19 DVT
w

14

Design Change. Design Change of Circuit Application. 0.2 33 Add PL202 SM01000C000 2013/12/19 DVT
15
w

A (S SUPPRE_ TAI-TECH HCB2012KF-121T50 0805) A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 44 of 45
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 2 of 2 for PWR

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

16 Design Change. Design Change of Circuit Application. 0.2 33 Change PR211 to SD028000080(S RES 1/16W 0 +-5% 0402). 2013/12/25 DVT

D D

17 Design Change. Design Change of Circuit Application. 0.2 35 Change PC426 to pop. 2013/12/25 DVT

m
18 Design Change. Design Change of Circuit Application. 0.2 33 Change PR216 to SD034162280(S RES 1/16W 16.2K +1% 0402). 2013/12/25 DVT

19 Design Change. Design Change of Circuit Application. 0.2 33 Change PR216 to SD034169280(S RES 1/16W 16.9K +-1% 0402). 2014/01/02 DVT

o
20 Design Change. Design Change of Circuit Application. 0.2 33 Change PR202 to SD034100280(S RES 1/16W 10K +-1% 0402). 2014/01/02 DVT

.c
21 Design Change. Design Change of Circuit Application. 0.3 37.38. Change PR813,PR601,PR706,PR702,PR1004 2014/02/07 PVT
39.41. to SD028000080(S RES 1/16W 0 +-5% 0402).

x
C C
22 Design Change. Design Change of Circuit Application. 0.3 35 Remove PD401. 2014/02/07 PVT
Add @PR410 SD028000080(S RES 1/16W 0 +-5% 0402).

fi
a
in
B

h B
.c
w
w
w

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/03/27 Deciphered Date 2016/03/27 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_PIR
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, March 27, 2014 Sheet 45 of 45
5 4 3 2 1