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– Consistent Encounter-integrated
and standalone use model improves
productivity
Vector profiling
Encounter Power System includes
Figure 2: Global Power Debug
multiple vector profiling options to help
designers study VCD profiles textually and
graphically. Activity-based vector profiling
• Embedded design sanity checks such as • Integrated full-featured waveform
enables fast identification of high activity
completeness of LEF library data, timing viewer enables study of dynamic power
regions of VCDs. A fast vector power-
library data, physical and logical netlist and IR drop waveforms, with composite
profiling option calculates switching
annotation, and SPEF annotation waveform creation capabilities across
power of the design over time. The
design hierarchies and clock domains
• Fast structural power grid verification to accurate vector power-profiling option
identify missing vias and disconnected • Embedded Encounter layout viewer allows full power estimation of a VCD,
power pins with ability to cross-probe power and IR with activity propagation capabilities for
drop information non-annotated nodes.
• Access to the Encounter Timing System
signoff timing engine, enabling fast • Instance-based effective resistance plots
timing database queries for slews and with automatic least-resistive path
arrival times highlighting
Powerful GUI
• Command console with full Tcl support,
command completion, history, and Effective Resistance Plots
context highlighting highlighting weak connections
• Script editor to evaluate scripts with
ability to crosslink and expand Tcl
procedures
Automatic least resistive
Easy debugging
path highlighting
• Global Power Debug for analyzing
power consumption at different levels
of hierarchy, cell type, power net,
power domain, clock domain, etc., with
pie charts and histograms
Comprehensive IR drop
analysis solution
Encounter Power System uses Power
Grid Views (PGVs) as the building blocks
for hierarchical power grid analysis. The
Figure 4: HTML reports VoltageStorm family of products, such
as VoltageStorm Transistor and Virtuoso®
Automatic de-coupling information to Encounter Timing System, Analog VoltageStorm Option, analyze IR
capacitance optimization which calculates the impact of IR drop drop across custom-digital and analog/
on delay- and signal integrity-generated mixed-signal blocks accordingly. After this
Encounter Power System can calculate
noise. Encounter Power System can also analysis, both products create PGVs for
and recommend the amount of additional
generate dynamic IR drop and ground- use in Encounter Power System during
de-coupling capacitance necessary to
bounce waveforms for critical paths, full-chip static and dynamic runs. This
limit the dynamic IR drop to user-specified
allowing Encounter Timing System to allows study of IR drop across the entire
limits. This recommended additional
accurately trace and analyze such paths. chip, taking into account digital, custom
de-coupling capacitance can then drive an
automated optimization flow throughout block, and analog domains’ power grid
the Encounter Platform, where filler Analysis of IR drop-induced interactions.
cells are swapped with de-coupling delay variability on clock
capacitance cells. For low-power designs, and data networks Thermal and statistical
this flow can be used to remove extra The delay variation introduced by analysis
de-coupling capacitance cells in the instantaneous rail voltage changes on the Designed for advanced nodes, Encounter
design, improving leakage and yield. clock network can cause set-up and hold Power System allows designers advanced
violations in a design. The different delays analysis features such as thermal and
Package/die co-design seen on the clock and data networks statistical leakage power analysis (SLPA).
Encounter Power System integration with could introduce further set-up and hold Worst-case leakage has a very low
Allegro Package Designer enables easy violations. By monitoring the effective probability of occurring across the entire
hand-off of package and die models. operating voltage of the clock and data chip, and leakage distributions have long
Encounter Power System enables chip network elements, Encounter Power tails that make worst-corner analysis very
designers to create an abstract parasitics System enables Encounter Timing System pessimistic. Using SLPA, designers can
and dynamic current profile of the die for to more accurately analyze clock jitter, capture a more realistic picture of their
package designers. It also takes in 2 or skew, and delay variability across clock design’s leakage power distribution. SLPA
n-port package models to enable accurate and data networks. This analysis allows accounts for global, within-the-die, and
IR drop analysis, taking into account the Encounter Timing System to identify random variation. It enables designers to
package effects. problematic clock network elements spend less time fixing leakage problems
and to create and run a complete jitter- that are very unlikely to occur. Thermal
sensitized Spice trace. analysis allows users to study the impact
Analysis of IR drop impact on
of power on temperature variations across
timing and signal integrity
Power-switch optimization the die, which in turn impact leakage and
Encounter Power System calculates power consumption, and hence IR drop. It
Today, many low-power designs include
instance operating voltages based on also helps designers ensure proper cooling
switched blocks through the use of power
the switching windows associated with of the die to avoid thermal runaways.
switches. These blocks are only turned
each instance. It then provides this
on when needed, saving leakage power
– Timing libraries
SPEF GDS Spice
– Verilog Subckts
– SDC
– Package model
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20718 08/08 MK/MVC/CS/PDF