Departmental Exam 13.

The Boolean expression X + 0 = X is an example

COE117 - LOGIC CIRCUIT & SWITCHING THEORY 1 of which Law/Theorem?
4TH Qtr. AY 2015 – 2016 A. Null C. Absorption
NOTES: B. Identity D. Idempotent
Any form of cheating is punishable with a grade of 5.
14. The Boolean expression (X)(0) = 0 is an example
No calculators, listening and mobile devices allowed. of which Law/Theorem?
Keep them in your bag. A. Null C. Absorption
B. Identity D. Idempotent
Write all answers in CAPITAL LETTERS ONLY. 15. The Boolean expression X + 1 = 1 is an example of
which Law/Theorem?
NO OVERLAPPING of answers. A. Null C. Absorption
B. Identity D. Idempotent
No Student ID, No EXAM
For nos. 16 – 17, refer to the given minterm expansion
1. What is the binary equivalent of 3276810 ? below.
A. 1000000000000002 C. 11111111111111112
F(A,B,C,D) = m(2,6,11,13)
B. 1111111111111112 D. none of the above
D(A,B,C,D ) = m(1,5,7,9,10,15)
2. What is the decimal equivalent of 0.101012 ?
A. 0.78125 C. 0.65625 16. Simplify the given Boolean function F together with
B. 0.90625 D. 0.71825 the don’t care condition D in sum of products.
A. AD’ + AC’D C. AD + A’CD’
3. Convert the hexadecimal 0.7A3D to decimal B. A’D + A’C’D D. none of these
accurate to 5 digits.
A. 0.4775010 C. 0.4775210 17. Simplify the given Boolean function F together with
B. 0.4774910 D. none of these the don’t care condition D in product of sums.
A. (C’ + D’) (A + D’) (A’ + D’)
4. Convert 901610 to base 18. B. (C + D) (A’ + D) (A + D’)
A. 19141618 C. F8CH18 C. (C’ + D) (A’ + D’) (A’ + D’)
B. 19EG18 D. none of these D. none of the above

5. What is the equivalent of 3H9520 in base 7 ? 18. Find the simplified form of the function
A. 157123 C. 156223 ((AB)+A’C) (BA’+AC’+AC’+BC’) + (BA’+AC’)
B. 155112 D. none of these (AC’+BC’)
A. C(A+B) C. 1
6. Which of the following is the gray code equivalent of B. AC’+BA’ D. AB’ + AC’
the BCD number 1001 0111 0110?
For numbers 19 – 20, refer to the truth table below:
A. 1101 0100 0101 C. 1101 0101 0101
B. 1100 0100 0101 D. 1001 0101 0101 Inputs Outputs
L D M X Y
7. 10010011 is a signed binary number in 2’s 0 0 0 0 0
complement format. What decimal number does this 0 0 1 0 1
represent? 0 1 0 0 1
A. - 147 C. - 109 0 1 1 1 0
B. + 147 D. + 109 1 0 0 0 1
1 0 1 1 0
8. Given two signed BCD numbers. When one BCD 1 1 0 1 0
number was subtracted from the other BCD number, 1 1 1 1 0
the result was 100110010111BCD. What decimal
number does the result represent? 19. Which of the following is equal to X?
A. + 2455 C. - 97 A. L’D’ + L’M’ + D’M’
B. - 2455 D. none of these
B. L  D  M
9. What signed binary number in the 2’s complement C. LD + LM + DM
format does the result in Prob. 8 represent? D. LDM + L’DM’ +LD’M’
A. 000110010111 C. 10011111
B. 100110010111 D. none of these 20. Which of the following is equal to X AND Y?
A. LDM
10. The Boolean expression (X)(X’) = 0 is an example B. L+D+M
of which Law/Theorem? C. L  D  M
A. Involution C. Dominance D. 0
B. Null D. none of these
21. Use K-map to find the minimum sum of products
11. The Boolean expression X(X + Y) = X is an expression for the following functions: (A,B,C,D,E)
example of which Law/Theorem? =∑ (1,3,5,7,8,12,15,18,19,22,23,24,27,28,31)
A. Associative C. De Morgan’s A. ABE + CD’E + AB’D+ADE+BD’E’
B. Absorption D. Simplification B. A’B’E + CDE + AB’D+ADE+BD’E’
C. ABE + CD’E + AB’D+A’DE+BD’E’
12. The Boolean expression (X)(X) = X is an example D. A’B’E + CD’E + AB’D+ADE+BD’E’
of which Law/Theorem?
A. Null C. Absorption
B. Identity D. Idempotent

“The more I live, the more I learn. The more I learn, the more I realize, the less I know.”
- Michel Legrand
 22. Use the K-map to find the minimum sum of 32. How many non-essential prime implicants will there
products of F(A,B,C,D) = ∏ (0,2,4,6,8,10,12,14) be?
A. F = D’ C. F = A’D A. 3 C. 1
B. F = D D. F = ABCD B. 2 D. 0

23. Find the simplified form of the function 33. If the expression of output W is expressed in POS,
((AB)+A’C) (BA’+AC’+AC’+BC’) + (BA’+AC’) what will it be?
(AC’+BC’) A. (A + B) (B’ + C + D)
A. 1 B. A’C’ + A’B’ B. (A + B) (A + C + D)
B. AB’+AC’ D. AC’ + BA’ C. (BC + D) (A + C’ + D)
D. (C + A’D) (B + C + D’)
24. You are to design a combinational circuit with a
mode input P. If P=0 the circuit should act as a 4-bit
adder and if P=1 the circuit should act as a 4-bit 34. What will be the Boolean expression for output X in
subtractor. 7486 - Quad 2 input XOR gate POS?
(30Php/IC), 7408 - Quad 2 input AND gate A. (C + D) (B’ + D’) (B’ + C’)
(25Php/IC), and 7483 - 4-bit adder (35Php/IC) are B. (B + D’) (A’ + C’) (B + D)
the only available ICs. Find the least probable cost C. (A + C’) (B’ + D’) (B + C)
for the design. D. (C’ + D’) (C’ + D) (A’ + B’)
A. 90.00 Php C. 65.00 Php
B. 85.00 Php D. 55.00 Php 35. How many essential prime implicants will there be if
25. A multiplexer with a 8-bit SELECT signal (S7, S6, output X is expressed in SOP?
S5, S4, S3, S2, S1, and S0) can accommodate a A. 0
maximum of how many input signals? B. 1
A. 8 C. 256 C. 2
B. 64 D. 512 D. 3

26. A combinational logic circuit with four inputs

(a,b,c,d) and one output F has the following For nos.36 - 37. The transition table of a sequential circuit is
specifications: shown below (NOTE: X = input control):
The output is low if b = c = d = 0 or a=c=d=1, the Present Next State Output
output is high if a=0 and c=1 provided that d=0 or State X=0 X=1 X=0 X=1
b=0. The output is don't care for the other A F D 0 1
combinations of the input variables. B B C 1 1
C B A 0 1
A. F = a’b’cd’ C. F = a’c
D H D 0 1
B. F = a’cd’ D. None of these
E B C 1 1
For nos. 27 – 28. Design a combinational circuit with two F C C 0 0
inputs (A & B) and four outputs. The output (w, x, y, z) G E A 0 1
represents the square of the designated value. H G G 0 0
27. Find the Boolean expression of the output y. 36. What are the states that will be eliminated if state
A. 0 C. AB’ reduction will be performed?
B. A’B D. none of these A. D,E,G,H C. D,E,C,H
B. D,F,C,H D. D,F,G,H
28. Find the Boolean expression of the output w.
A. 0 C. AB 37. How many flip-flops are needed to implement the
B. 1 D. none of these reduced state table?
A. 1 C. 4
29. How many 3-to-8 decoder is needed to implement a
B. 2 D. 8
6-to-64 Decoder?
A. 3 B. 6 C. 9 D. 11
38. The master-slave is a pulse-triggered flip-flop and is
30. What is the minimum number of 2-input, 4-bit indicated as such with a right angle symbol called a
multiplexers needed if you are going to use these as A. postponed output C. dynamic input
the building block in constructing a 16-input, 4-bit indicator indicator
multiplexer? B. static pulse indicator D. none of these
A. 15
B. 18 39. Which of the following is not true about T flip-flop?
C. 20 A. at T=0, Qnext = Qpresent
D. 24 B. at T=1, Qnext = T ’
C. at T=1, Qnext = Qpresent’
31. In designing (most economical) a logic circuit in D. all are true
BCD Code (ABCD) to Excess-3 Code (WXYZ),
40. This element of the ASM chart is connected by
what will be the Boolean expression of output W in
directed edges indicating the sequential precedence
SOP?
and evolution of the states as the machine operates.
A. A + B’C + BD’ C. A + BC + BD
A. decision box C. conditional box
B. A’ + BC + BD’ D. B + AD + CD
B. state box D. all of these

“The more I live, the more I learn. The more I learn, the more I realize, the less I know.”
- Michel Legrand
 41. This element of the ASM chart is connected by For nos.47 - 50. The initial states of registers A, B, and C in
directed edges indicating the sequential precedence Figure 69 at time t = 0 are shown below.
and evolution of the states as the machine operates.

A. decision box C. conditional box

B. state box D. all of these

For nos.42 - 43. Given the state diagram below:

0/1 0/0

00 01
1/0
1/0 0/0

10 11 1/1
0/1 1/1

NOTE:
X = input control
QA and QB = present state of the flip-flops

42. If the circuit is to be constructed using D flip-flops, Figure 69

what will be the input equation of the signal in the SI – serial input FA = full adder circuit
least significant flip-flop? SO – serial output
A. QAQB + X C. QAQB’ + X
B. X’QB + XQA D. XQB + X’QA 47. What will be the content of Register B after the
arrival of the 7th initiating clock?
43. What is the input equation of the signal in the most A. 1 1 0 1 C. 0 1 0 1
significant flip-flop? B. 1 0 1 0 D. 1 1 1 0
A. QAQB + X C. QAQB’ + X
B. X’QB + XQA D. XQB + X’QA 48. What will be the content of Register A after the
arrival of the 4th initiating clock?
For nos.44 - 46. The initial state of the circuit in Figure 100 at A. 1 0 1 1 C. 0 1 0 1
time t = 0 is 0 0 0 1 (DCBA). B. 0 1 1 0 D. 1 0 1 0

49. What will be the value of XYZ after the arrival of the
6th initiating clock?
A. 0 1 1 C. 1 1 0
B. 1 0 1 D. 0 0 1

50. What will be the value of SCDQ after the arrival of

the 8th initiating clock?
A. 0 1 1 1 C. 0 1 0 1
B. 1 1 0 0 D. 1 0 1 0

44. What will be the state of the state of the flip-flops

(DCBA) at time t = 8?
A. 1 0 0 1 C. 1 0 1 1
B. 1 0 0 0 D. 1 0 1 0

45. What will be the state of the state of the flip-flops

(DCBA) at time t = 10?
A. 1 0 0 1 C. 1 0 1 1
B. 1 0 0 0 D. 1 0 1 0

46. What will be the state of the state of the flip-flops

(DCBA) at time t = 12?
A. 1 1 0 0 C. 1 1 1 0
B. 1 1 0 1 D. 1 1 1 1

“The more I live, the more I learn. The more I learn, the more I realize, the less I know.”
- Michel Legrand