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IRFP240

Data Sheet January 2002

20A, 200V, 0.180 Ohm, N-Channel Power Features


MOSFET • 20A, 200V
This N-Channel enhancement mode silicon gate power field
• rDS(ON) = 0.180Ω
effect transistor is an advanced power MOSFET designed,
tested, and guaranteed to withstand a specified level of • Single Pulse Avalanche Energy Rated
energy in the breakdown avalanche mode of operation. All of • SOA is Power Dissipation Limited
these power MOSFETs are designed for applications such
as switching regulators, switching convertors, motor drivers, • Nanosecond Switching Speeds
relay drivers, and drivers for high power bipolar switching • Linear Transfer Characteristics
transistors requiring high speed and low gate drive power.
• High Input Impedance
These types can be operated directly from integrated
circuits. • Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Formerly developmental type TA17422.
Components to PC Boards”

Ordering Information Symbol


PART NUMBER PACKAGE BRAND
D
IRFP240 TO-247 IRFP240

NOTE: When ordering, include the entire part number.


G

Packaging
JEDEC STYLE TO-247

SOURCE
DRAIN
GATE

DRAIN
(FLANGE)

©2002 Fairchild Semiconductor Corporation IRFP240 Rev. B


IRFP240

Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified


IRFP240 UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS 200 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 200 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID 20 A
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 80 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD 150 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W/oC
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 510 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL 300 oC
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 260 oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. TJ = 25oC to 125oC.

Electrical Specifications TC = 25oC, Unless Otherwise Specified

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS


Drain to Source Breakdown Voltage BVDSS VGS = 0V, ID = 250µA (Figure 10) 200 - - V
Gate to Threshold Voltage VGS(TH) VGS = VDS , ID = 250µA 2.0 - 4.0 V
Zero-Gate Voltage Drain Current IDSS VDS = Rated BVDSS , VGS = 0V - - 25 µA
VDS = 0.8 x Rated BVDSS , VGS = 0V, TJ = 125oC - - 250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON)MAX , VGS = 11V (Figure 7) 20 - - A
Gate to Source Leakage IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) VGS = 10V, ID = 10A (Figures 8, 9) - 0.14 0.18 Ω
Forward Transconductance (Note 2) gfs VDS ≥ 10V, ID = 11A 6.7 11 - S
Turn-On Delay Time td(ON) VDD = 100V, ID ≈ 18A, RGS = 9.1Ω , VGS = 10V, - 14 21 ns
RL = 5.4Ω
Rise Time tr - 51 77 ns
MOSFET Switching Times are Essentially
Turn-Off Delay Time td(OFF) Independent of Operating Temperature - 45 68 ns
Fall Time tf - 36 54 ns
Total Gate Charge Qg(TOT) VGS = 10V, ID = 18A, VDS = 0.8 x Rated BVDSS, - 43 60 nC
(Gate to Source + Gate to Drain) IG(REF) = 1.5mA (Figure 14)
Gate Charge is Essentially Independent of
Gate to Source Charge Qgs - 10 - nC
Operating Temperature
Gate to Drain “Miller” Charge Qgd - 32 - nC
Input Capacitance CISS VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) - 1275 - pF
Output Capacitance COSS - 500 - pF
Reverse Transfer Capacitance CRSS - 160 - pF
Internal Drain Inductance LD Measured between the Modified MOSFET - 5.0 - nH
Contact Screw on Symbol Showing the
Header that is Closer to Internal Devices
Source and Gate Pins Inductances
and Center of Die D

Internal Source Inductance LS Measured from the LD - 12.5 - nH


Source Lead, 6mm
(0.25in) from Header to
G
Source Bonding Pad LS

S
Junction to Case RθJC - - 0.83 oC/W

Junction to Ambient RθJA Free Air Operation - - 30 oC/W

©2002 Fairchild Semiconductor Corporation IRFP240 Rev. B


IRFP240

Source to Drain Diode Specifications


PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET D - - 20 A
Symbol Showing the
Pulse Source to Drain Current (Note 3) ISDM - - 80 A
Integral Reverse P-N
Junction Diode
G

Source to Drain Diode Voltage (Note 2) VSD TJ = 25oC, ISD = 18A, VGS = 0V (Figure 13) - - 2.0 V
Reverse Recovery Time trr TJ = 25oC, ISD = 18A, dISD/dt = 100A/µs 120 250 530 ns
Reverse Recovered Charge QRR TJ = 25oC, ISD = 18A, dISD/dt = 100A/µs 1.3 2.6 5.6 µC
NOTES:
2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 50V, starting TJ = 25oC, L = 1.9mH, RGS = 50Ω , peak IAS = 20A.

Typical Performance Curves Unless Otherwise Specified

1.2 20
POWER DISSIPATION MULTIPLIER

1.0
16
ID, DRAIN CURRENT (A)

0.8
12

0.6
8
0.4

4
0.2

0 0
0 50 100 150 25 50 75 100 125 150
TC , CASE TEMPERATURE (oC) TC , CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE CASE TEMPERATURE

1
ZθJC, NORMALIZED TRANSIENT

0.5
THERMAL IMPEDANCE

0.2
0.1 0.1
0.05
PDM
0.02
0.01

10-2 t1
SINGLE PULSE
t2 t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
10-3 -5
10 10-4 10-3 10-2 0.1 1 10
t1, RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

©2002 Fairchild Semiconductor Corporation IRFP240 Rev. B


IRFP240

Typical Performance Curves Unless Otherwise Specified (Continued)

1000 30
OPERATION IN THIS VGS = 8V PULSE DURATION = 80µs
REGION IS LIMITED DUTY CYCLE = 0.5% MAX
BY rDS(ON) VGS = 10V VGS = 7V
24

ID , DRAIN CURRENT (A)


ID , DRAIN CURRENT (A)

100 10µs

18
100µs
10
1ms VGS = 6V
12
10ms
1
DC 6
TC = 25oC
TJ = MAX RATED VGS = 5V
SINGLE PULSE VGS = 4V
0.1 0
1 10 102 103 0 20 40 60 80 100
VDS , DRAIN TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS

30
PULSE DURATION = 80µs 100
VGS = 10V PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX VGS = 8V DUTY CYCLE = 0.5% MAX
24 VDS ≥ 50V
VGS = 7V
ID , DRAIN CURRENT (A)

ID , DRAIN CURRENT (A)

10
18

12
VGS = 6V TJ = 150oC TJ = 25oC
1

6
VGS = 5V

VGS = 4V
0 0.1
0 1 2 3 4 5 0 2 4 6 8 10
VDS , DRAIN TO SOURCE VOLTAGE (V) VGS , GATE TO SOURCE VOLTAGE (V)

FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS

3.0
1.5 PULSE DURATION = 80µs
PULSE DURATION = 2µs DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE

DUTY CYCLE = 0.5% MAX ID = 10A, VGS = 10V


2.4
rDS(ON) , DRAIN TO SOURCE

1.2
ON RESISTANCE
ON RESISTANCE (Ω)

1.8
0.9
VGS = 10V
1.2
0.6

0.6
0.3
VGS = 20V
0
0 -60 -40 -20 0 20 40 60 80 100 120 140 160
0 15 30 45 60 75
TJ, JUNCTION TEMPERATURE (oC)
ID , DRAIN CURRENT (A)

NOTE: Heating effect of 2µs pulse is minimal. FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE GATE RESISTANCE vs JUNCTION TEMPERATURE
VOLTAGE AND DRAIN CURRENT

©2002 Fairchild Semiconductor Corporation IRFP240 Rev. B


IRFP240

Typical Performance Curves Unless Otherwise Specified (Continued)

1.25 3000
ID = 250µA VGS = 0V, f = 1MHz
CISS = CGS + CGD
NORMALIZED DRAIN TO SOURCE

1.15 2400 CRSS = CGD


COSS ≈ CDS + CGD

C, CAPACITANCE (pF)
BREAKDOWN

1.05 1800 CISS

0.95 1200 COSS

0.85 600 CRSS

0.75 0
-60 -40 -20 0 20 40 60 80 100 120 140 160 1 2 5 10 20 50 100
TJ , JUNCTION TEMPERATURE (oC) VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
VOLTAGE vs JUNCTION TEMPERATURE

15 100
PULSE DURATION = 80µs
PULSE DURATION = 80µs
ISD , SOURCE TO DRAIN CURRENT (A)
DUTY CYCLE = 0.5% MAX
DUTY CYCLE = 0.5% MAX
gfs , TRANSCONDUCTANCE (S)

12
TJ = 25oC
10
9
TJ = 150oC

6 TJ = 150oC
1

3
TJ = 25oC

0 0.1
0 6 12 18 24 30 0 0.4 0.8 1.2 1.6 2.0
ID , DRAIN CURRENT (A) VSD , SOURCE TO DRAIN VOLTAGE (V)

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

20
ID = 18A
VGS , GATE TO SOURCE VOLTAGE (V)

16

VDS = 40V
12
VDS = 100V

VDS = 160V
8

0
0 12 24 36 48 60
Qg, GATE CHARGE (nC)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

©2002 Fairchild Semiconductor Corporation IRFP240 Rev. B


IRFP240

Test Circuits and Waveforms


VDS
BVDSS

tP
L VDS
IAS
VARY tP TO OBTAIN VDD
+
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS 0

0.01Ω tAV

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

tON tOFF

td(ON) td(OFF)

tr tf
VDS
RL 90% 90%

+
10% 10%
VDD 0
RG
-
90%
DUT
VGS 50% 50%
PULSE WIDTH
10%
0
VGS

FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

VDS
CURRENT (ISOLATED
REGULATOR SUPPLY) VDD

Qg(TOT)
VGS
SAME TYPE
Qgd
12V AS DUT
0.2µF 50kΩ Qgs
BATTERY
0.3µF

D VDS

G DUT 0

IG(REF) S IG(REF)
0
VDS
IG CURRENT ID CURRENT
SAMPLING SAMPLING 0
RESISTOR RESISTOR

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

©2002 Fairchild Semiconductor Corporation IRFP240 Rev. B


TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™ FAST  OPTOLOGIC™ SMART START™ VCX™
Bottomless™ FASTr™ OPTOPLANAR™ STAR*POWER™
CoolFET™ FRFET™ PACMAN™ Stealth™
CROSSVOLT™ GlobalOptoisolator™ POP™ SuperSOT™-3
DenseTrench™ GTO™ Power247™ SuperSOT™-6
DOME™ HiSeC™ PowerTrench  SuperSOT™-8
EcoSPARK™ ISOPLANAR™ QFET™ SyncFET™
E2CMOSTM LittleFET™ QS™ TinyLogic™
EnSignaTM MicroFET™ QT Optoelectronics™ TruTranslation™
FACT™ MicroPak™ Quiet Series™ UHC™
FACT Quiet Series™ MICROWIRE™ SILENT SWITCHER  UltraFET 
STAR*POWER is used under license
DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER


NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and


supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product


that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H4

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