PD -95727A

IRF8915PbF
HEXFET® Power MOSFET
Applications
Dual SO-8 MOSFET for POL
VDSS RDS(on) max ID
converters in desktop, servers, 20V 18.3m:@VGS = 10V 8.9A
graphics cards, game consoles
and set-top box
l Lead-Free
1 8
S1 D1
2 7
G1 D1

3 6
S2 D2
Benefits
4 5
G2 D2
l Ultra-Low Gate Impedance
l Very Low RDS(on) Top View SO-8
l Fully Characterized Avalanche Voltage
and Current

Absolute Maximum Ratings

Parameter Max. Units
VDS Drain-to-Source Voltage 20 V
VGS Gate-to-Source Voltage ± 20
ID @ TA = 25°C Continuous Drain Current, VGS @ 10V 8.9
ID @ TA = 70°C Continuous Drain Current, VGS @ 10V 7.1 A
IDM Pulsed Drain Currentc 71
PD @TA = 25°C Power Dissipation 2.0 W
PD @TA = 70°C Power Dissipation 1.3
Linear Derating Factor 0.016 W/°C
TJ Operating Junction and -55 to + 150 °C
TSTG Storage Temperature Range

Thermal Resistance
Parameter Typ. Max. Units
RθJL Junction-to-Drain Lead ––– 42 °C/W
RθJA Junction-to-Ambient f ––– 62.5

Notes  through … are on page 10

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Static @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
BVDSS Drain-to-Source Breakdown Voltage 20 ––– ––– V VGS = 0V, ID = 250µA
∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.015 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 14.6 18.3 mΩ VGS = 10V, ID = 8.9A e
––– 21.6 27 VGS = 4.5V, ID = 7.1A e
VGS(th) Gate Threshold Voltage 1.7 ––– 2.5 V VDS = VGS, ID = 250µA
∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -4.8 ––– mV/°C
IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA VDS = 16V, VGS = 0V
––– ––– 150 VDS = 16V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
gfs Forward Transconductance 12 ––– ––– S VDS = 10V, ID = 7.1A
Qg Total Gate Charge ––– 4.9 7.4
Qgs1 Pre-Vth Gate-to-Source Charge ––– 1.8 ––– VDS = 10V
Qgs2 Post-Vth Gate-to-Source Charge ––– 0.61 ––– nC VGS = 4.5V
Qgd Gate-to-Drain Charge ––– 1.7 ––– ID = 7.1A
Qgodr Gate Charge Overdrive ––– 0.79 ––– See Fig. 6
Qsw Switch Charge (Qgs2 + Qgd) ––– 2.3 –––
Qoss Output Charge ––– 2.7 ––– nC VDS = 10V, VGS = 0V
td(on) Turn-On Delay Time ––– 6.0 ––– VDD = 4.5V, VGS = 4.5V
tr Rise Time ––– 12 ––– ns ID = 7.1A
td(off) Turn-Off Delay Time ––– 7.1 ––– Clamped Inductive Load
tf Fall Time ––– 3.6 –––
Ciss Input Capacitance ––– 540 ––– VGS = 0V
Coss Output Capacitance ––– 180 ––– pF VDS = 10V
Crss Reverse Transfer Capacitance ––– 91 ––– ƒ = 1.0MHz

Avalanche Characteristics
Parameter Typ. Max. Units
EAS Single Pulse Avalanche Energy d ––– 15 mJ
IAR Avalanche Current c ––– 7.1 A

Diode Characteristics
Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 2.5 MOSFET symbol D

(Body Diode) A showing the

ISM Pulsed Source Current ––– ––– 71 integral reverse G

(Body Diode)c p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.0 V TJ = 25°C, IS = 7.1A, VGS = 0V e
trr Reverse Recovery Time ––– 13 19 ns TJ = 25°C, IF = 7.1A, VDD = 10V
Qrr Reverse Recovery Charge ––– 3.5 5.2 nC di/dt = 100A/µs e

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 IRF8915PbF
100 100
VGS VGS
TOP 10V TOP 10V
8.0V 8.0V
5.5V 5.5V
10
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

4.5V 4.5V
3.5V 3.5V
3.0V 3.0V
2.8V 10 2.8V
BOTTOM 2.5V BOTTOM 2.5V
1

0.1
1
2.5V
2.5V
0.01
≤60µs PULSE WIDTH ≤60µs PULSE WIDTH
Tj = 25°C Tj = 150°C
0.001 0.1
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

100 1.5
ID = 8.9A
RDS(on) , Drain-to-Source On Resistance

VGS = 10V
ID, Drain-to-Source Current (Α)

10
(Normalized)

T J = 150°C
1.0

T J = 25°C
1

VDS = 10V
≤60µs PULSE WIDTH
0.1 0.5
1 2 3 4 5 6 7 -60 -40 -20 0 20 40 60 80 100 120 140 160

T J , Junction Temperature (°C)

VGS, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

vs. Temperature
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 IRF8915PbF
10000 6.0
VGS = 0V, f = 1 MHZ
ID= 7.1A
C iss = C gs + C gd, C ds SHORTED
C rss = C gd 5.0 VDS= 16V

VGS, Gate-to-Source Voltage (V)

C oss = C ds + C gd VDS= 10V
C, Capacitance(pF)

1000 4.0
Ciss

3.0
Coss

100 Crss 2.0

1.0

10 0.0
1 10 100 0 1 2 3 4 5 6 7
VDS, Drain-to-Source Voltage (V) QG Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

100.00 1000

OPERATION IN THIS AREA

LIMITED BY R DS(on)
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)

100
TJ = 150°C
10.00

10
100µsec
T J = 25°C
1.00 1msec
1
10msec
T A = 25°C
Tj = 150°C
VGS = 0V Single Pulse
0.10 0.1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 1 10 100 1000
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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9 3.0

VGS(th) Gate threshold Voltage (V)

7 2.5
ID, Drain Current (A)

5
2.0
4 ID = 250µA

3
1.5
2

0 1.0
-75 -50 -25 0 25 50 75 100 125 150
25 50 75 100 125 150
T A , Ambient Temperature (°C) T J , Temperature ( °C )

Fig 9. Maximum Drain Current vs. Fig 10. Threshold Voltage vs. Temperature
Ambient Temperature

100

D = 0.50
Thermal Response ( Z thJA )

0.20
10
0.10
0.05 R1 R2 R3 R4 Ri (°C/W) τi (sec)
R1 R2 R3 R4
τJ τC 3.68799 0.000349
1 0.02 τJ τ
0.01 τ1 2.18971 0.005246
τ2 τ3 τ4
τ1 τ2 τ3 τ4 34.7298 0.470610
Ci= τi/Ri 21.8971 13.52000
Ci i/Ri
0.1 P DM

SINGLE PULSE t1

( THERMAL RESPONSE ) t2

Notes:
1. Duty factor D = t 1/ t 2
2. Peak T J = P DM x Z thJA +T A
0.01
1E-006 1E-005 0.0001 0.001 0.01 0.1 1 10 100

t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient

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40
RDS(on) , Drain-to -Source On Resistance (m Ω)

60
ID

EAS , Single Pulse Avalanche Energy (mJ)

ID = 8.9A
TOP 2.4A
35 50
2.9A
BOTTOM 7.1A
30 40

25 30
T J = 125°C

20 20
TJ = 25°C

15 10

10 0
1 2 3 4 5 6 7 8 9 10 25 50 75 100 125 150

VGS, Gate -to -Source Voltage (V) Starting T J , Junction Temperature (°C)

Fig 12. On-Resistance vs. Gate Voltage Fig 13. Maximum Avalanche Energy
vs. Drain Current
Current Regulator
Same Type as D.U.T.
V(BR)DSS
15V tp 50KΩ

12V .2µF
.3µF
VDS L DRIVER
+
V
D.U.T. - DS
RG D.U.T +
- VDD
IAS A
VGS
20V
VGS
tp 0.01Ω
I AS 3mA

IG ID
Fig 14. Unclamped Inductive Test Circuit Current Sampling Resistors
and Waveform
LD Fig 15. Gate Charge Test Circuit
VDS
VDS
+ 90%
V DD -

D.U.T
10%
VGS
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
td(on) tr td(off) tf

Fig 16. Switching Time Test Circuit Fig 17. Switching Time Waveforms
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 IRF8915PbF
Driver Gate Drive
P.W.
D.U.T P.W.
Period D=
Period
+

VGS=10V *
ƒ Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance
D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG V DD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• I SD controlled by Duty Factor "D" - Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

Id
Vds

Vgs

Vgs(th)

Qgs1 Qgs2 Qgd Qgodr

Fig 16. Gate Charge Waveform

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IRF8915PbF
Power MOSFET Selection for Non-Isolated DC/DC Converters

Control FET Synchronous FET

Special attention has been given to the power losses The power loss equation for Q2 is approximated
in the switching elements of the circuit - Q1 and Q2. by;
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the Ploss = Pconduction + Pdrive + Poutput
*
MOSFET, but these conduction losses are only about
one half of the total losses.

Power losses in the control switch Q1 are given

by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
Ploss = (Irms 2 × Rds(on ) )
⎛ Qgd ⎞ ⎛ Qgs 2 ⎞ portant characteristic; however, once again the im-
+⎜I × × Vin × f ⎟ + ⎜ I × × Vin × f ⎟
⎝ ig ⎠ ⎝ ig ⎠ it impacts three critical areas. Under light load the
+ (Qg × Vg × f )
⎛ Qoss
+ × Vin × f ⎞
⎝ 2 ⎠ are transfered to Q1 and increase the dissipation in
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitance’s Cds and Cdg when multiplied by
the power supply input buss voltage.
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( 2
Ploss = Irms × Rds(on) )
+ (Qg × Vg × f )
⎛Q ⎞
+ ⎜ oss × Vin × f + (Qrr × Vin × f )
⎝ 2 ⎠
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
portance of gate charge must not be overlooked since
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
 IRF8915PbF

SO-8 Package Outline(Mosfet & Fetky)

Dimensions are shown in milimeters (inches)
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SO-8 Part Marking Information

(;$03/(7+,6,6$1,5)026)(7
'$7(&2'(<::
3 ',6*1$7(6/($')5((
352'8&7237,21$/
< /$67',*,72)7+(<($5
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/2*2 3$57180%(5

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
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IRF8915PbF
SO-8 Tape and Reel
Dimensions are shown in millimeters (inches)
TERMINAL NUMBER 1

12.3 ( .484 )
11.7 ( .461 )

8.1 ( .318 )
7.9 ( .312 ) FEED DIRECTION

NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.

330.00
(12.992)
MAX.

14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Notes:
 Repetitive rating; pulse width limited by max. junction temperature.
‚ Starting TJ = 25°C, L = 0.59mH, RG = 25Ω, IAS = 7.1A.
ƒ Pulse width ≤ 400µs; duty cycle ≤ 2%.
„ When mounted on 1 inch square copper board.
… Rθ is measured at TJ of approximately 90°C.

Data and specifications subject to change without notice.

This product has been designed and qualified for the Consumer market.
Qualifications Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.07/2008
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