Memory Elements

• Combinational logic cannot remember

 Output logic values are function of inputs only
 Feedback is needed to be able to remember a logic value
• Memory elements are needed in most digital logic
circuits to hold (remember) logic values
• 2 basic types of memory elements
 Latches
• Level-sensitive to inputs
 Flip-flops
• Edge-triggered on active edge of clock

C. E. Stroud Latches & Flip-flops (10/12) 1

 Reset-Set (RS) Latch (NOR)
• The simplest memory element R Q
 Aka set-reset (SR) latch
• Cross-coupled NOR gates
 Level sensitive Q
S
 Active high inputs
• R (reset)
R S Q Q’ Function
• S (set)
• Only one input can be active 0 0 Q Q’ Storage
 To avoid undefined state 0 1 1 0 Set
 Outputs: Q and Q’ 1 0 0 1 Reset
• Q = current state of latch
1 1 0-? 0-? Undefined
C. E. Stroud Latches & Flip-flops (10/12) 2
 Reset-Set (RS) Latch (NAND)
• Dual of NOR RS latch R Q
• Cross-coupled NAND gates
 Level sensitive
 Active low inputs Q
S
• R (reset)
• S (set)
• Only one input can be active R S Q Q’ Function
 To avoid undefined state 0 0 1-? 1-? Undefined
 Outputs: Q and Q’ 0 1 0 1 Reset
• Q = current state of latch
1 0 1 0 Set
1 1 Q Q’ Storage
C. E. Stroud Latches & Flip-flops (10/12) 3
 Enabled Reset-Set (RS) Latch (NOR)
• Aka gated RS latch R
Q
 When enable E is inactive, RS latch
is forced into storage state
• R and S can do nothing
E
• AND gates plus NOR RS latch Q
 Level sensitive S
 Active high inputs
• E (enable) E R S Q Q’ Function
• R (reset)
• S (set)
0 X X Q Q’ Storage
• R and S cannot both be active when 1 0 0 Q Q’ Storage
E is active
 To avoid undefined state 1 0 1 1 0 Set
 Outputs: Q and Q’
1 1 0 0 1 Reset
• Q = current state of latch
1 1 1 0-? 0-? Undefined
C. E. Stroud Latches & Flip-flops (10/12) 4
Enabled Reset-Set (RS) Latch (NAND)
• Aka gated RS latch R
Q
 When enable E is inactive, RS latch
is forced into storage state
• R and S can do nothing
E
• OR gates plus NAND RS latch Q
 Level sensitive S
 Active low inputs
• E (enable) E R S Q Q’ Function
• R (reset)
• S (set)
1 X X Q Q’ Storage
• R and S cannot both be active when 0 0 0 1-? 1-? Undefined
E is active
 To avoid undefined state 0 0 1 0 1 Reset
 Outputs: Q and Q’
0 1 0 1 0 Set
• Q = current state of latch
0 1 1 Q Q’ Storage
C. E. Stroud Latches & Flip-flops (10/12) 5
 Enabled Data or Delay (D) Latch
D
Q
• Aka transparent D latch
 Overcomes undefined state E
• R & S never active at same time Q

• Inverter plus enabled RS latch

E D Q Q’ Function
 Level sensitive
0 X Q Q’ Storage
• Active high enable for NOR latch
1 0 0 1 Transparent
• Active low enable for NAND latch
1 1 1 0 Transparent
D
Q E D Q Q’ Function logic D Q
active
E 0 0 0 1 Transparent symbols high
E Q’
Q 0 1 1 0 Transparent D Q
1 X Q Q’ Storage active
low
C. E. Stroud Latches & Flip-flops (10/12)
E Q’ 6
 D Flip-Flop
D Q
D Q D Q
• Aka Master-Slave flip-flop active active
Clk low high Q’
• Two transparent D latches E E Q’
 Sensitive to opposite levels of Clock master slave
• One is always in storage and the other master transparent master storage
transparent
Clock slave storage slave transparent
• Edge-triggered
rising edge
 Data moves through on Clock transition
 Active-low latch followed by active-high D Q
D Q D Q
active active
• Rising edge-triggered high low
Clk Q’
 aka leading edge-triggered E E Q’
 Active-high latch followed by active-low
master slave
• Falling edge-triggered master transparent master storage
 aka trailing edge-triggered
Clock slave storage slave transparent
C. E. Stroud Latches & Flip-flops (10/12) falling edge 7
 D Flip-Flop
• Gate-level implementation
 No need for inverter in slave latch since master has Q & Q’
D active-low active-high
Q
Rising edge-triggered
Q D flip-flop

Clk active-high active-low

D
Q

Falling edge-triggered
D flip-flop Q

Clk

C. E. Stroud Latches & Flip-flops (10/12) 8

 Timing Considerations
• Set-up time (tsu) = minimum time data
(D) must be valid at input to flip-flop
prior to the active edge of the clock
• Hold time (th) = minimum time data
(D) must remain valid at input to flip-
D
flop after the active edge of the clock tsu th
• Clock-to-output delay (tco) = Clk
tco
maximum time before output data (Q)
is valid after the active edge of the Q
clock
C. E. Stroud Latches & Flip-flops (10/12) 9
 Timing Considerations
• Set-up & hold time violations in a
real circuit result in metastability
Flip-flop goes to intermediate logic
levels (Q = Q’)
D
Eventually resolves to an unknown tsu th
state Clk
tco
• Set-up & hold time violations in a
vector set for simulation referred Q
to as clock-data-races
Leads to invalid simulation results
& manufacturing testing problems
C. E. Stroud Latches & Flip-flops (10/12) 10
 What is the Clock?
• Typically a periodic signal (a sequence of
pulses) used to:
sample data, and
store the sampled data in memory elements
• Clock frequency = 1/period
tco time for tsu
fclk = 1/Tp
Pdel
Tp  tco + Pdel + tsu
• Pdel  Tp - tco - tsu
period
Tp time
1

0
C. E. Stroud Latches & Flip-flops (10/12) 11
 Serial Shift Register Example
• A series of D flip-flops whose outputs are connected
to the input of the next flip-flop
 serial-in, serial-out = data in on Din, data out on Qc
 serial-in, parallel-out = data in on Din, data out on Qa, Qb,
and Qc Din Qa Qb Qc

time Clk Timing diagram

Clk
Din
Qa
Qb
Qc
C. E. Stroud Latches & Flip-flops (10/12) 12
 Another Shift Register Example
• A series of multiplexers and D flip-flops whose outputs
are connected to the input of the next flip-flop
 parallel-in, parallel-out = data in on Da, Db, and Dc; data out
on Qa, Qb, and Qc (Shift/Load = 0)
 parallel-in, serial-out = data in on Da, Db, and Dc; data out
on Qc (Shift/Load = 0, then Shift/Load = 1)
 Serial-in, serial-out = data in on Din, data out on Qc
(Shift/Load = 1)
 Serial-in, parallel-out = data in on Din, data out on Qa, Qb,
and Qc (Shift/Load = 1) Da Db Dc
0 0 0
Din 1 1 1

Clk
Shift/Load Qa Qb Qc
C. E. Stroud Latches & Flip-flops (10/12) 13
 PSIM Architecture
Sequential Logic:
Program Memory (MEM)
Program Counter (PC)
Address Register (AR)
Data Register (DR)
Input Register (IN)
Output Register (OR)
Accumulator (AC)
ALU Carry Register (C)
Instruction Register (IR)
Timing Counter (TC)
Combinational Logic:
Control Logic
Arithmetic/Logic Unit (ALU)
Multiplexers 1&2 (MUX)
C. E. Stroud Latches & Flip-flops (10/12) 14
 Another Register Example
• A series of multiplexers and D flip-flops whose
outputs are connected to the input of the MUX
Register with active high Load
• Load = 1 & rising edge of clock: parallel-in, parallel-out =
data in on Da, Db, and Dc; data out on Qa, Qb, and Qc
• Otherwise: Holds data; data out remains on Qa, Qb, and Qc
Basic register design used in PSIM for:
• AR, DR, OR, IN (all 8-bits) and IR (4-bits)
Da Db Dc
0 0 0

1 1 1

Clk
Load
Qa Qb Qc
C. E. Stroud Latches & Flip-flops (10/12) 15
 Accumulator Register Example
• Accumulator in PSIM AC-C2
ACi
 Functions controlled DRi 0
by combinational AC-C1 DRi
1
logic design ACi
• Including holding data 2
Cin Sumi
when no operations 3
are specified
ACi adder Zi ACi

 Via feedback of ACi ACi

4

 Only need a flip-flop DRi 5

ACi
at output of MUX DRi 6
• AC register (8-bits) ACi
7
• C register (1-bit) DRi
 Similar to ACi 3
design shown here AC_C2-0
Clock
C. E. Stroud Latches & Flip-flops (10/12) 16
Random Access Memory (RAM)
• Assuming MEM from PSIM
 8-bit address => 256 words
• MADD DR(7-0)

8
 8-bit words 8 DIN
MADD(7-0) ADD
• Input data = 8-bits
 From DR MEM
• Output data = 8-bits WR-MEM WE
DOUT
 From MEM

8
 Active high write enable MEM(7-0)
• WR-MEM (to DR)

 When WR-MEM = 1, data

from DR is written into address
location specified by MADD
C. E. Stroud Latches & Flip-flops (10/12) 17
 RAM continued
• RAM consists of: DIN
Address decoder with 8

DI
enable W0
LD Word0

ADD(7-0)
• Produces active high DO

DECODE

8
ADD(7-0)
enables to registers 8 8
Registers with parallel DI

MUX
W255 DOUT
load WR
LD Word255
DO
8

• Stores data associated

8
with specified address
Read MUX
• Reads specified address
C. E. Stroud Latches & Flip-flops (10/12) 18
 RAM continued
DIN
• Word Registers with 8

DI
parallel load Wi
LD Word0
DO
8 D-latches with active high
8
enable WORDi
DI0 DI7

D Q D Q
D active active
Q LDi high high
E Q’ E Q’
E
Q DO0 DO7

C. E. Stroud Latches & Flip-flops (10/12) 19

 RAM continued Word0 8

MUX
DOUT
• Read MUX 8
Word255 8
8 256-to-1 MUXs
8
Functional equivalent ADD0’
ADD1’ ADD(7-0)
ADD2’

example
ADD3’
• Address decoder ADD4’
ADD5’

256 9-input AND gates ADD6’

ADD7’
Word0Bi

8 inverters DOUTi

ADD0’ ADD0
W0
ADD1’ ADD1
DECODE

ADD2 ADD2
ADD(7-0) ADD3 ADD3
ADD4’ W12
8 example ADD4
ADD5’ ADD5
W255 ADD6’ ADD6
WR ADD7’ ADD7
WR Word255Bi
C. E. Stroud Latches & Flip-flops (10/12) 20
 What is Sequential Logic?
• A collection of logic gates and flip-flops
 The logic values stored in the flip-flops establish the
current state of the sequential logic circuit
 The logic values at the inputs in conjunction with the
current state determines the next state of the sequential
logic circuit after the active edge of the clock
Primary Primary
Inputs Comb Outputs
Logic generalized architecture
for sequential logic circuits
Current Flip- Next also known as
State Flips State Huffman model

C. E. Stroud Latches & Flip-flops (10/12) 21

 Flip-Flop Information for
Sequential Logic Design
• Types of flip-flops • Each type has associated:
D (data) Characteristic equation
T (toggle) Characteristic table
SR (set-reset)  sometimes called state table
• Also known as RS
(reset-set) State diagram
JK (Jack Kilby) Excitation table
We will consider All provide same basic
only edge-triggered information but in slightly
flip-flops different forms
C. E. Stroud Latches & Flip-flops (10/12) 22
 State Diagrams & State Tables
• Describe complete operation of sequential logic circuit
 Vertices (nodes) represent states
 Edges represent state transitions on active edge of clock
based on primary input logic values
• State diagram & state tables provide exact same
information
 Diagram is graphical representation of same info as in state
table
• Given current state and primary input values we can
determine the next state after active edge of clock

C. E. Stroud Latches & Flip-flops (10/12) 23

 D Flip-Flop Specification
state diagram characteristic equation
1 Q+ = D
0 0 1 1
D Q
0 excitation table
Clk Q Q Q+ D
characteristic table 0 0 0
D Q+ logic diagram 0 1 1
0 0 1 0 0
1 1 1 1 1

C. E. Stroud Latches & Flip-flops (10/12) 24

 T Flip-Flop Specification
state diagram characteristic equation
1 Q+ = TQ’ + T’Q
0 =TQ
0 1 0 T Q

1 excitation table
Clk Q
Q Q+ T
characteristic table 0 0 0
logic diagram
T Q+ Mode 0 1 1
0 Q Storage 1 0 1
1 Q’ Toggle 1 1 0

C. E. Stroud Latches & Flip-flops (10/12) 25

 RS Flip-Flop Specification
state diagram
characteristic equation
10
Q+ = S + R’Q
0X 0 1 X0
R Q
01 S
input ordering = SR Q
Clk
characteristic table excitation table
S R Q+ Mode logic diagram Q Q+ SR
0 0 Q Storage 0 0 0X
0 1 0 Reset 0 1 10
1 0 1 Set 1 0 01
1 1 ? Indeterminant 1 1 X0

C. E. Stroud Latches & Flip-flops (10/12) 26

 JK Flip-Flop Specification
state diagram
characteristic equation
1X
Q+ = JQ’ + K’Q
0X 0 1 X0
J Q
X1 K
input ordering = JK Clk Q
characteristic table excitation table
J K Q+ Mode logic diagram Q Q+ JK
0 0 Q Storage 0 0 0X
0 1 0 Reset 0 1 1X
1 0 1 Set 1 0 X1
1 1 Q’ Toggle 1 1 X0

C. E. Stroud Latches & Flip-flops (10/12) 27

 Flip-Flop Initialization
• Preset (aka set) => Q+ = 1 Typical logic symbol
• Clear (aka reset) => Q+ = 0 with active high preset
and active low clear
• Some flip-flops have: Cannot determine sync Pre
 Both preset and clear (set and reset) or async from symbol
 A preset or a clear D Q
 Neither (JK & SR flops have set/reset functions)
Clk Q
• Preset and/or clear can be
 Active high or active low
 Synchronous => with respect to active edge of clock Clr
 Asynchronous => independent of clock edges
• Initialization important for:
 logic simulation to remove undefined logic values (2, 3, U, etc.)
 system operation to put system in a known state
C. E. Stroud Latches & Flip-flops (10/12) 28
 Synchronous vs. Asynchronous
Pre
• Synchronous =>
states of memory D Q
elements change only Example:
with respect to active assume sync preset Clk Q
edge of clock and async clear
• Asynchronous =>
states of memory Clr
elements can change Clk
without an active D
edge of clock
 Asynchronous designs Pre
often have timing Clr
problems
Q
C. E. Stroud Latches & Flip-flops (10/12) 29