1.

MOS: Device Operation and

Large Signal Model
Sedra & Smith (6th Ed): Sec. 5.1-5.3
Or Sedra & Smith (5th Ed): Sec. 4.1-4.3
ECE65 Lecture notes: Intro to MOS

ECE 102, Fall 2012, F. Najmabadi

Operational Basis of a Field-Effect Transistor (1)
 Transistors acts as valves or gate in which the “main”
current flowing through the transistor is controlled by
another “small” current or voltage.
 In a Field Effect Transistor, current flowing across the
semiconductor is controlled by an electric field
perpendicular to the current

Controlled
Controller part:
part, iD
vGS (or VOV )

F. Najmabadi, ECE102, Fall 2012 (22/22)

Operational Basis of a Field-Effect Transistor (2)

To see how an electric field can control the current flow,

consider the hypothetical semiconductor below:
(constructed similar to a parallel plate capacitor)

Electrical contact

Metal
Insulator
Dopent ions
P-type semiconductor
Holes
(majority carries)

F. Najmabadi, ECE102, Fall 2012 (3/22)

Operational Basis of a Field-Effect Transistor (3)

Depletion Region  If we apply a voltage v1 between electrodes, a

(no majority carrier)
charge Q = C v1 will appear on each capacitor
plate.
o The electric field is strongest at the interface with the
insulator and charge likes to accumulate there.
 Holes are pushed away from the insulator
interface forming a “depletion region”.
 Depth of depletion region increases with v1.
Inversion layer
(“channel”)  If we increase v1 above a threshold value (Vt),
the electric field is strong enough to “pull” free
electrons to the insulator interface. As the
holes are repelled in this region, a “channel” is
Depletion Region formed which contains electrons in the
(no majority carrier)
conduction band (“inversion layer”).
 Inversion layer is a “virtual” n-type material.
F. Najmabadi, ECE102, Fall 2012 (4/22)
Operational Basis of a Field-Effect Transistor (4)
 We apply a voltage across the p-type semiconductor:
(Assume current flows only in the n-type material,
ignore current flowing in the p-type semiconductor)

No inversion layer (v1 < Vt):
 No current will flow
F. Najmabadi, ECE102, Fall 2012 (5/22)
With inversion layer (v1 > Vt):
 A current will flow in the channel
 Current will be proportional to electron
charge in the channel or (v1 − Vt )
 Magnitude of Current i2 is controlled by
voltage v1 (a Transistor!)
Operational Basis of a Field-Effect Transistor (5)
 We need to eliminate currents flowing in the p-type, i.e.,
current flows only in the “channel” which is a virtual n-type.

 Make the terminals of n-type material (set up diodes between terminals & p-type “body”)
 Heavy doping of the n-type terminals provides a source of free electrons for the channel.
 Make insulator layer as thin as possible to increase the electric field.

 Body-source and body-drain junctions should always be in reverse bias for FET to work!
F. Najmabadi, ECE102, Fall 2012 (6/22)
 Channel length (L) is
the smallest feature on the chip surface
MOSFET “cartoons” for deriving
MOSFET (or MOS): Metal-oxide field effect transistor
MOSFET characteristics
NMOS: n-channel enhancement MOS

MOSFET implementation on a chip

F. Najmabadi, ECE102, Fall 2012 (7/22)

 NMOS i-v Characteristics (1)
 To ensure that body-source and body-drain junctions are reversed bias, we
assume that Body and Source are connected to each other and vDS ≥ 0.
o We will re-examine this assumption later

 Without a channel, no current flows (“Cut-off”).

 For vGS > Vtn, a channel is formed. The total
charge in the channel is
|Q| = CV = CoxWL (vGS -Vtn )
C = Cox W L
ε ox
Cox = : Capacitance per unit area
tox
tox : Thickness of insulator
ε ox : permitivity of insulator
ε ox = 3.9ε 0 = 3.45 ×10 −11 F/m (for SiO 2 )

F. Najmabadi, ECE102, Fall 2012 (8/22)

 NMOS i-v Characteristics (2)
 We now apply a small voltage vDS between drain and source.

 A channel is formed when vGS > Vtn

 Electrons (in the n-channel) move from source
to drain with a velocity:
vDS
vdrift = µ n | E | = µ n
L
 The resulting current is
dq dQ dx | Q | |Q|
iD = = × = × vdrift = µ n 2 vDS
dt dx dt L L
|Q| = CoxWL (vGS -Vtn )
W
iD = µ nCox (vGS − Vtn )vDS
L Assumes a uniform channel
depth which is correct for
vDS << vGS - Vtn
F. Najmabadi, ECE102, Fall 2012 (9/22)
 NMOS i-v Characteristics (3)
Overdrive Voltage: VOV = vGS –Vtn

 When VOV > 0 (vGS > Vtn ) and vDS << VOV
W
iD = µ nCox VOV vDS
L
v 1 W
iD = DS with = g DS = µ nCox VOV
rDS rDS L

MOS acts as a resistance

whose conductivity is
controlled by VOV (or vGS).

F. Najmabadi, ECE102, Fall 2012 (10/22)

 NMOS i-v Characteristics (4)
 When vDS is increased the channel becomes narrower near the drain
(local depth of the channel depends on the difference between VOV and
local voltage).

Q
iD = µ n v
2 DS
L
Q = CoxWL (Vov − 0.5vDS )

iD = µ nCox
W
L
[
VOV vDS − 0.5vDS
2
] Cross sectional area
of the channel

F. Najmabadi, ECE102, Fall 2012 (11/22)

 NMOS i-v Characteristics (5)

 When vDS = VOV , the channel

depth becomes zero at the drain
(Channel is “pinched off”).

W
L
2
[ W
] [
iD = µ nCox VOV vDS − 0.5vDS = µ nCox VOV VOV − 0.5VOV2
L
]
W 2
iD = 0.5µ nCox VOV
L

 When vDS is increased further, vDS > VOV , the location of channel pinch-
off remains close to the drain and iD remains approximately constant.

F. Najmabadi, ECE102, Fall 2012 (12/22)

 NMOS i-v Characteristics (6)
For a given vGS (or VOV)

F. Najmabadi, ECE102, Fall 2012 (13/22)

 NMOS i-v Characteristics Plot (1)
 NMOS i-v characteristics iD = f (vGS , vDS ) is a surface

F. Najmabadi, ECE102, Fall 2012 (14/22) * Plot for Vt,n = 1 V and µnCox (W/L) = 2.0 mA/V2
 NMOS i-v Characteristics Plot (2)

Looking at surface with vGS axis

pointing out of the paper*

*Note: surface is truncated (i.e., vGS < 5 V)

F. Najmabadi, ECE102, Fall 2012 (15/22)

 NMOS i-v Characteristics Plot (3)

F. Najmabadi, ECE102, Fall 2012 (16/22)

 Channel-Length Modulation

 The expression we derived for saturation region

assumed that the pinch-off point remains at the
drain and thus iD remains constant.
 In reality, the pinch-off point moves “slightly”
away from the drain: Channel-length Modulation

VOV (1 + λ vDS )
W 2
iD = 0.5µ nCox
L
λ = 1 / VA

F. Najmabadi, ECE102, Fall 2012 (17/22)

 Body Effect

 Recall that Drain-Body and Source-Body diodes should be reversed biased.

o We assumed that Source is connected to the body (vSB = 0) and vDS = vDB >
0
 In a chip (same body for all NMOS), it is impossible to connect all sources
to the body (all NMOS sources are connected together.
 Thus, the body (for NMOS) is connected to the largest negative voltage
(negative terminal of the power supply).
 Doing so, changes the threshold voltage (called “Body Effect”)
Vtn = Vtn ,0 + γ ( | 2φ F + VSB | − | 2φF | )

 In this course we will ignore body effect as well as other second-

order effects such as velocity saturation.

F. Najmabadi, ECE102, Fall 2012 (18/22)

 P-channel Enhancement MOS (PMOS)
 A PMOS can be constructed analogous to an NMOS: (n-type body), heavily
doped p-type source and drain.
 A virtual “p-type” channel is formed in a P-MOS (holes are carriers in the
channel) by applying a negative vGS.
 i-v characteristic equations of a PMOS is similar to the NMOS with the
exception:
o Voltages are negative (we switch the terminals to have positive voltages: use
vSG instead of vGS ).
o Use mobility of holes, µp , instead of µn in the expression for iD

F. Najmabadi, ECE102, Fall 2012 (19/22)

 MOS Circuit symbols and conventions

NMOS PMOS

F. Najmabadi, ECE102, Fall 2012 (20/22)

 MOS i-v Characteristics Equations
NMOS (VOV = vGS – Vtn)
Cut - Off : VOV ≤ 0 iD = 0

Triode : VOV ≥ 0 and vDS ≤ VOV iD = 0.5µ nCox

W
L
[
2VOV vDS − vDS
2
]
Saturation : VOV ≥ 0 and vDS ≥ VOV iD = 0.5µ nCox
W 2
L
[
VOV 1 + λvDS ]

PMOS (VOV = vSG – |Vt,p|)*

Cut - Off : VOV ≤ 0 iD = 0

Triode : VOV ≥ 0 and vSD ≤ VOV iD = 0.5µ p Cox

W
L
[2VOV vSD − vSD
2
]
Saturation : VOV ≥ 0 and vSD ≥ VOV iD = 0.5µ p Cox
W 2
L
[
VOV 1 + λvSD ]
*Note: S&S defines |VOV |= vSG – |Vtp| and uses |VOV |in the PMOS formulas.
F. Najmabadi, ECE102, Fall 2012 (21/22)
 To Solve MOS Circuit:
(with Large Signal Model)
1. Hypothesis: assume one of the modes of operation for the MOSFET

2. Solve: Use the equations for the selected mode to solve the circuit

3. Check: at the end perform the check for the selected mode to
verify the hypothesis

4. Redo: if the hypothesis check fails, try another hypothesis and start
over

Controller part: Controlled part:

Circuit connected to GS iD & vDS are set by
sets vGS (or VOV ) transistor state (&
outside circuit)
F. Najmabadi, ECE102, Fall 2012 (22/22)