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A perfect clock is defined as perfectly periodic signal that is simultaneous triggered at var-
ious memory elements on the chip. However, due to a variety of process and environmen-
tal variations, clocks are not ideal. To illustrate the sources of skew and jitter, consider the
simplistic view of clock generation and distribution as shown in Figure.Typically, a
high frequency clock is either provided from off chip or generated on-chip. From a central
point, the clock is distributed using multiple matched paths to low-level memory ele-
ment.s registers. In this picture, two paths are shown.The clock paths include wiring and
the associated distributed buffers required to drive interconnects and loads.