2017-18

B. Tech. (Electronics) V-Semester

VLSI Design & Technology
EL-315

Assignment-I

In the given data_path_1 and data_path_2, A, B C, D, E, F, and S are 4-bit

registers. The block with ‘+’ represents a 4-bit adder block having a delay of 2ns
each. Assume that the wire delay, setup time, clk→q delay and hold time are
negligibly small.
Determine the maximum clock frequency that can be used for the given data
paths.
Write Verilog code for both the data paths using hierarchical modeling
concept.
Verify the constraint on maximum clk frequency through simulation.

Note: Your report shall include the following

1. Verilog code for the leaf cells along with their simulation waveforms
2. Verilog code for the top module (i.e. data_path_1 and data_path_2) and stimulus along with the simulation
waveforms
3. A discussion on the use of registers ‘E’ and ‘F’ in data_path_2.
 MAXIMUM CLOCK FREQUENCY.

In the given data path, any path can be taken as critical path.
We have to ignore setup time and clock to q frequency.
Therefore, delay is of the 2 adder blocks in a data path.
I.e. 2+2 = 4ns.
Since the delay is of 4ns, the frequency is 0.25GHz.
If the time period of the clock is kept less than 4ns,
The output will not be optimum.

USE OF REGISTERS E AND F IN DATA PATH 2

In data path 2, one advantage of using E and F registers is to keep the intermediate
computational results within the same clock cycles.
In simpler words, we can know the sum of our individual adder blocks.
In the case where we are not using the register, we cannot see the sum of individual adder
blocks.
Rather, only the final output are known.
Also, since the clock to Q delay and setup times are negligible,
There would not b and added delay due to it.
Therefore, data path 2 is better design in this case.
VERILOG CODE FOR LEAF CELLS AND TESTBENCH:

1) 4 BIT REGISTER
module register (out, data, clk);
output reg [3:0]out;
input [3:0]data;
input clk;
always @ (posedge clk)
assign out = data;
endmodule
4 BIT REGISTER TESTBENCH

module stimulus_reg;
reg clk;
reg [3:0]data;
wire [3:0]out;
register r(out, data, clk);
initial
clk = 1'b1;
always
#5 clk= ~clk;
initial
begin
data = 4'b0000;
#10 data = 4'b1000;
#10 data = 4'b1010;
#10 data = 4'b1100;
#10 data = 4'b1011;
#10 $finish;
end
endmodule
 2) 1 BIT FULL ADDER

module FA(s, co, a, b, ci);

output s, co;
input a, b, ci;
wire m, n, p;
xor g1 (m, a, b);
xor g2 (s, m, ci);
and g3(n, m, ci);
and g4(p, a, b);
or #2 g5(co, n, p);
endmodule

1 BIT FULL ADDER TESTBENCH

module stimulus_FA;
reg a, b, ci;
wire co, s;
FA F1(s, co, a, b, ci);
initial
begin
a=1'b0; b=1'b0; ci=0;
#10 a=1'b0; b=1'b0;
#10 a=1'b0; b=1'b1;
#10 a=1'b1; b=1'b0;
#10 a=1'b1; b=1'b1;
#10 $finish;
end
endmodule
 3) 4 BIT FULL ADDER

module FA4 (s, co, a, b, ci);

input [3:0]a, b;
input ci;
output [3:0]s;
output co;
wire [2:0]c;
FA F1 (s[0], c[0], a[0], b[0], ci);
FA F2 (s[1], c[1], a[1], b[1], c[0]);
FA F3 (s[2], c[2], a[2], b[2], c[1]);
FA F4 (s[3], co, a[3], b[3], c[2]);
endmodule

4 BIT FULL ADDER TESTBENCH

module stimulus_FA4;
reg [3:0]a, b;
reg ci;
wire co;
wire [3:0]s;
FA4 F(s, co, a, b, ci);
initial
begin
a=4'b0000; b=4'b0000; ci=0;
#10 a=4'b0001; b=4'b0010;
#10 a=4'b0010; b=4'b1001;
#10 a=4'b1001; b=4'b0101;
#10 a=4'b0101; b=4'b0111;
#10 $finish;
end
endmodule
 VERILOG CODE FOR DATA PATH 1

module addertree1 (x, co, a, b, c, d, ci);

input [3:0]a, b, c, d;
input [2:0]ci;
output [3:0]x;
output [2:0]co;
wire [3:0]w [0:6];
assign clk=1;
register A(w[0], a, clk);
register B(w[1], b, clk);
register C(w[2], c, clk);
register D(w[3], d, clk);
FA4 M1(w[4], co[0], w[0], w[1], ci[0]);
FA4 M2(w[5], co[1], w[2], w[3], ci[1]);
FA4 M3(w[6], co[2], w[4], w[5], ci[2]);
register S(x, w[6], clk);
endmodule

VERILOG CODE FOR DATA PATH 2

input [3:0]a, b, c, d;
input [2:0]ci;
output [3:0]x;
output [2:0]co;
wire [3:0]w [0:8];
assign clk=1;
register A(w[0], a, clk);
register B(w[1], b, clk);
register C(w[2], c, clk);
register D(w[3], d, clk);
FA4 M1(w[4], co[0], w[0], w[1], ci[0]);
FA4 M2(w[5], co[1], w[2], w[3], ci[1]);
register E(w[6], w[4], clk);
register F(w[7], w[5], clk);
FA4 M3(w[8], co[2], w[6], w[7], ci[2]);
register S(x, w[8], clk);
endmodule
 TESTBENCH FOR DATA PATH 1 AND 2

module stimulus_addertree;
reg [3:0]a, b, c, d;
reg [2:0]ci;
wire [3:0]x;
wire [2:0]co;
reg clk;
addertree1 a1(x, co, a, b, c, d, ci);
//addertree2 a2(x, co, a, b, c, d, ci);
initial
clk=1'b1;
always
#5 clk= ~clk;
initial
begin
a=4'b0000; b=4'b0000; c=4'b0000; d=4'b0000; ci[0]=0; ci[1]=0; ci[2]=0;
#10 a=4'b0001; b=4'b0011;
#10 a=4'b0010; b=4'b0011;
#10 a=4'b0010; b=4'b0101;
#10 a=4'b0110; b=4'b0010;
#10 $finish;
end
initial
begin
#10 c=4'b0101; d=4'b0100;
#10 c=4'b0100; d=4'b0010;
#10 c=4'b0110; d=4'b0001;
#10 c=4'b0011; d=4'b0100;
#10 $finish;
end
endmodule
 TESTBENCH WAVEFORM FOR DATA PATH 1

TESTBENCH WAVEFORM FOR DATA PATH 2