EXPERIMENT NO 2

AIM: To implement HALF ADDER in VHDL using dataflow, behavioral and

structural style of modeling.

INTRODUCTION:
Half adder is the most basic digital arithmetic circuit. It is a logical circuit that
performs an addition operation on two binary digits. It is a combinational circuit
which produces a sum and a carry value, which are both binary digits.

A half adder has two inputs, generally labeled A and B, and two outputs, the “sum”
S and “carry flag” C.

S is the two-bit “XOR gate” of A and B, and C is the “AND gate” of A and B.

S= A xor B

C=A and B

Following is the truth table for a half adder is –

A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Dataflow code for half adder
library ieee;

use ieee.std_logic_1164.all;

entity halfdata is

port(a,b:in bit;

s,c:out bit);

end halfdata;

architecture halfdata of halfdata is

begin

s<=a xor b;

c<= a and b;

end halfdata;

Output

Behaviuoral code for half adder

library ieee;

use ieee.std_logic_1164.all;

entity halfbehv is

port(a,b:in bit;

s,c:out bit);

end halfbehv;

architecture halfbehv of halfbehv is

begin

p1:process(a,b)

begin

if a & b ="00"

then s<='0'; c<='0';

elsif a & b ="01"

then s<='1'; c<='0';

elsif a & b ="10"

then s<='1'; c<='0';

else s<='0'; c<='1';

end if;

end process p1;

end halfbehv;

Output

Structural code for half adder

library ieee;

use ieee.std_logic_1164.all;

entity andg is

port(a,b:in bit;

z:out bit);

end andg;
architecture e1 of andg is

begin

z<= a and b;

end e1;

entity xorg is

port(a,b:in bit;

z:out bit);

end xorg;

architecture e2 of xorg is

begin

z<= a xor b;

end e2;

entity ha is

port(a,b:in bit;

s,c:out bit);

end ha;

architecture ha of ha is

component andg

port(a,b:in bit;

z:out bit);

end component;

component xorg

port(a,b:in bit;

z:out bit);

end component;

begin
a1 : andg port map(a,b,c);

a2 : xorg port map(a,b,s);

end ha;

Output
 EXPERIMENT NO 3

AIM: To implement FULL ADDER in VHDL using dataflow,

behavioral and structural style of modeling.
INTRODUCTION:
Full adder is a combinational circuit that performs an addition operation on three
binary digits. It produces a sum and a carry value, which are both binary digits.

A half adder has three inputs, generally labelled A, B, and Cin, and two outputs,
the “sum” S and “carry flag” Cout.

S is the two-bit “XOR gate” of A, B, and Cin.

S= A xor B xor Cin

Cout=A.B+ (A xor B) Cin

Following is the truth table for a full adder is-

A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Dataflow code for full adder

library ieee;

use ieee.std_logic_1164.all;

entity fa is

port(a, b, c: in bit;

sum, carry : out bit);

end fa;

architecture full_adder of fa is

begin

sum <= a xor b xor c;

carry <= (a and b)or(b and c)or(c and a);

end full_adder;

Output waveform
Structural code for full adder
library ieee;

use ieee.std_logic_1164.all;

entity xor2 is

port(a,b:in bit;

y:out bit);

end xor2;

architecture e3 of xor2 is

begin

y<= a xor b;

end architecture;

entity and2 is

port(a,b:in bit;

y:out bit);

end and2;

architecture e2 of and2 is

begin

y<= a and b;

end architecture;

entity or3input is
port(d,e,f:in bit;

y:out bit);

end or3input;

architecture e1 of or3input is

begin

y<=d or e or f;

end architecture;

entity fastr is

port(a,b,c:in bit;

sum,carry:out bit);

end fastr;

architecture gate of fastr is

component xor2

port(a,b:in bit;

y:out bit);

end component;

component and2

port(a,b:in bit;

y:out bit);

end component;

component or3input

port(d,e,f:in bit;

y:out bit);

end component;

signal y1,x1,x2,x3:bit;

begin
u0:xor2 port map(a,b,y1);

u1:and2 port map(a,b,x1);

u2:and2 port map(b,c,x2);

u3:and2 port map(c,a,x3);

u4:xor2 port map(y1,c,sum);

u5:or3input port map(x1,x2,x3,carry);

end gate;

Output waveform

Behavioural code for full adder

library ieee;

use ieee.std_logic_1164.all;

entity fa is

port (a, b, c : in bit;

sum,carry: out bit);

end fa;

architecture fa_beh of fa is

begin

process (a,b,c)

begin

if a & b & c ="000"

then sum<='0'; carry<='0';

elsif a & b & c ="001"

then sum<='1'; carry<='0';

elsif a & b & c ="010"

then sum<='1'; carry<='0';

elsif a & b & c ="011"

then sum<='0'; carry<='1';

elsif a & b & c ="100"

then sum<='1'; carry<='0';

elsif a & b & c ="101"

then sum<='0'; carry<='1';

elsif a & b & c ="110"

then sum<='0'; carry<='1';

elsif a & b & c ="111"

then sum<='1'; carry<='1';

end if;

end process;

end fa_beh;

Output waveform

EXPERIMENT NO 4
AIM: To implement a 4X1 multiplexer in VHDL using dataflow,
behavioral and structural style of modeling.
INTRODUCTION: In electronics, a multiplexer or mux is a device that
performs multiplexing; it selects one of many analog or digital input signals and
forwards the selected input into a single line. A multiplexer of 2n inputs has n
select lines, which are used to select which input line to send to the output.
An electronic multiplexer makes it possible for several signals to share one device
or resource, for example one A/D converter or one communication line, instead of
having one device per input signal.

FUNCTION : Y = ((d0 and (not s0) and (not s1)) or

(d1 and (not s1) and s0) or

(d2 and s1 and (not s0)) or

(d3 and s0 and s1))

Dataflow code for 4*1 mux

library ieee;

use ieee.std_logic_1164.all;

entity mux4 is

port(d0,d1,d2,d3,s0,s1:in bit;

y:out bit);

end mux4;

architecture gate of mux4 is

begin

y<=((d0 and (not s0) and (not s1)) or(d1 and (not s1) and s0) or(d2 and
s1 and (not s0)) or (d3 and s0 and s1));

end gate;

Output waveform

Behavioral code for 4 to 1 multiplexer

TRUTH TABLE:

I/P O/P

S0 S1 Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3
Behavioral code:
library ieee;

use ieee.std_logic_1164.all;

entity mux4beh is

port(d0,d1,d2,d3,s0,s1:in bit;

y:out bit);

end mux4beh;

architecture gate of mux4beh is

begin

process(d0,d1,d2,d3,s0,s1)

begin

if(s1='0' and s0='1')

then y<=d0;

elsif(s0='0' and s1='1')

then y<=d1;

elsif(s0='1'and s1='0')

then y<=d2;

elsif(s0='1' and s0='1')

then y<=d3;

end if;

end process;

end gate;

Output waveform
Structural code for 4*1 mux
library ieee;

use ieee.std_logic_1164.all;

entity not1 is

port(a:in bit;

y:out bit);

end not1;

architecture e1 of not1 is

begin

y<= not a;

end architecture;

entity and3 is

port(a,b,c:in bit;

y:out bit);

end and3;

architecture e2 of and3 is

begin

y<= a and b and c;

end architecture;

entity or4 is

port(a,b,c,d:in bit;

y:out bit);

end or4;

architecture e3 of or4 is

begin

y<= a or b or c or d;

end architecture;

entity mux4str is

port(d0,d1,d2,d3,s0,s1:in bit;

y:out bit);

end mux4str;

architecture gate of mux4str is

component not1

port(a:in bit;

y:out bit);

end component;

component and3

port(a,b,c:in bit;

y:out bit);

end component;

component or4

port(a,b,c,d:in bit; y:out bit);

end component;

signal x1,x2,x3,x4,x5,x6:bit;
begin

u0:not1 port map(s0,x1);

u1:not1 port map(s1,x2);

u2:and3 port map(x1,x2,d0,x3);

u3:and3 port map(x1,s1,d1,x4);

u4:and3 port map(x2,s0,d2,x5);

u5:and3 port map(s0,s1,d3,x6);

u6:or4 port map(x3,x4,x5,x6,y);

end gate;

Output waveform
 EXPERIMENT NO 5

AIM: To implement a 3X8 decoder in VHDL using dataflow,

behavioral and structural style of modeling.

INTRODUCTION: A decoder is a device which does the reverse of

an encoder, undoing the encoding so that the original information can be retrieved.
The same method used to encode is usually just reversed in order to decode.
In digital electronics, a decoder can take the form of a multiple-input, multiple-
output logic circuit that converts coded inputs into coded outputs, where the input
and output codes are different. e.g. n-to-2n, binary-coded decimal decoders. Enable
inputs must be on for the decoder to function, otherwise its outputs assume a single
"disabled" output code word. Decoding is necessary in applications such as
data multiplexing, 7 segment display and memoryaddress decoding.

Decoder behavioural
library ieee;

use ieee.std_logic_1164.all;

entity decoder is

port (s:out bit_vector(0 to 7);

a:in bit_vector(0 to 2));

end decoder;

architecture behaviour of decoder is

begin

process(a)

begin

case a is

when "000" => s<="10000000";

when "001" => s<="01000000";

 when "010" => s<="00100000";

when "011" => s<="00010000";

when "100" => s<="00001000";

when "101" => s<="00000100";

when "110" => s<="00000010";

when "111" => s<="00000001";

end case;

end process;

end behaviour;

OUTPUT:
Decoder dataflow
library ieee;

use ieee.std_logic_1164.all;

entity decoder is

port(x,y,z,enable:in bit;a,b,c,d,e,f,g,h:out bit);

end decoder;

architecture deco1 of decoder is

begin

a<=((not x)and (not y)and (not z));

b<=((not x)and (not y)and z);

c<=((not x)and y and (not z));

d<=((not x)and y and z);

e<=(x and (not y)and (not z));

f<=(x and (not y)and z);

g<=(x and y and (not z));

h<=(x and y and z);

end deco1;

OUTPUT
Decoder in structural
entity notg is

port(a:in bit;

b: out bit);

end notg;

architecture e1 of notg is

begin

b<= not a;

end architecture;

entity andg is

port(a,b,c:in bit;

d: out bit);

end andg;

architecture e2 of andg is

begin

d<= a and b and c;

end architecture;

entity main is

port( a: in bit_vector(0 to 2);

d: out bit_vector(0 to 7));

end main;

architecture main of main is

component notg is

port(a:in bit;

b: out bit);

end component;
component andg is

port(a,b,c:in bit;

d: out bit);

end component;

signal x,y,z:bit;

begin

x1:notg port map(a(0),x);

x2:notg port map(a(1),y);

x3:notg port map(a(2),z);

x4:andg port map(x,y,z,d(0));

x5:andg port map(x,y,a(2),d(1));

x6:andg port map(x,a(1),z,d(2));

x7:andg port map(x,a(1),a(2),d(3));

x8:andg port map(a(0),y,z,d(4));

x9:andg port map(a(0),y,a(2),d(5));

x10:andg port map(a(0),a(1),z,d(6));

x11:andg port map(a(0),a(1),a(2),d(7));

end architecture;
OUTPUT
 EXPERIMENT 6
AIM: To implement a D, T, S-R, J-K Flip Flop using behavioural style
of modeling.
INTRODUCTION:
D FLIP FLOP : The Q output always takes on the state of the D input at the
moment of a rising clock edge (or falling edge if the clock input is active low).[7] It
is called the D flip-flop for this reason, since the output takes the value of
the D input or Data input, and Delays it by one clock count. The D flip-flop can be
interpreted as a primitive memory cell, zero-order hold, or delay line.
Truth table:

Clock D Q Qprev

Rising
0 0 X
edge

Rising
1 1 X
edge

Non-Rising X Qprev

D FLIP FLOP CODE

library ieee;

use ieee.std_logic_1164.all;

entity diff is

port(d,clk:in bit;

q,qbar:inout bit);
end diff;

architecture behav of diff is

begin

process(d,clk)

begin

if clk='1' and clk' event

then

q<= d;

qbar<= not d;

end if;

end process;

end behav;

Output
T FLIP FLOP

INTRODUCTION: If the T input is high, the T flip-flop changes state ("toggles") whenever the
clock input is strobed. If the T input is low, the flip-flop holds the previous value. This behavior is
described by the characteristic equation:

(or, without benefit of the XOR operator, the

equivalent: )

and can be described in a truth table:

T Flip-Flop operation [6]

Characteristic table Excitation table

T Q Qnext Comment Q Qnext T Comment

0 0 0 hold state (no clk) 0 0 0 No change

0 1 1 hold state (no clk) 1 1 0 No change

1 0 1 toggle 0 1 1 Complement

1 1 0 toggle 1 0 1 Complement
T FLIP FLOP CODE
library ieee;

use ieee.std_logic_1164.all;

entity tiff is

port(t,clk:in bit;

q,qbar:inout bit);

end tiff;

architecture behav of tiff is

begin

process(t,clk)

begin

if clk='1' and clk' event

then

q<=not t;

qbar<=t;

end if;

end process;

end behav;

Output
SR FLIP FLOP
INTRODUCTION : The fundamental latch is the simple SR flip-flop, where S and R stand
for set and reset, respectively. It can be constructed from a pair of cross-coupled NAND or NORlogic
gates. The stored bit is present on the output marked Q.

Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs
in a constant state, with Q the complement of Q. If S is pulsed high while R is held low, then the Q output
is forced high, and stays high even after S returns low; similarly, if R is pulsed high while S is held low,
then the Q output is forced low, and stays low even after R returns low.

SR Flip-Flop operation (BUILT WITH NOR GATES) [6]

Characteristic table Excitation table

S R Action Q(t) Q(t+1) S R Action

0 0 Keep state 0 0 0 X No change

0 1 Q=0 0 1 1 0 reset

1 0 Q=1 1 0 0 1 set

1 1 Unstable combination 1 1 X 0 race condition

('X' denotes a Don't care condition; meaning the signal is irrelevant)

SR FLIP FLOP CODE
library ieee;

use ieee.std_logic_1164.all;

entity srff is

port(s,r,clk:in bit;

q,qbar:inout bit);

end srff;

architecture behav of srff is

begin

process(s,r,clk)

variable g: bit_vector(0 to 1);

begin

g:= s&r;

if clk='1' and clk' event

then

case g is

when "00"=> null;

when "01"=> q<='0'; qbar<='1';

when "10"=> q<='1'; qbar<='0';

when "11"=> assert r/='1' and s/='1'report "invalid condition" severity error;

end case;

end if;

end process;

end behav;

Output
JK FLIP FLOP
INTRODUCTION: The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by
interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K =
0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and
the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical
complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the
current state. To synthesize a D flip-flop, simply set K equal to the complement of J. The JK flip-flop is
therefore a universal flip-flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T
flip-flop.

The characteristic equation of the JK flip-flop is:

and the corresponding truth table is:

JK Flip Flop operation [6]

Characteristic table Excitation table

J K Qnext Comment Q Qnext J K Comment

0 0 Qprev hold state 0 0 0 X No change

0 1 0 reset 0 1 1 X Set

1 0 1 set 1 0 X 1 Reset

1 1 Qprev toggle 1 1 X 0 No change

JK FLIP FLOP CODE

library ieee;

use ieee.std_logic_1164.all;
library ieee;

use ieee.std_logic_1164.all;

entity jkff is

port(j,k,clk:in bit;

q,qbar:inout bit);

end jkff;

architecture behav of jkff is

begin

process(j,k,clk)

variable s: bit_vector(0 to 1);

begin

s:= j&k;

if clk='1' and clk' event

then

case s is

when "00"=> null;

when "01"=> q<='0'; qbar<='1';

when "10"=> q<='1'; qbar<='0';

when "11"=> q<=not q; qbar<=q;

end case;

end if;

end process;

end behav;
OUTPUT

EXPERIMENT 7
AIM: To design shift registers in VHDL using structural.
INTRODUCTION: These are the simplest kind of shift registers. The data string is
presented at 'Data In', and is shifted right one stage each time 'Data Advance' is brought high.
At each advance, the bit on the far left (i.e. 'Data In') is shifted into the first flip-flop's
0 0 0 0
output. The bit on the far right (i.e. 'Data Out') is shifted out and lost.
1 0 0 0
The data are stored after each flip-flop on the 'Q' output, so there are four storage
0 1 0 0
'slots' available in this arrangement, hence it is a 4-Bit Register. To give an idea of
1 0 1 0
the shifting pattern, imagine that the register holds 0000 (so all storage slots are
1 1 0 1
empty). As 'Data In' presents 1,0,1,1,0,0,0,0 (in that order, with a pulse at 'Data
0 1 1 0
Advance' each time. This is called clocking or strobing) to the register, this is the
0 0 1 1
result. The left hand column corresponds to the left-most flip-flop's output pin, and so
0 0 0 1
on.
0 0 0 0
So the serial output of the entire register is 10110000 (). As you can see if we were to
continue to input data, we would get exactly what was put in, but offset by four 'Data Advance'
cycles. This arrangement is the hardware equivalent of a queue. Also, at any time, the whole
register can be set to zero by bringing the reset (R) pins high.

This arrangement performs destructive readout - each datum is lost once it been shifted out of
the right-most bit.

SISO CODE
entity dff is

port(d,clk:in bit;

q:out bit);

end dff;

architecture e1 of dff is

begin

process(d, clk)

begin

if clk='1' and clk'event then

q<=d;

end if;

end process;

end e1;

entity siso is

port( input,clk:in bit;

qout:out bit);

end siso;

architecture e1 of siso is

component dff

port(d,clk:in bit;

q:out bit);

end component;

signal q0,q1,q2:bit;

begin

n1:dff port map(input,clk,q0);

n2:dff port map(q0,clk,q1);

n3:dff port map(q1,clk,q2);

n4:dff port map(q2,clk,qout);

end e1;
OUTPUT:

PIPO
INTRODUCTION: The PARALLEL IN/PARALLEL OUT shift register is loaded
with four bits simultaneously, in parallel.They are also clocked out
simultaneously, in parallel.

PIPO CODE

library ieee;

use ieee.std_logic_1164.all;

entity dff is

port(d,clk:in bit;
q:out bit);

end dff;

architecture e1 of dff is

begin

process(d, clk)

begin

if clk='1' and clk'event then

q<=d;

end if;

end process;

end e1;

entity pipo is

port( a,b,c,d,clk:in bit;

q0,q1,q2,q3:out bit);

end pipo;

architecture e1 of pipo is

component dff

port(d,clk:in bit;

q:out bit);

end component;

begin

n1:dff port map(a,clk,q0);

n2:dff port map(b,clk,q1);

n3:dff port map(c,clk,q2);

n4:dff port map(d,clk,q3);

end e1;
OUTPUT:
PISO
INTRODUCTION: This configuration has the data input on lines D1 through D4 in parallel
format. To write the data to the register, the Write/Shift control line must be held LOW. To shift
the data, the W/S control line is brought HIGH and the registers are clocked. The arrangement
now acts as a SISO shift register, with D1 as the Data Input. However, as long as the number of
clock cycles is not more than the length of the data-string, the Data Output, Q, will be the
parallel data read off in order.

PISO CODE

library ieee;

use ieee.std_logic_1164.all;

entity dff is

port(d,clk:in bit;

q:out bit);

end dff;

architecture e1 of dff is

begin

process(d, clk)

begin

if clk='1' and clk'event then

q<=d;

end if;

end process;

end e1;

entity cont is

port(outf1,x,control: in bit;

inpf2: out bit);

end cont;
architecture e1 of cont is

begin

process(x,control,outf1)

begin

if control='1' then

inpf2<=x;

else

inpf2<=outf1;

end if;

end process;

end architecture;

entity piso is

port( a,b,c,d,clk,control:in bit;

q0,q1,q2,q3:inout bit;

d0,d1,d2,d3: inout bit);

end piso;

architecture e1 of piso is

component dff

port(d,clk:in bit;

q:out bit);

end component;

component cont is

port(outf1,x,control: in bit;

inpf2: out bit);

end component;

begin
d0<=a;

n1:dff port map(a,clk,q0);

n2:cont port map(q0,b,control,d1);

n3:dff port map(d1,clk,q1);

n4:cont port map(q1,c,control,d2);

n5:dff port map(d2,clk,q2);

n6:cont port map(q2,d,control,d3);

n7:dff port map(d3,clk,q3);

end e1;

OUTPUT
Output when cntrl=1
Output when control=0

SIPO
INTRODUCTION: This configuration allows conversion from serial to parallel format. Data is
input serially, as described in the SISO section above. Once the data has been input, it may be either
read off at each output simultaneously, or it can be shifted out and replaced.

SIPO CODE:
library ieee;

use ieee.std_logic_1164.all;

entity dff is

port(d,clk:in bit;
q:out bit);

end dff;

architecture e1 of dff is

begin

process(d, clk)

begin

if clk='1' and clk'event then

q<=d;

end if;

end process;

end e1;

entity sipo is

port( input,clk:in bit;

q0,q1,q2,q3:inout bit);

end sipo;

architecture e1 of sipo is

component dff

port(d,clk:in bit;

q:out bit);

end component;

begin

n1:dff port map(input,clk,q0);

n2:dff port map(q0,clk,q1);

n3:dff port map(q1,clk,q2);

n4:dff port map(q2,clk,q3);

end e1;
OUTPUT

Bcd

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY binary_counter IS
port( clk, reset:in bit; count:out std_logic_vector( 0 to 2));
END ENTITY binary_counter;

--
ARCHITECTURE binary OF binary_counter IS
signal temp: std_logic_vector( 0 to 2):="000";
BEGIN
process ( clk, reset)
begin
if reset='1' then temp<="000";
else if clk='1' and clk'event then
temp<= temp+ 1;
end if;
end if;
end process;
count<= temp;
END ARCHITECTURE binary;