1.

Which of the following is NOT an advantage of digital circuits over analog

circuits?
a) Reproducibility of results
b) Ease of design
c) Programmability
d) Accuracy

2. Which ‘law’ describes the exponential growth of integrated circuit complexity?

a) Ohm’s law
b) Faraday’s law
c) Moore’s law
d) Stephen’s law

3. Which of the following is not the advantage of digital design?

a) Computing power doubles every 18 months
b) Less effected by noise
c) The price of computing increase by half every 18 months
d) Higher storage capability

4. What implementation method would be appropriate for an application having a

complexity equivalent to about 20 standard logic gates?
a) A series of standard CMOS or TTL gate devices
b) A simple PLD
c) A complex PLD or FPGA
d) A microprocessor

5. What is the defining difference between microprocessor/DSP systems and other

digital systems?
a) The microprocessor follows a programmed sequence of instructions that
the designer specified
b) The digital system follows a programmed sequence of instructions that the
designer specified
c) The microprocessor/DSP is faster
d) The digital system is faster

6. Why have PLDs taken over so much of the market?

a) One PLD does the work of many ICs
b) The PLDs are cheaper
c) Less power is required
d) All of the above

7. Which of the following statements is incorrect?

a) Some PLDs are programmed using mechanical switches
b) Some PLDs are programmed using fuses that are selectively blown
c) Some PLDs are programmed using anti-fuses that are selectively joined
d) Some PLDs are programmed using electrically operated switches

8. Which type of PLD used multiple circuit blocks to program the logic functions?
 a) PLA
b) PAL
c) CPLD
d) SLD

9. Once a PAL has been programmed:

a) it cannot be programmed
b) its outputs are only active HIGHs
c) its outputs are only active LOWs
d) its logic capacity is lost

10. The difference between a PLA and a PAL is:

a) the PLA has a programmable OR plane and a programmable AND plane,
while the PAL only has a programmable AND plane
b) the PAL has a programmable OR plane and a programmable AND plane,
while the PLA only has a programmable AND plane
c) the PAL has more possible product terms than the PLA
d) PALs and PLAs are the same thing

11. A CPLD is a
a) controlled program logic device
b) complex programmable logic driver
c) complex programmable logic device
d) central processing logic device

12. The CPLD contains several PLD blocks and:

a) Field-programmable switches
b) AND/OR arrays
c) a global interconnection matrix
d) a language compiler

13. Many companies are transitioning to using FPGAs for their processor designs
instead of ASICs. Why?
a) FPGAs always outperform an ASIC
b) The development cycle for an FPGA is much shorter
c) FPGAs are both smaller and faster
d) FPGAs are more space-efficient

14. __________ are the EDA tools for front-end design process.
a) Design entry
b) Simulation tools
c) Synthesis tools
d) All of these

15. HDL is a
a) logic device
b) PLD programming language
c) computer language
d) very high density logic
16. HDL can be used to
a) Represent Boolean expressions and complex abstraction of the behaviour
of a digital system
b) Represent logic diagram and truth tables only
c) Represent logic diagram, truth table, Boolean expressions and complex
abstraction of the behaviour of a digital design
d) None of the above

17. Which the following statements is not relevant regarding the goal of the HDL?
a) Most reliable design process
b) With maximum cost and time
c) With minimum cost and time
d) Free of design errors

18. What is design entry in HDL?

a) It is to create HDL based description of functionality to be fabricated in
hardware
b) It is to create HDL based description of propagation time
c) It is to create HDL based description of time delay
d) None of the above

19. What is test bench in HDL?

a) A physical arrangement for the testing
b) A software stimulus that test the functionality of the design
c) A hardware module that test the functionality of the design
d) None of the above

20. Which of the following features of the HDL structural modeling is NOT true?
a) It cannot model the gate’s delay
b) It is suitable for the large logic system
c) The order of the gate instantiations does not matter
d) It requires users to pre-minimize the logic function.

21. Construct a table of differences between four philosophies of digital design?