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Summary Intelligence for the NanoBoard-NB1 is provided courtesy of firmware running in the
board's NanoTalk Controller. This application note describes how to update this
Application Note
firmware, which gets loaded into the NanoTalk Controller at power-up.
AP0105 (v2.0) February 28, 2008
The NanoBoard firmware is the program that is loaded into the NanoTalk Controller when the board is powered-up. The
NanoBoard-NB1 uses a Xilinx Spartan IIE-100K device (XC2S100E) as the controller for the board. Referred to as the
NanoTalk Controller, this device (U8 on the board) manages JTAG communications with the following:
• FPGA Daughter Board
• Master/Slave daisy-chain
• User Board connectors (A and B)
• Flash RAMs (U6 and U7)
• The SPI Master clock.
The NanoTalk Controller also manages the following two areas of the board:
• LEDs SL1-SL8
• The following jumpers on JP2:
- AUTO LOAD FPGA
- CLOCK0
- CLOCK1
- CLOCK2
- USER A – BYPASS SOFT
- USER B – BYPASS SOFT
- TEST 0
- TEST 1
The firmware that is loaded into the NanoTalk Controller is stored in a Xilinx Serial PROM device (XCF01S). This is U5 on the
board.
On power-up, the firmware is automatically loaded into the NanoTalk Controller.
Pre-update preparation
Before the new version of firmware can be downloaded to the Serial PROM, the NanoBoard must first be prepared as follows.
1. Turn off the NanoBoard.
2. Remove any FPGA Daughter Board that is currently plugged in.
3. Insert a jumper at JP2 – SYSTEM JTAG on the NanoBoard (to the bottom left of the parallel cable connector). This is a fixed
function jumper which, when inserted, switches control of the NanoBoard from the NanoTalk Controller (Spartan IIE-100K) to
a simple hardware chain, which involves the NanoTalk Controller and the Xilinx Serial PROM. These will display in the Hard
Devices chain in the Devices view, as shown in Figure 1.
4. Power-up the NanoBoard.
The Xilinx Serial PROM is a Flash memory device. Before it can be programmed with the new firmware, it must first be cleared.
To do this, right-click on its icon in the Hard Devices chain (Platform Flash) and choose Reset Hard Device from the pop-up
menu.
The erasing process will proceed, with progress shown in Altium Designer's Status bar. The process takes approximately 15
seconds to complete.
Figure 2. Target FPGA device detection and test of the Soft Devices chain.
7. With the chosen design running in the FPGA, double-click on the icon for the NB1 (in the NanoBoard chain of the Devices
view). The Instrument Rack for the NanoBoard Controllers will appear. Use the Instrument Panel to change the system clock
frequency. This will write the new clock frequency to the system clock which, being an SPI device, will test that
communication to SPI devices is working correctly.
As well as writing the new frequency to the clock, the value will also be stored in the NanoTalk Controller and will be read
back to verify the change. The new frequency is persistent across design sessions with respect to the software, but not
persistent across hardware sessions. Therefore, closing the application, relaunching and opening an FPGA project will result
in the last clock frequency entered being used. However, cycling the power on the NanoBoard will result in the default clock
frequency (50MHz) being used because the register used to store the chosen clock frequency in the NanoTalk Controller is
cleared on power-down.
Revision History
Date Version No. Revision