International Journal of Electronics

ISSN: 0020-7217 (Print) 1362-3060 (Online) Journal homepage: http://www.tandfonline.com/loi/tetn20

Modeling, design and stability analysis of an

improved SEPIC converter for renewable energy
systems

G Dileep, S. N. Singh & G. K. Singh

To cite this article: G Dileep, S. N. Singh & G. K. Singh (2017): Modeling, design and stability
analysis of an improved SEPIC converter for renewable energy systems, International Journal of
Electronics, DOI: 10.1080/00207217.2017.1312709

To link to this article: http://dx.doi.org/10.1080/00207217.2017.1312709

Accepted author version posted online: 11

Apr 2017.

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Download by: [Oklahoma State University] Date: 16 April 2017, At: 14:15
Publisher: Taylor & Francis

Journal: International Journal of Electronics

DOI: 10.1080/00207217.2017.1312709
Modeling, design and stability analysis of an improved SEPIC
converter for renewable energy systems
Dileep. G*, S. N. Singh**, G. K. Singh***
*
Research Scholar, Alternate Hydro Energy Centre, Indian Institute of Technology Roorkee,
Uttarakhand-247667
E-mail: dileepmon2@gmail.com
**
Senior Scientific Officier, Alternate Hydro Energy Centre, Indian Institute of Technology
Roorkee, Uttarakhand-247667
***
Professor, Electrical Engineering Department, Indian Institute of Technology Roorkee,
Uttarakhand-247667
Abstract

In this paper, a detailed modeling and analysis of a switched inductor (SI) based improved single
ended primary inductor converter (SEPIC) has been presented. To increase the gain of
conventional SEPIC converter, input and output side inductors are replaced with switched
inductor structures. Design and stability analysis for continuous conduction mode (CCM)
operation of the proposed SI-SEPIC converter has also been presented in this paper. State space
averaging technique is used to model the converter and carry out the stability analysis.
Performance and stability analysis of closed loop configuration is predicted by observing the
open loop behavior using Nyquist diagram and Nichols chart. System was found to stable and
critically damped.

Keywords: SEPIC, switched circuits, voltage multiplier, high gain, stability.

1. Introduction
DC-DC converters (Akter et al 2015, Silva et al 2015) have drawn attraction these days, and
are being used extensively with modern electronic systems. Since most of the renewable energy
resources produce dc voltage, a DC-DC converter is used to transfer the power from source to
load. For tracking solar and wind power, which are stochastic in nature, DC-DC converters are
used as an impedance matching unit. . In order to track the varying power, a DC-DC converter
with maximum power point tracker is used. DC-DC converters act as an impedance matching
unit in between the PV panel and load. By controlling the converter duty ratio, input impedance

1
of the converter is made equal to output impedance of the PV panel and load matching is
achieved. Selection of DC-DC converters for solar power tracking is based on certain factors
such as efficiency, cost, PV module effect, input/output energy flow and flexibility. Boost
converter, Buck converter, Buck-Boost converter, Single ended primary inductor converter
(SEPIC) and Cuk converter are commonly used for power tracking. Boost converter (Lee et. Al
2015, Silva et al 2016, Do 2012) is used to step up the input voltage. Input/output energy flow of
boost converter is continuous and higher efficiency can be achieved with low cost circuit
topology. Output voltage flexibility of boost converter is not good, as it is not able to step down
the voltage which adversely affects the peak power tracking under certain conditions. Buck
converter (Tsai et al 2007, Lin et al 2010, Lee et al 2012) is used to step down the input voltage;
input power flow in buck converter is not continuous as the input side switch is continuously
operated. Due to continuous operation of input side switch, PV array will be isolated from the
load for a moment. Buck converter is not able to step up the output voltage which affects the
peak power tracking. Buck-Boost, Cuk and Single ended primary inductor converter (SEPIC)
performs both boosting action and bucking actions. Similar to buck converter, input power flow
of Buck-Boost converter (Sundareswaran et al 2010) is discontinues and input side switching
losses are more. Peak power tracking with Buck-Boost converter is flexible; but, out voltage of
converter is inverted. Cuk (Lin et al 2009, Hoyo et al 2006) converter provides better efficiency
than Buck-Boost converter with continuous input/output power flow, but output voltage is
inverted. SEPIC provides non inverted output voltage with continuous input/output energy flow
and better efficiency. Due to these inherent advantages, SEPIC converter is preferred over other
converter topologies for solar power tracking. Ebhramin has analyzed the energy transmission
process (Babaei et al 2014) in SEPIC converter during continuous (CCM) and discontinuous
(DCM) mode of operation. Boundary condition between CCM and DCM and design of input
inductor for maintaining continuous conduction is also presented in this paper. Kim-Bum et al.
increased the gain of conventional SEPIC converter (Park et al 2010) by integrating it with a
boost converter. The proposed converter is simple and small in size since boost and SEPIC
counterpart uses common switch and input inductor, but associated switching loss and switching
stress is high. Hong boma et al. proposed a SEPIC converter based LED lightning system (Hong
boma et al 2012), which reduces the size and stress on LED storage capacitor. By reducing stress
on storage capacitor, author increased the overall life time of LED lightning system. Rodhi sahid
et al. presented a bridge less SEPIC converter for power factor correction (PFC) (Sahid et al
2011) with less number active components during each switching period. They verified the large
signal behavior of the proposed converter by developing and carrying out the analysis on large
signal and switch model. Kannan et al. have proposed the modeling and analysis along with the
controller design of a SEPIC converter for PFC (Kanaan et al 2013). Numerical simulation and
analysis of converter with three control techniques (hysteresis current controller, frequency
domain linear design of regulator, and input/output feedback linearization) has also been
discussed. Jacey et al. (Jozwik et al 1989) proposed the dual SEPIC converter with pulse width
modulation (PWM) switching. They modified the conventional forward converter by replacing

2
one of the rectifier diode with coupling capacitor. Ebrahim et al. presented a paper on output
voltage ripple calculation of SEPIC converter and design method for calculating equivalent
inductance and capacitance (Babaei et al 2014). Tsang et al. have designed a SEPIC converter
with multiloop controller for battery charging application (Tsang et al 2012). Instead of
designing a single controller, they designed a multiloop controller to improve the speed of
response. The decoupled fourth order system into first order systems and designed proportional
plus integral control for first order system then combined together to form multiloop control
system. Jinyinh et al. proposed a quasi resonant SEPIC converter with minimum switching loss
for high frequency control operation (Hu et al 2012). Proposed converter provides a wide voltage
conversion ratio, better steady state and transient performance. Henry et al. (Chung et al 2003)
have discussed a maximum power point tracking technique with SEPIC converter which
eliminates the use of microprocessor/micro computer. MPP is located by comparing the
switching stress and variation in input voltage for small duty cycle perturbation. Veerachary has
presented a technique for MPPT with coupled inductor (Veerachary 2005) SEPIC converter.
Chiang et al designed and implemented the peak current controlled SEPIC converter for peak
power tracing (Chiang et al 2009). Experimental results show that the proposed technique tracks
peak power quickly with fewer oscillations around MPP. Mustafa et al. have given an improved
converter with additional isolation transformer and diode to reduce the output voltage ripple and
switching stress on semiconductor devices (Al-Saffar et al 2008). Roger et al. have explained an
improved SEPIC converter with increased static gain for renewable energy application (Roger et
al. 2008). Performance of improved SEPIC converter with magnetic coupling and without
magnetic coupling has also been compared. Many modified converters techniques (Do et al
2012, Babaei et al 2011, Babaei et al 2012) to reduce switching loss and switching stress of the
semiconductor devices have been proposed by the researchers. Bridgeless SEPIC converter
topologies (Mahdavi et al 2011, Yang et al 2013, Melo et al 2010) are extensively used for
power factor correction, as it offers good steady state and dynamic performance, input/output
isolation by coupling capacitor along with the power factor correction.

Similar techniques were developed for increasing the static gain of converter such as voltage
multiplier cells (Zhou et al 1999, Prudente et al 2008, Ismail et al 2008) inductor magnetic
coupling (Zhao et al 2003, Henn et al 2010, Wai et al 2005, Li et al 2007&2008, Seong et al
2012 ) and combinations of these two ( Wai et al 2007 & 2005, Tofoli 2012, Li et al 2012 ). This
high gain structures are getting greater importance these days due their application in renewable
energy system. But most of these systems are designed for buck, boost and buck-boost
converters. In this paper, a switched inductor SEPIC converter, which doubles the gain of
conventional SEPIC converter, is discussed. Proposed converter is not superior to all the
converters mentioned in literature. However ripple in output voltage is much less in the proposed
converter and extra switches are not used for increasing the gain. Power loss in the converter is
slightly more than conventional SEPIC converter. The main advantage of this converter topology
is that it can be implemented along with some other topologies mentioned in the literature to

3
increase gain. Modeling, design and analysis of the proposed system are presented in detail in
this paper.

In this paper, a SI-SEPIC converter, which doubles the gain of conventional SEPIC
converter, is discussed. Ripple in output voltage is much less in the proposed converter and extra
switches are not used for increasing the gain. Power The main advantage of this converter
topology is that it can be implemented along with some other topologies mentioned in the
literature to increase the gain.

2. Operation of improved switched inductor SEPIC converter

As shown in Fig. 1, input and output side inductors of SEPIC converter are replaced with
switched inductor in SI-SEPIC converter. When switch is made ON, all inductors charges to its
maximum value; and when switch is made OFF, all the inductors discharge simultaneously.
Operation of the proposed converter is symmetrical in two half-line cycles of the input voltage;
hence, converter operation during one switching period in positive half-line cycles of the input
voltage is explained here. It is assumed that all the elements are ideal and converter operates at
steady state in CCM. In order to reduce the output voltage ripple, output capacitor, is
assumed to be large.

Figure. 1. Circuit diagram of improved switched inductor SEPIC converter.

Continuous conduction mode operation of the proposed SI-SEPIC converter can be

divided into two phases: (1). Parallel charging phase of the inductors when switch Q and diodes
, , , and , are ON and diodes , , and D are OFF. (2). Series discharging phase of
the inductors when switch, Q, , , , and , are OFF and diodes , , and D are ON.

Phase: 1 (0 < t <DT): Phase 1 starts when switch is made ON by applying gate pulse. Inductor
currents , , , which was minimum prior to this mode start increasing linearly with
the slopes , , and respectively. Inductors and are charged up to the input
voltage while inductors and are charged up to the coupling capacitor voltage .
Output is completely isolated from the input during this mode, since the diode D is reverse
biased and capacitor maintains the load current continuous. Equivalent circuit of SI-SEPIC
converter during ON period is shown in Fig. 2.

Figure. 2. Circuit diagram for Phase 1, when switch is ON.

Phase: 2 (DT < t <T): Phase 2 starts when switch is made OFF by removing the gate pulse.
Energy stored in inductors and along with is transferred to load through diode D.
During this period, the output capacitor is charged to its maximum value. Inductor
currents , , , decreases linearly with a slope of , , and respectively.

4
Voltage across inductors during this period is equal to . Equivalent circuit of SI-SEPIC
converter during OFF period is shown in Fig. 3.

Figure. 3. Circuit diagram for Phase 2, When switch is OFF.

3. DC voltage transfer function

Applying volt-sec balance theorem,

− −
+ (1 − ) = 0 (3.1)

Since, = and = = = ,voltage across inductor and when switch is closed will
be, from Eq. (3.1),

− (1 − ) = 0 (3.2)
2
The DC voltage transfer function, for the proposed converter,

2
= == (3.3)
1−

From Eq. (3.3), it is clear that the voltage gain of improved SI-SEPIC converter is twice the
conventional SEPIC converter.

4. Design procedure
Design procedure of the proposed converter is similar to conventional SEPIC converter.
Design procedure of an SI-SEPIC converter for a PV module with assumption of following
parameters are described in this section:
Minimum input voltage, Vin (min) = 4V
Maximum input voltage, Vin (max) = 21V
Output voltage, Vo = 14V
Switching frequency, f sw = 50 kHz
Load Resistance, R=10 Ω
4.1. Duty cycle consideration

From Eq. (3) duty cycle for a SI-SEPIC converter operating in CCM can be derived as;
Vo
Dmax = = 0.64
2Vin (min) + Vo

And

5
 Vo
Dmin = = 0.25
2Vin (max) + Vo

4.2. Inductor selection

Ripple current through input inductor L1
Vo
ΔI L = I o × × 40 % = 2.8 A
Vin(min)
And the inductance L1, L2, L3 and L4 are
Vin(min)
L1 = L2 = L3 = L4 = L = × D max = 18μH
ΔI L × f sw
Peak inductor currents which is half of ripple current is given as,
I Vo 40 %
I L1( peak ) = I L 2( peak ) = o × × (1 + ) = 4.35 A
2 Vin(min) 2
Io 40 %
I L 3( peak ) = I L 4( peak ) = × (1 + ) = 1.2A
2 2
4.3. Output capacitor selection
Output capacitor RMS current of modified SEPIC converter is same as conventional SEPIC
converter,
Vo
I co( rms ) = I o = 6.65 A
2Vin
And the output capacitance,
I o × D max
Co ≥ = 180 μF
ΔVo × 0.5 × f sw
4.4. Coupling capacitor selection
Coupling capacitor RMS current is same as conventional SEPIC converter ,
Vo
I cs ( rms ) = I o = 6.65 A
2Vin
Assuming peak to peak ripple as 2% of the output voltage, output capacitor is:
I × D max
Cs ≥ o = 60 μF
ΔVo × f sw
5. Modeling of SI-SEPIC converter by state space averaging

Circuit averaging method or state averaging method can be used to model a SI-SEPIC
converter. State space averaging technique is used for modeling and performing stability analysis
of SI-SEPIC converter. Switching converter is approximated to be a continuous linear system in
this technique. It is difficult to model a non linear system and predict its behavior. Bode plot of
the linearized SI-SEPIC converter can be used to determine the feedback loop compensation
6
required to obtain the desired steady state and transient performances. State space averaging
technique is used for this. As shown in Fig. 2 and Fig. 3, operating phases of SI-SEPIC converter
can be divided into two; phase 1 when switch is turned ON, during this period inductors are
charged and phase 2 when switch is turned OFF, inductors discharge during this period.

5.1. State transition equations of SI-SEPIC converter

During switch ON: Applying KCL and KVL, state equations of the proposed converter are given
by Eq. (5.1) to Eq. (5.4),

= (5.1)

=− (5.2)

= (5.3)

=− (5.4)

State equations for ON period are expressed in state space form as given in Eq. (5.5) and Eq.
(5.6),

 di L a 
 dt  0 0 0 0  1
   −1   iL a   
 dV c s  0 0 0  V   Lb 
 dt  = Cs   cs 
   × + 0  × (5.5)
−1 i
 di Lb   0 0 0   Lb   0 
Lb 1  V  
 dt     co   0 
   −1   
 dV co  0 0 0

 dt   RCo 

 iLa 
 
Vc 
= [ 0 0 0 1] ×  s 
i
 Lb 
Vc 
 o (5.6)

For ON period La1 is equivalent inductance of parallel combination of L1 and L2 and Lb1 is
equivalent inductance of parallel combination L3 and L4 as given in Eq. (5.7) and Eq. (5.8).

7
 L1 L2 − M 2
La1 =
L1 + L2 − 2M
(5.7)

L3 L4 − M 2
Lb1 =
L13 + L4 − 2M
(5.8)

During switch OFF: Applying KCL and KVL, state equations of the proposed converter are
given by Eq. (5.9) to Eq. (5.12),
− −
= (5.9)
2

=− (5.10)

= (5.11)

= − − (5.12)

State equations for ON period are expressed in state space form as given in Eq. (5.13) and
Eq.(5.14),

 di La   −1 −1 
   0 0  1 
 dt   2 La 2 2 La 2 
  iLa   2L 
 dV c s   1     a 
  = 0 0 0  × V c s  + 0 (5.13)
×
 dt   Cs  i   
 di Lb   − 1   Lb 
 dt   0 0 0   0 
   2 L b 2  V c o 
  0 
 dV co   1 1 −1 
 dt   C 0 
 o Co RCo 

And,

 iLa 
 
Vc 
= [ 0 0 0 1] ×  s 
i
 Lb 
Vc 
 o (5.14)

8
For OFF period La2 is equivalent inductance of series combination of L1 and L2 and Lb2 is
equivalent inductance of series combination L3 and L4 as given in Eq. (5.15) and Eq. (5.16).

La 2 = L1 + L2 + 2M
(5.15)

Lb 2 = L1 + L4 − 2 M
(5.16)

5.2. Transfer function of SI-SEPIC converter

Output to input transfer function of SI-SEPIC converter is given by,

X(S) = ( − ) + (5.17)

Substituting for system matrix A, input matrix B, output matrix, C and direct transmission
matrix, E in Eq. (5.17), output to input transfer function of SI-SEPIC converter is obtained as,

1875( + 5 ∗ 10 )
= (5.18)
+ .01 + 87500 + 375 ∗ 10 + 3.1 ∗ 10

6. Various plots of the improved SI-SEPIC converter

Magnitude and phase plot of the proposed SI-SEPIC converter is shown in Fig.4. To determine
the gain margin of the proposed converter phase cross over frequency, the frequency at which the
phase plot crosses -180 degree is measured. Then gain corresponding to phase cross over
frequency is measured from the plot and subtracted from zero to obtain the gain margin. From
the plot, it is clear that the phase angle never crosses -180 degree, and hence gain margin of the
proposed converter is infinity. To determine the phase margin of the proposed converter gain
cross over frequency, the frequency at which gain crosses 0 db is measured. Then phase angle
corresponding to gain cross over frequency is obtained and added to 180 degree to obtain phase
margin. Gain cross over frequency of the proposed converter was found to be 39.7 rad/sec and
the phase angle corresponding to this frequency as -57.6 degree.

Figure. 4. Bode plot of the proposed converter.

Hence phase margin of the proposed converter is 122.40 degrees. For a system to be stable both
gain margin and phase margin must be greater than zero. For the proposed converter gain margin
is infinity and phase margin is 122.4 degrees, since both these values are positive, the proposed
converter is stable. Since phase plot of the proposed converter never crosses -180 degree,
converter never becomes unstable even if gain margin is increased.
Figure. 5. Nyquist diagram of the proposed converter.

9
 Figure. 6. Nichols chart of the proposed converter.

Performance and stability of the closed loop SI-SEPIC converter can be predicted by
observing the open loop behavior using nyquist diagram. As shown in Fig. 5, sum of open loop
poles in right half, and the number of encirclements of -1 made by the nyquist diagram (N) is a
positive real number and mapped contour does not encircle the critical pole (-1,0); hence the
closed loop system will be stable. A system is said to be stable if Nichols plot crosses 0 db line
within (-180, 180) range. As shown in Fig. 6, nichols plot of the proposed converter crosses 0 db
line within (-180, 180) range, hence the proposed converter is stable. Root locus plot of the
proposed converter is shown in Fig. 7. All poles and zeros of the proposed converter lies on left
hand side of S-plane, hence proposed converter is stable and causal.

Figure. 7. Root locus plot of the proposed converter.

7. Experimental results

To validate the theoretical analysis, a low power prototype of the proposed SI-SEPIC converter
has been realized and tested in laboratory. Circuit parameters of the prototype used for
experimental verification are as follows; L1= L2= L3=L4=18µH, C=60µF, Co=200µF, fs=50Khz,
Po=20W and ESR of capacitor and inductor 20mΩ. Experimental set up of the proposed
converter is shown in Fig. 8 and test bench of SI-SEPIC converter is shown insight.

Figure. 8. Experimental setup of SI-SEPIC converter.

An OPAL-RT OP5060 controller has been employed for generating PWM signal in open loop
structure with switching frequency fs=50 Khz. IRF 540 N MOSFET switch and BY229X-500
fast recovery diodes are used to develop the prototype. An FOD 3180 optocoupler-driver IC was
used to amplify the PWM pulse and provide isolation between control circuit and power circuit.
12 V DC power supply for the operation of FOD 3180 has been provided using a regulated
power supply. 0-50 Ω, 5 A rheostat has been used as the resistive load. To check the feasibility
of converter under different operating conditions, it has been tested for various duty cycle values,
input voltage and at different load values. Experimental waveforms of the converter for an input
of 15 V, D=0.60 and load resistance 12 Ω is shown in Fig. 9. The output voltage and current
waveforms are depicted in Fig. 9(a), which closely agree with the predicted theoretical voltage
gain. Inductor voltage and current waveforms are depicted in Fig. 9(b), which also closely agrees
with the theoretical value. Fig. 9(c) depicts the switch voltage and current, maximum current
through switch is 9 A and maximum voltage across the switch is 62 volts, which also agree with
the theoretical value. Coupling capacitor voltage and current are shown in Fig. 9(d), voltage
across coupling capacitor is 15 volts, which also agree the theoretical value. Voltage across diode
D1 and current are depicted in Fig. 9(e), voltage across the diode is 22 V and current is 2.4 A.
Voltage across the diodes D3, D4 and D6 and current are same as that of D1. Voltage and current
waveforms of diode D2 are shown in Fig. 9(f), voltage across the diode is 14.4 V and current is

10
2.4 A. Voltage across diodes D5 and current through it are same as that of D2. Due to the low
component stress on diodes and switch the proposed converter topology provides efficiency up
to 90 %.

(a) (b)

(c) (d)

(e) (f)

Figure. 9. Experimental results of the SI-SEPIC converter for an input of 15 V, duty cycle of
0.60 and time period of 20 μs (a) VO (10 V/division) and IO (5 A/division) (b) VL (5 V/division)
and IL (2 A/division) (c) Vq (20 V/division) and Iq (10 A/division) (d) Vcs (9 V/division) and Ics
(5 A/division) (e) VD1 (15 V/division) and ID1 (3 A/division) (f) VD2 (9 V/division) and ID2 (3
A/division).

8. Comparison between SI-SEPIC converter and Conventional SEPIC converter.

Comparison of the proposed SI-SEPIC converter with conventional SEPIC converter is provided
in this section.

8.1. Duty Cycle

For the same overall voltage conversion ratio, proposed SI-SEPIC converter operates at lower
duty ratio when compared to conventional SEPIC converter. Relation between duty ratios of the
proposed SI-SEPIC converter and conventional SEPIC converter is given in Eq. (8.1),

2
= = (8.1)
1− 1−

where, D and DC are duty ratios of SI-SEPIC and conventional SEPIC converter respectively.

Solving for D,

= (8.2)
2−

Figure. 10. DC voltage transfer function (M) versus ON switch duty cycle D for the continuous
conduction mode of operation.

11
 From Eq. (8.2) it is clear that SI-SEPIC converter operates with lower duty ratio for the same
voltage conversion ratios. Fig. 10 shows the plot of DC voltage transfer function (M) versus ON
switch duty cycle D for continuous conduction mode of operation of the proposed converter and
conventional SEPIC converter. From Fig. 10, it is clear that voltage conversion ratio of SI-
SEPIC converter is 200% more than the conventional SEPIC converter. For obtaining high
voltage conversion ratios, conventional SEPIC converter must operate with high duty ratios,
which in turn increases the current stress on output diode and results in severe reverse recovery.

8.2. Semiconductor stresses

As shown in Table 1, peak switching voltage and diode blocking voltage of SI-SEPIC converter
is lower than the conventional SEPIC converter.

Table. 1: Parameters of SI-SEPIC converter and conventional SEPIC converter.

As voltage gain M increases, the switch voltage stress of SI-SEPIC converter decreases up to
half the output voltage. But in case of conventional SEPIC converter, rate of decrease in switch
voltage stress with increase in M is smaller as compared to SI-SEPIC converter. Moreover, the
switch voltage stress equals to output voltage for high values of M. Hence, lower voltage rated
switches with small on state resistance can be used in SI-SEPIC converter, it reduces the
switching and conduction losses. Fig. 11 shows the plot of switch RMS current (IQrms) versus ON
switch duty cycle D for continuous conduction mode of operation of proposed converter and
conventional SEPIC converter. Average diode current for both the converter is equal to load
current IO while peak diode current of SI-SEPIC converter is less than the conventional SEPIC
converter. Peak switch current of the proposed converter is slightly greater than the conventional
SEPIC converter. However, conduction losses of the proposed converter will not be that much
high, since power switch in the proposed converter has lower voltage stress with lower on state
resistance.

Figure. 11. Switch RMS current (IQrms) versus DC voltage transfer function (M) for the continuous
conduction mode of operation.

8.3. Active Switch Utilization

Ratio of converter output power to total active switch stress (product of voltage across switch
and RMS current through switch) is defined as active switch utilization factor U. Active switch
utilization factor indicates how well converter utilizes the capabilities of switches to achieve
required output power. Converters with high switch utilization factor operate with higher
efficiency because for a given power, switching stress will be less. U factor for SI-SEPIC
converter is given in Eq. (8.3),

12
 M
U =2
(2 + M ) 3 (8.3)

For conventional SEPIC converter it is given by Eq. (8.4),

M
Uc =
(1 + M )3 (8.4)

Figure. 12. Switch utilization factor (U) versus DC voltage transfer function (M) for the continuous
conduction mode of operation.

Variation of active switch utilization factor U with voltage conversion ratio M is shown in Fig.
12. Maximum U for both the converter topologies is 0.385 and at M=0.7 U for both converter is
0.377. For voltage conversion ratios above 0.7 (M > 0.7), U is greater for the proposed SI-SEPIC
converter, switch is utilized much better in SI-SEPIC than the switch in conventional SEPIC
converter.

8.4. Output voltage ripple

Normalized output voltage ripple of SI-SEPIC converter can derived as given in Eq. (8.5),

Δv o T M
= s ( )
Vo RCo 2 + M (8.5)

Normalized output ripple voltage of conventional SEPIC converter is given in,

Δv o T M
= s ( )
Vo RCo 1 + M (8.6)

Figure. 13. Normalized output voltage ripple versus DC voltage transfer function (M) for the
continuous conduction mode of operation.

Variation in output voltage ripple with M is shown in Fig. 13. Output voltage ripple in SI-SEPIC
converter is less than that of conventional SEPIC converter, and the ripple current through
capacitor is also less. For a voltage gain of 5, output voltage ripple of SI-SEPIC converter is 0.71
V and for conventional SEPIC converter it is 0.81 V. Thus capacitor with low equivalent series
resistance (ESR) can be used in SI-SEPIC converter. Normalized ripple current through output
capacitors of the conventional and SI-SEPIC converter is given by Eq. (8.7) and Eq. (8.8)
respectively,

I co M
( )m =
Io 2 (8.7)

13
And,

I co
( )c = M
Io (8.8)

Figure. 14. Output current ripple versus DC voltage transfer function (M) for the continuous
conduction mode of operation.

Variation in capacitor ripple current for SI-SEPIC converter and conventional SEPIC converter
is shown in Fig. 14. It can be seen that the capacitor ripple current is also less in SI-SEPIC
converter as compared conventional SEPIC converter. For a voltage gain of 5, the output current
ripple of SI-SEPIC converter is 1.55 A, whereas for conventional SEPIC converter it is 2.20 A.

8.5. Input current ripple

Peak to peak ripple current of conventional SEPIC converter and SI-SEPIC converter is
proportional to duty ratio. Input ripple current of conventional and SI-SEPIC converter is given
by Eq. (8.9) and Eq. (8.10) respectively,

ΔiL1 RT 1
( )m = s ( )
Io L 2+M (8.9)

And,

ΔiL1 RT 1
( )c = s ( )
Io L 1+ M (8.10)

Figure.15. Input current ripple versus DC voltage transfer function (M) for the continuous
conduction mode of operation.

Variation in input ripple current with voltage gain M is shown in Fig. 15. It can be seen that the
input ripple current is also less in SI-SEPIC converter than the conventional SEPIC converter.
For a voltage gain of 5, input current ripple of SI-SEPIC converter is 0.1 A and 0.175 for
conventional SEPIC converter.

9. Conclusion

A detailed analysis of improved SEPIC converter topologies was carried out and it was found
that the SEPIC converters are suitable for renewable energy power tracking. Continuous
input/output energy flow, better efficiency, non inverted output voltage and ability to track
maximum power over entire load line of power characteristics are some of the advantages of
SEPIC converter. In this paper, a novel SEPIC converter with high gain is presented. Design and

14
stability analysis of a modified SEPIC converter has been explained in this paper. State space
averaging technique is used to develop transfer function of the converter for carrying out the
stability analysis. Bode plot, root locus, nyquist diagram and nichols chart of the proposed
converter have been presented. MATLAB was used to carry out the stability analysis. It was
found that the proposed converter is stable and causal. An experimental prototype of the
converter has been realized to verify the effectiveness of proposed converter. Theoretical and
experimental results show that SI-SEPIC converter is able to improve gain and is able to regulate
output voltage over wide range of input voltage. Proposed SI-SEPIC converter presents higher
circuit complexity than the conventional SEPIC converter. Also, advantages are higher static
gain for the operation with lower input voltage, lower switching stress, lower input and output
current ripple, lower output voltage ripple, and flexibility to use for non linear power tracking
applications.

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17
Appendix 1

Phase 1

Applying KVL in source side considering, L1, in Fig. 2,

= = (1.1)

From Eq. (1.1) ripple current through inductor L1,

(∆ ) = (1.2)

Similarly, ripple current through inductor L2,

(∆ ) = (1.3)

Applying KVL in coupling capacitor side by considering, L3,

= = (1.4)

From Eq. (1.4) ripple current through inductor L1,

(∆ ) = (1.5)

Similarly, ripple current through inductor L2,

(∆ ) = (1.6)

Voltage across the coupling capacitor Cs is,

= (1.7)

Comparing Eq. (1.2), Eq. (1.3), Eq. (1.5), Eq. (1.6) and Eq. (1.7),

(∆ ) = (∆ ) = (∆ ) = (∆ ) = (1.8)

where, = = = = ,

Applying KVL in the outer loop having diode, D,

+ + = 0 (1.9)

18
From (1.9) voltage across the diode, D is,

= −( + ) (1.10)

Voltage across diodes , , , and is,

= = = = 0 (1.11)

Voltage across diodes and is,

= = (1.12)

Current through switch, Q can be determined by applying KCL, and it is sum of all the inductor
currents given in Eq. (1.13), Since all the inductor currents are same, total current is,

=4 + (0) = 4 + (0) (1.13)

Current ripple in the inductor is,

∆ = ( ) − (0) = = (1.14)

where fS is the switching frequency.

Current through diodes D, and is,

= = = 0 (1.15)

Current through diodes, and is,

= = (1.16)

Current through diodes, and is,

= = (1.17)

Phase 2

Applying KVL in source side considering, L1,

= − − − = (1.18)

From Eq. (1.18) ripple current through inductor L1,

19
 − − −
(∆ ) = (1 − ) (1.19)

Similarly, ripple current through inductor L2,

− −
(∆ ) = (1 − ) (1.20)

Applying KVL in output loop considering inductor L3,

= − = (1.21)

From Eq. (1.21) ripple current through inductor L1,

−
(∆ ) = (1 − ) (1.22)

Similarly, ripple current through inductor L2,

−
(∆ ) = (1 − ) (1.23)

Since all the inductors have same the value voltage across inductors are,

= = = = (1.24)
2
Comparing Eq. (1.19), Eq. (1.20), Eq. (1.21), Eq. (1.22), Eq. (1.23) and Eq. (1.24),

(1 − )
(∆ ) = (∆ ) = (∆ ) = (∆ ) = (1.25)
2

Voltage across diodes D, and is,

= = = 0 (1.26)

Voltage across diodes , , , and is given in Eq. (1.26),

1
= = = =− (1.27)
2

Current through inductor is,

1
= + ( )=− ( − )+ ( ) (1.28)
2

20
Current ripple in the inductor is,

(1 − )
∆ = ( )− ( )=− ( − )= (1.29)
2 2

Current through diode D is,

=( + ) (1.30)

Current through diodes, , , , and is,

= = = = 0 (1.31)

Current through diode is,

= (1.32)

Current through diode is given in Eq. (2.42),

= (1.33)

Current and voltage waveforms

Continuous conduction mode operation of proposed SI-SEPIC converter can be divided

into two phases: 1) Parallel charging phase of the inductors when Q, , , , and , are ON
and diodes , , and D are OFF, as shown in Fig. 3(a). 2) Series discharging phase of the
inductors when Q, , , , and , are OFF and diodes , , and D are ON as shown in
Fig. 3(b). For analysis inductor currents are assumed to same, since voltage applied each
inductor has same value. Steady state current and voltages can derived as follows,
Current through the switch for a complete cycle is given in Eq. (1.34),

0 ≤ ≤
= (1.34)
0 ≤ ≤

RMS current through switch is given by,

√
= ( ) + 0 = (1.35)

21
Current through the switch for a complete cycle is given by,

0 0 ≤ ≤
= (1.36)
≤ ≤

RMS current through switch is given by,

= 0 + ( ) = (1.37)
√

Average current through switch is given is by,

= 0 + = (1.38)

Current through the diodes D1, D3, D4, D6 for one complete cycle is given by,

0 ≤ ≤
, , ,
= (1.39)
0 ≤ ≤

RMS current through diodes D1, D3, D4, and D6 is given is given by,

√
= ( ) + 0 = (1.40)

Average current through diodes D1, D3, D4, and D6 is given by,

= + 0 = (1.41)
( )

Current through the diodes D2 and D4 for one complete cycle is given by,

0 0 ≤ ≤
= (1.42)
≤ ≤

RMS current through diodes D2 and D4 is given by,

= 0 + ( ) = (1.43)
√

Average current through diodes D2 and D4 is given by,

22
 = 0 + =2 (1.44)

Current through output capacitance for one complete cycle is given by,

− 0 ≤ ≤
= (1.45)
≤ ≤

RMS current through output capacitance is given by,

DT T
1 D(1 + 3D)
I corms = (  ( I o )2 dt +  ( I in ) 2 dt ) = I o
T 0 1− D
DT (1.46)

Current through coupling capacitance for one complete cycle is given by,

− 0 ≤ ≤
= (1.47)
≤ ≤

RMS current through output capacitance is given by,

DT T
1 D(1 + 3D)
I csrms = (  ( I o )2 dt +  ( I in )2 dt ) = I o
T 0 1− D
DT (1.48)

Appendix 2

Circuit averaging method or state space averaging method can be used to model SI-SEPIC
converter. Here, state space averaging technique is used for modeling and perform analysis of SI-
SEPIC converter. Switching converter is approximated to be a continuous linear system in this
technique. It is difficult to model a non linear system and predict its behavior. Bode plot of the
linearized SI-SEPIC converter can be used to determine the feedback loop compensation
required to obtain desired steady state and transient performances. State space averaging
technique is used for this. As mentioned in section 2, operating modes of SI-SEPIC converter
can be divided into two, mode 1 when switch is turned ON, during this period inductors are
charged and stage 2 when switch is turned OFF, inductors discharges during this period.

State space equation for ON period (0 < t <DT) is given by Eq. (2.1) and Eq. (2.2),

= + (2.1)

= + (2.2)

And during OFF (DT < t <(1-D)T) period is given by Eq. (2.3) and Eq. (2.4),

X = A x + B u (2.3)

23
 = + (2.4)

Equations corresponding to both modes are time weighted and averaged to produce average
description of the converter over entire switching period (Ts). Averaged equation of the converter
over a complete switching cycle is given in Eq. (w) and Eq. (x),

= + (2.5)

= + (2.6)

where,

System matrix, = + (1 − )

Input matrix, = + (1 − )

Output matrix, = + (1 − )

Direct transmission matrix, = + (1 − )

From the above equations it is clear that output voltage can be controlled by varying duty cycle.
The duty cycle of SI-SEPIC converter can be varied by using a controller and the circuit can be
made to reject the disturbances.

24
Appendix 3

Figure showing the converter connected to controller and CRO.

25
Figure. 1. Circuit diiagram of im
mproved sw
witched inducctor SEPIC converter.

Circuit diagrram for Phaase 1, when sswitch is ON

Figure. 2. C N.

26
Figure. 3. Circuit diagraam for Phasse 2, When sswitch is OF
FF.

Figurre.4. Bode pplot of the proposed connverter.

27
Figure. 5. Nyquist diagram of the proposed converter.

Figure. 6. Nichols chart of the proposed converter.

28
 Figure. 7. Root locus plot of the proposed converter.

Figure. 8. Experimental setup of SI-SEPIC converter.

29
 (b) (b)

(c) (d)

(e) (f)

Figurre. 9. Experiimental resuults of the SII-SEPIC connverter for an

a input of 15 V, duty cycle
c of
0.60 annd time periood of 20 μs (a) VO (10 V/division) and IO (5 A/division)
A ((b) VL (5 V//division)
and IL (2
( A/divisioon) (c) Vq (220 V/divisioon) and Iq (10 A/division) (d) Vcs (99 V/divisionn) and Ics
(5 A/ddivision) (e)) VD1 (15 V
V/division) annd ID1 (3 A//division) (ff) VD2 (9 V/division) annd ID2 (3
A/divisionn).

30
Figure.. 10. DC volltage transfeer function ((M) versus ON switch duty cycle D for the coontinuous
conductiion mode off operation.

Table. 1: P
Parameters oof SI-SEPIC
C converter and convenntional SEPIIC converterr.

Parameteer SI-SEPIC Converter

C SEPIC Coonverter
2+ M 1+ M
Peak switch volttage 2MM M
Switcch RMS currrent M (2 + M ) M (1 + M )
2+ M 1+ M
Peak diode voltaage M
2M M
M
Diodee RMS currrent 1+
2 1+ M
Averaage diode ccurrent 1 1

31
Figure. 11. Switch RMS current (IQrms) versus DC voltage transfer function (M) for the continuous
conduction mode of operation.

Figure. 12. Switch utilization factor (U) versus DC voltage transfer function (M) for the continuous
conduction mode of operation.
32
Figure. 13. Normalized output voltage ripple versus DC voltage transfer function (M) for the
continuous conduction mode of operation.

Figure. 14. Output current ripple versus DC voltage transfer function (M) for the continuous
conduction mode of operation.

33
Figure.15. Input current ripple versus DC voltage transfer function (M) for the continuous
conduction mode of operation.

34