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Proceedings of the IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI Systems Design (ISVLSI’04) 0-7695-
2097-9/04 $20.00 © 2004 IEEE
with five stages has a critical path delay of 0.98 ns. In
comparison, a 64-bit Kogge-Stone binary adder has an
area of 0.063 mm2 and a critical path delay of 0.60 ns
when implemented using the same design constraints and
standard cell library.
4. Conclusions
Proceedings of the IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI Systems Design (ISVLSI’04) 0-7695-
2097-9/04 $20.00 © 2004 IEEE