Ic (Digital & Analog) Lab Manual by A.darwin Jose Raju

Integrated Circuits Lab IC-01
Integrated Circuits
Lab Manual
Prepared By
A.DARWIN JOSE RAJU, M.E., SMIEEE,
Senior Lecturer
Electrical and Electronics Engineering,
St.Xavier’s Catholic College of Engineering,
Kanyakumari District,
Pin Code 629807.
Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

Exp. No. : 1 Date :
STUDY OF LOGIC GATES
AIM:
To familiarize with logic gate IC packages and to verify the truth tables of
the logic gates. Also to familiarize with the digital IC trainer kit.
COMPONENTS AND EQUIPMENTS REQUIRED:
Sl.No. Items Range Quantity

1 Power Supply (0-05)V 1
2 7400 IC 1
3 7402 IC 1
4 7404 IC 1
5 7408 IC 1
6 7432 IC 1
7 7486 IC 1
8 Resistor 330 Ohm 1
9 LED 1
9 Bread Board 1
10 Wire Required
11 IC Trainer Kit 1
TROUBLESHOOTING WITH DIGITAL ICs:
Experiments with digital integrated circuits are rather easy compared

with analog integrated circuits. Operator must be cautious about the connecting
wires and pins of the IC. In most of the logic gate ICs pin no.7 is GND and pin
no.14 is Vcc. But this is not the case with all digital ICs. There is a chance that
the operator may commit mistake by taking for granted that pin nos.7 and 14
are Vcc and GND respectively for all pin ICs.

AND GATE
A B Z OB
0 0 0
0 1 0
1 0 0
1 1 1
OR GATE
A B Z OB
0 0 0
0 1 1
1 0 1
1 1 1

THEORY:
LOGIC GATES:
In digital electronics, a gate is a logic circuit with one output and one or
more inputs. Logic gates are available as integrated circuits (ICs).
AND GATE:
The AND gate performs logical multiplication, more commonly known as

AND function. The AND gate output will be in high state when all the inputs are
in high state.
7408 is a digital IC in TTL family which contains four AND gates. For
this reason, it is called quad two input AND gate. Every AND gate has two inputs
in this dual-in-line package (DIP). Pin 14 is the supply pin. For TTL devices to
work properly, the supply voltage level must be between +4.75 V and +5.25 V.
This is why +5 V is the nominal supply voltage specified for all TTL devices. Pin 7
is a common ground for the chip. The other pins are for inputs and outputs.
OR GATE:
It performs logical addition. Its output will become high if any of the
inputs is in logic high. 7432 is a quad two input OR gate.
NOT GATE:
It performs a basic logic function called inversion or complementation.

The purpose of the inverter is to change one logic level to opposite level. IC
7404 is a hex inverter(means six inverters in the DIP).

NOT GATE
A Z OB
0 1
1 0
NAND GATE
A B Z OB
0 0 1
0 1 1
1 0 1
1 1 0

NAND GATE:
A NOT gate following an AND gate is called NOT-AND or NAND gate.

Its output will be low if all the inputs are in high state. 7400 IC is a quad two
input NAND gate.
NOR GATE:
A NOT gate following an OR gate is called NOT-OR or NOR gate. Its

output will be low if all the inputs are in high state. 7402 IC is a quad two input
NOR gate.
EXOR GATE:
Its output will be high if and only if one input is in high state.7486 is
aa quad two input EXOR gate.
PROCEDURE:
1. Test all the components and IC packages using a digital IC tester. Also
assure whether the connecting wires are in good condition by checking for the
continuity using a Multimeter or a trainer kit. Continuity of wires can be tested
using a trainer kit by shorting a 5 V supply in the trainer to an LED of the panel.
If wires are good, LED will glow.
2. Verify the dual-in-line package (DIP) pin out of the IC before feeding the
inputs.
3. Set up the circuits and observe the outputs. Enter the input and output states
in truth table corresponding to the input combinations.

NOR GATE
A B Z OB
0 0 1
0 1 0
1 0 0
1 1 0
EXOR GATE
A B Z OB
0 0 0
0 1 1
1 0 1
1 1 0

IC TRAINER KIT:
IC trainer kit is mainly used to test and implement digital circuits.

Integrated circuits can be fitted in sockets or breadboard provided in it. The
associated circuits can be set up on the breadboard. There are built-in voltage
source and clock signals in it. The frequency of clock can be selected by turning
the knob into different positions. In order to feed monopulses manually, a
debouncer switch is also provided. So many select-switches are provided to
obtain 0 or 1 state voltages for digital inputs. Green and red LEDs are provided
to represent low and high states respectively to visualize the digital outputs.
RESULT:
Roll No. Submission Date Marks Remarks Staff Signature

Exp. No.: 2 Date:
REALISATION OF FLIPFLOPS
AIM:
1. To realize different types of Flip flops using logic gates and to verify
their truth tables.
2.To familiarize with flip flop ICs 7473 , 7474,7476
Sl. No. Items Range Quantity

1 Power supply (0-05)V 1
2 Function Generator 1
3 IC 7400 1
4 IC 7402 1
5 IC 7476 1
6 IC 7404 1
8 LED Different colors 2
9 Bread Board 1
10 Connecting Wires Required
THEORY:
Flip flop is a simple two state device capable of storing single bit of
information. A flip flop has two outputs. One for normal value and other for
complemented value. Flip flops are also called as latches. They are the main
storage devices in sequential logic circuits.

SR FLIP FLOP
1 4
3 6 330 ohm
UA
S 2 5 UB
Q
9 12
11 330 ohm
UC 8
R 10 13 UD
Q'
UA – UB → 7400 G
Output
Input
Theoretical Practical
1
R S Q Q Q Q1
0 0 No Change
1 0 0 1
0 1 1 0
1 1 For Bidden
SR FLIP FLOP Using NOR Gates
S 2
330 ohm
UA 1
3
Q
5
4 330 ohm
R UB
6
Q'
UA – UB → 7402
G
CLOCKED SR FLIP FLOP
S 1 4
3 6 330 ohm
UA
2 5 UB
Q
C/K G
9 12
11 330 ohm
UC 8
R 10 13 UD
Q'
UA – UB → 7400
G
Output
Input
1
CK R S Q Q Q Q1
0 0 No Change
1 0 0 1
0 1 1 0
1 1 For Bidden

Basic Flip flop:
Basic flip flop operates in asynchronous mode. It can be constructed from
two NAND gates or two NOR gates. It has two control inputs namely set unit and
reset unit. This flip flop is also known as direct coupled RS Flip flop.
Clocked SR Flip flop:
‘S’ and ‘R’ stands for set and reset. There are four input
combinations possible at the inputs. But S=R=1 is forbidden since the output
will be indeterminate. When the FF is switched ON its output state will be
uncertain. When the initial state is to be assigned, two separate inputs called
preset and clear are used. They are active low inputs.
JK Flip flop:
The indeterminate output state of SRFF when S=R=1 is avoided by
converting it to a JK FF.
Master Slave JK Flip Flop:
The race around condition of JKFF is rectified in master slave
JKFF. Racing is nothing but the toggling of the output more than once during a
positive clock edge. MSJKFF is created by cascading two JKFFs. The clock fed
to the first stage (Master) is inverted and fed to the second stage (Slave). This
enables that the slave follows the master eliminating the chance of racing.

D FLIP FLOP
D 330 ohm
2
4 J S Q 15
1 CP _
C/K 16 K Q 14
G
1
R 330 ohm
3
2
74LS76
1/6 7404 G
Output
Input
1
D Q Q Q Q1
0
1
T FLIP FLOP
T
330 ohm
7
9 J S Q 11
C/K 6 CP _
12 K Q 10
330 ohm G
R
8
74LS76
G
Output
Input
1
T Q Q Q Q1
0
1

D Flip Flop:
It has only one input referred to as D input or data input. The

input data appears at the output after a clock pulse is applied. DFF can be
derived from JKFF by using J input as the D input and J is inverted and fed
to K input.
T Flip Flop:
T stands for ‘toggle’. The output toggles when a clock pulse is

applied. That is,the output of the flip flop changes state for an input pulse. TFF
can be derived from JK Flip Flop by shorting J and K inputs.
Flip Flop ICs:
7476 is dual negative edge triggered MSJKFF with preset and

clear facility. It is a 16-pin DIP chip.7473 is a is dual negative edge triggered
MSJKFF with clear facility in 14-pin DIP. It does not have preset input. 7474 is
positive edge triggered dual DFF with 14 pin DIP.
PROCEDURE:
1. Test all components and IC packages using multimeter and digital IC

tester.
2. Set up the FFs using gates and verify their truth tables.
3. Verify the truth tables of D Flip flop and T Flip flop using 7476 ICs.
RESULT:

Exp. No.: 3 Date:
CODE CONVERTERS
AIM:
To design and set up the following circuits.
1. A four-bit binary to Gray code converter.
2. A four-bit Gray to Binary code converter.
1 Power supply (0-05) V 1
2 IC 7486 1
5 Bread Board 1

FOUR BIT BINARY TO GRAY CODE CONVERTER
B0 U1C G0
10 330 ohm
8
9
G
B1 U1B
5 330 ohm
6 G1
4
G
B2 U1A
2 330 ohm
3
1 G2
G
B3 330 ohm
G3
Tabulation:
Gray Code
Binary Code
B3 B2 B1 B0 G3 G2 G1 G0 G3 G2 G1 G0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

THEORY:
Binary to Gray code
To convert a binary number to corresponding Gray code, the following rules
are applied.
1. The MSB in the Gray code is the same as the corresponding digit in a
binary number.
2. Going from left to right, add each adjacent pair of binary digits to get the
next Gray code digit. Disregard carries.
As the first step to design a binary to Gray code converter, set up a
truth table with binary numbers B3 B2 B1 B0 and corresponding Gray code
numbers G3 G2 G1 G0. Set up a circuit realizing the simplified logic expressions
obtained using K maps for Gs as the functions of Bs.

FOUR BIT GRAY TO BINARY CODE CONVERTER
G0 U1C
10
B0
330 ohm
8
9
G
G1 U1B
5 330 ohm
6 B1
4
G
G2 U1A
2 330 ohm B2
3
1
G3 330 ohm
B3
G
Tabulation:
Binary Code
Gray Code
G3 G2 G1 G0 B3 B2 B1 B0 B3 B2 B1 B0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Gray to Binary code
To convert from Gray code to binary, the following rules are applied.
1. The most significant digit in the binary number is the same as the
corresponding digit in the Gray code.
2. Add each binary digit generated to the Gray code digit in the next
adjacent position. Disregard carries.
To design the Gray to binary code converter, set up the truth table
and get simplified expressions using Karnaugh maps for each binary bits as a
function of Gray code number differs from the preceding number by a single
bit.
PROCEDURE:
1. Test all the components and IC packages using Multimeter and digital IC
tester.
2. Verify the truth tables of the circuit by feeding the input bit combinations.
RESULT:

Exp. No.: 4 Date:
MULTIPLEXER AND DEMULTIPLEXER
AIM:
To design and study the operation of a Multiplexer and
Demultiplexer circuit.
APPARATUS AND COMPONENTS REQUIRED:
2 IC 7411 2
3 IC 7432 1
4 IC 7404 1
7 Bread Board 1

Pin Diagram:
Circuit Diagram:
S1 So
7404 7404
1 2 3 4
74LS11
Do 1
2 12
13 74LS32
1
3
2
74LS11
3
D1 4 6
5 74LS32
9 330 ohm
8
10
74LS11
9
D2 10 8 G
11 74LS32
4
6
5
74LS11
D3 1
2 12
13
Tabulation:
Data Select Input Output

Input S1 S0 Theoretical Practical
D0 0 0 D0
D1 0 1 D1
D2 1 0 D2
D3 1 1 D3

THEORY:
Multiplexer:
The term multiplex means “many into one”. Multiplexing is the process of
transmitting a large number if information over a single line. A digital
multiplexer (MUX) is a combinational circuit that selects one digital information
from several sources and transmits the selected information on a single output
line. A multiplexer is also called a data selector since it selects one of many
inputs and steers the information to the output.
The multiplexer has several data input lines and a single output line. The
selection of a particular input line is controlled by a set of selection lines. The
selection lines decide the number of input line of a particular multiplexer. If the
number of n input lines is equal to 2m, then m select lines are required to select
one of the n input lines. For eg., to select 1 out of 4 input lines, two select lines
are required to select 1 of 8 input lines three select lines are required and so on.
4 to 1 multiplexer has four data input lines ( D0- D3 ) , a single output

line (y) and two select lines ( S0 and S1 ) to select one of the four input lines.

Circuit Diagram:
D S1 S2
7404 7404
1 2 3 2
74LS11
1 330 ohm
2 12
13
G
74LS11
3 330 ohm
4 6
5
G
74LS11
9 330 ohm
10 8
11
G
74LS11
1 330 ohm
2 12
13
Tabulation:
Input Select Output

Input
D S1 S0 Y3 Y2 Y1 Y0
1 0 0
1 0 1
1 1 0
1 1 1

Demultiplexer
The word “demultiplex “means one into many. Demultiplexing is the

process of taking information from one input and transmitting the same
over one of several outputs.
A demultiplexer is a logic circuit that receives information on a

single input and transmit the same information over one of several ( 2n )
out put lines. It has one input signal, m select signals and n output signal.
The select inputs determine to which output the data input will be
connected. As the serial data is changed parallel data, ie. The input
caused to appear on one of the n output lines, the demultiplexer is also
called a distributor or a serial – to – parallel converter.
1 – to – 4 demultiplexer has a single input (D), four outputs ( Y0 to

Y3 ) and to select inputs ( S1 and S0 ).
PROCEDURE:
(i) Test the ICs using a digital IC tester before conducting the
experiment.
(ii) Connections are made as per the circuit diagram.
(iii) Verify the truth tables of the circuit by feeding the inputs.
RESULT:

Exp. No.: 5 Date:
ASYNCHRONOUS COUNTERS
AIM:
To set up following asynchronous counters and study their working.

1. 4 bit binary up counter (mod 16)
2. 4 bit binary down counter

3 IC 7476 2
6 Bread Board 1
THEORY:
A counter is a circuit that produces a set of unique output combinations
in relation to the number of applied input pulses. The number of unique outputs
of a counter is known as its modulus or mod number.
In asynchronous counters, the flip flops are not given the clock
simultaneously. Therefore the propagation delay increases with the number of
flip flops used. Four JK flip flops must be used in toggle mode to count 16 states
(JKFF can be converted to TFF by shorting J & K inputs).

FOUR BIT BINARY UP COUNTER
Circuit diagram:
Qo Q1 Q2 Q3
330 ohm 330 ohm 330 ohm 330 ohm

5V
S S S S
clock J Q J Q J Q J Q
CP _ CP _ CP _ CP _
K Q K Q K Q K Q
R R R R
1/2 7476 1/2 7476 1/2 7476 1/2 7476
5V
Tabulation:
OUT PUT
Clock
Pulse
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

4 Bit Binary Up Counter (Ripple Counter):
In the circuit set up, all flip flops are clocked by the Q output of the
preceding flip flop. JK inputs of all the flip flops are connected to a high state.
7476 is a dual JK Master Slave flip flop with preset and clear. A ripple counter
comprising of n flip flops can be used to count up to 2n pulses. A four flip flop
circuit gives a maximum cunt of 24 =16. The counter gives a natural binary
count from 0 to 15 and resets to initial condition on 16th input pulse.
With the application of the first clock pulse Q0 changes from 0 to 1.
Q1,Q2 and Q3 remains unaffected. With second clock pulse, Q0 becomes 0 and Q1
becomes 1. At the arrival of 15th clock pulse all the Q outputs will become 1.At
the 16th clock pulse all Q outputs become reset and cycle repeats.
4 Bit Binary Down Counter (Ripple Counter):
In this circuit, the succeeding flip flops are clocked by the Q output of
preceding flip flops. The outputs are taken from Q outputs. Initially all output
are set. At the arrival of 16th clock pulse all q outputs becomes reset and cycle
continues.

FOUR BIT BINARY DOWN COUNTER
Circuit diagram:
Qo Q1 Q2 Q3
330 ohm 330 ohm 330 ohm 330 ohm

5V
S S S S
clock J Q J Q J Q J Q
CP _ CP _ CP _ CP _
K Q K Q K Q K Q
R R R R
1/2 7476 1/2 7476 1/2 7476 1/2 7476
5V
Tabulation:
OUT PUT
Clock
Pulse
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0
0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0

PROCEDURE:
1. Test all ICs using a digital tester. Also test all the wires for continuity
using a Multimeter or IC trainer. In IC trainer, by shorting any supply
point to an LED the continuity of a wire can be verified.
2. Set up the circuit for 4 bit ripple counter. Connect all the PRESET pins to
+5V to disable it.
3. Tie up all CLEAR pins together.
4. Use monopulse/debouncer to feed the clock manually.
5. Clear all FFs initially connecting common CLEAR to logic low input. After
the usage of CLEAR pins it opens. Apply monopulses. Counter starts
counting up. (Before setting up the down counter, shift the output LEDs to
Q¯ outputs and repeat steps 2 to 5. The down counting can be observed).
6. Move clock inputs of every flip flop except FF0 from Q outputs to the
Q ¯ outputs. Preset all FFs. Apply monopulses. Counter will start counting
downwards.
Note:
1. CLEAR and PRESET are active low inputs.After the use of these pins
either connect them to logic high or keep them open.
2. Select 7476 instead of 7473 if the presetting is required.
RESULT:

Exp. No.: 6 Date:
BASIC OPERATIONAL AMPLIFIER CIRCUITS
AIM:
To design and set up the following basic operational amplifier circuits.
(i) Zero crossing detector
(ii) Inverting amplifier
(iii) Non-inverting amplifier
(iv) Voltage follower
COMPONENTS AND APPARATUS REQUIRED:
1 Dual Power Supply (0-15)V 1
3 CRO 1
4 Op-amp LM741 1
5 Resistor 1K 2
6 Resistor 10K 1
7 Resistor 2K 1
8 Bread Board 1

Zero Crossing Detector
Circuit Diagram: Pin Diagram:
+15V
Vo
741
100mVpp=Vin
-15V
G
G
Model Graph
Vin
50mV
Vo
+Vsat
-Vsat
Tabulation
Time
No. of Amplitude Time/Div. No. of Frequency
Amp./Div. Period
Division (Volts) Division (Hz)
(ms)
Input
Output

THEORY:
Zero Crossing Detector:
It is a comparator which switches from OFF to ON when input crosses zero
reference voltage. An inverting comparator used as zero crossing detector is
shown in Fig.. That is, the output is driven into negative saturation when the
input signal passes through zero in positive direction. Conversely, when input
signal passes through zero in the negative direction, the output switches and
saturates positively. This circuit can be used as an easy technique to check
whether the op-amp is in good condition.
PROCEDURE:
(i) Setup the circuit shown in fig.
(ii) Apply an input signal of 100mVpp and 1 KHz to the inverting input.
(iii) Observe whether the output is a square wave swinging from
+Vsat to –Vsat.

Inverting Amplifier
Circuit Diagram
Rf
+15V
Ri
Vo
741
1 k
2Vpp=Vin
-15V
Model Graph
Vi
+1V
Vo
+V
-V
Tabulation Ri =
Input Theoretical Output Practical

Sl.No. Rf
(Volts) Gain (Volts) Gain
1
2
3

Inverting Amplifier:
This is one of the most popular op-amp circuits. The polarity of the input
voltage gets inverted at the output. If a sine wave is fed to the input of this
amplifier, the output will be an amplified sine wave with 180 degree phase shift.
The gain of the inverting amplifier is given by the expression A=Rf/Ri where Rf is
the feed back resistance and Ri is the input resistance.
Inverting amplifier can be used as a scalar because by varying either Rf or
Ri amplitude of the output can be varied.
PROCEDURE:
(i) Set up the circuit shown in fig. with Ri=1K, Rf=10K
(ii) Apply an input signal of 2Vpp and 1KHz to the inverting input.
Observe the output voltage Vo and input signal Vs on the dual
channel oscilloscope. Measure the peak voltages.
(iii) Repeat the measurements of Vo for Rf=10K.
(iv) Calculate the voltage gain.

Non Inverting Amplifier
Circuit Diagram
Rf
+15V
Ri
Vo
741
1 k
G -15V
2Vpp=Vin
G
Model Graph
Vi
+1V
Vo
+V
-V
Tabulation Ri =
Input Theoretical Output Practical

Sl.No. Rf
(Volts) Gain (Volts) Gain
1
2
3

Non-Inverting Amplifier:
This circuit provides a gain to the input signal without any change in
polarity. The gain of the non-inverting amplifier is given by the expression
A= 1+Rf/Ri, where Rf is the feedback resistance and Ri is the input resistance.
PROCEDURE:
(i) set up the circuit shown in Fig. with Ri=1K, Rf=10K
(ii) Apply an input signal of 2Vpp and 1KHz to the inverting input. Observe
the output and input waveforms on the dual channel oscilloscope.
Measure the peak voltages.
(iii) Repeat the measurements of Vo for Rf=10K.
(iv) Calculate the voltage gain.

Voltage Follower
Circuit Diagram
+15V
Vo
741
-15V
Vin
Model Graph
Vi
+1V
Vo
+V
-V
Tabulation
Time
Amp./ No. of Amplitude Time/ No. of Practical Theoretical
Period
Division Division (Volts) Division Division Gain Gain
(ms)
Input
Output

Voltage Follower
Doing a slight change in non-inverting amplifier circuit, we can make a
voltage follower circuit. The name voltage follower came from the fact that
output is the replica of the input (ie) unity gain and no change in polarity. This
circuit will provide very high input impedance. It is used as a buffer to connect a
high impedance signal source to a low impedance load.
PROCEDURE:
(i) Setup the circuit shown in Fig. with Ri=1K, Rf=10K
(ii) Observe the output and input waveforms and calculate the gain.
NOTE:
(i) Take care to switch on V+ and V- supplies before switching on input
signal sources.
(ii) Take care to switch off the V+ and V- supplies.
RESULT:

Exp. No.: 7 Date:
ASTABLE MULTIVIBRATOR
(SQUARE WAVE GENERATOR)
AIM:
To design and set up an Astable Multivibrator using op-amp for a

frequency of oscillation of 1 KHz, & to compare the theoretical frequency with
observed frequency by varying the capacitance value.
APPARATUS AND COMPONENTS REQUIRED:

1 Dual Power supply (0-15) V 1
2 Resister 100k 2
3 Resistor 2.2k 1
4 DCB 1
5 Op-amp LM 741 1
6 CRO 1
7 Bread Board 1
FORMULA:
Time, T = 2 RC ln (1+β/1- β)
Where β = R2/R1+R2

DESIGN:
Specification:
F = 1KHZ Therefore T = 1ms
Time period T = 2 RC ln [ 1+β / 1- β ] __________ (i)
Where β = R2 / R1+ R2
Let β = 0.5 Therefore R 1 = R2
Take R1 = R2 = 100 KΩ
Substitute β value in equn (i)
T = 2RC ln 3
= 2 RC 1.1 _______________ (ii)
Let C = 0.2 µF
Substitute C and T values in equn. (ii)
1x10-3 = 2.2R x 0.2 x 10-6
R = 1 x 10-3 / 2.2 x 0.2 x 10-6
R = 2272 Ω
Select R = 2.2 KΩ

THEORY:
The output of the op-amp is forced to swing repetitively between positive
saturation +Vsat and negative saturation –Vsat resulting in square wave output.
This circuit is also called as free running multivibrator or square wave generator.
The output of the op-amp will be in positive saturation if differential input
voltage is negative and vice versa. The differential voltage Vd = Vc - Vsat where
 is the feedback factor. Vo is the potential at non inverting terminal of op-amp.
Working Of The Circuit:
Consider the instant at which Vo = +Vsat. Now the capacitor charges
exponentially towards +Vsat through R. Automatically Vd increases and crosses
zero. This happens when Vc = + Vsat. The moment Vd becomes positive due to
further charging of the capacitor, output changes to –Vsat. Now capacitor starts
to discharge to zero and recharges towards –Vsat. Now Vd decreases and crosses
zero. This happens when Vc = Vsat. The moment Vd becomes negative again,
output changes to +Vsat. This completes one cycle.
The time period T of the square wave is T = 2 RC ln (1+β/1- β)
If β is made ½, T = 2.2 RC
This astable multivibrator is particularly useful for the generation of
frequency in the audio frequency range. Higher frequencies are limited by the
delay time and slew rate of the op-amp.

Circuit Diagram
R
2.2 k
+15V
Vo
741
C -15V R1 100 k
R2 100 k
G G
Model Graph
Amp
Vo
+ Vsat Vc
+ Vsat
Time
- Vsat
- Vsat
Tabulation
Capacitor Time/ Time Frequency Frequency

Amp. No. of Amplitude No. of
value C in Div. Period (Hz) (Hz)
/Div. Division (Volts) Division
µf (ms) (ms) (Pract.) (Theoret.)
0.1
0.2
0.3

PROCEDURE:
1. Connections are made as shown in circuit diagram.
2. The output square waveform is traced and its frequency is checked for
various value of capacitance.
3. The voltage across the capacitance Vc is also traced.
4. The output waveforms are plotted in the graph.
RESULT:

Exp. No.: 8 Date:
WIEN BRIDGE OSCILLATOR
Aim:
To design and study the operation of Wien Bridge Oscillator and to

compare the theoretical frequency with observed frequency.
Components And Apparatus Required:
1 Dual Power supply (0-15) V 1
2 Resistor 2.2k 2
3 Capacitor 0.1μf 2
4 Potentiometer 10k 1
5 Op-amp LM 741 1
6 CRO 1
7 Bread Board 1

Design:
Specification:
Frequency of oscillation = 750 Hz
Fo = 1/2RC Hz Let C = 0.1μf
R = 1/2x 750 x 0.1x 10 -6

= 2122.06Ω
Choose R = 2.2K Ω
Gain 1+Rf/Ri = 3 Let Ri = 1K then Rf = 2K
Circuit Diagram:
2.2 k
0.1μf
0.1uF +15V
Vo
741
-15V
2.2 k 0.1μf
0.1uF
10k
G G

Formula:
The frequency of oscillation is theoretically given by f= 1/2RC Hz
THEORY:
This is an audio frequency oscillator of high stability and simplicity.
The feedback signal in this circuit is connected to the non-inverting input
terminal so that the op-amp is working as a non-inverting amplifier. Therefore,
the feedback network need not provide any phase shift. The circuit can be
viewed as a Wien bridge with a series RC network in one arm and parallel RC
network in the adjoining arm. Resistors Ri and Rf are connected in the remaining
two arms. The condition of zero phase shift around the circuit is achieved by
balancing the bridge. The frequency of oscillation is the resonant frequency of
the balanced bridge and is given by the expression fo=1/2RC.
From the analysis of the circuit, it can be seen that the feed back factor
β=1/3 at the frequency of oscillation. Therefore, for the sustained oscillation, the
amplifier must have a gain of 3.

Model Graph:
Amp
Vm
Time
Tabulation:
Time Practical
No. of Amplitude Time/Div. No. of
Amp./Div. Period Frequency
Division (Volts) Division
(ms)

PROCEDURE:
(i) Connections are made as shown in fig.
(ii) The middle terminal of the potentiometer connected to the inverting
input terminal of the op amp.
(iii) The output is given to the CRO. The sine wave is generated by varying
the potentiometer.
(iv) Note down the time period and calculate the frequency.
RESULT:
Wien bridge oscillator is designed, constructed and observed

frequency is compared with theoretical frequency.
Theoretical Frequency = -------------- Hz

Practical Frequency = -------------- Hz

Exp. No.: 9 Date:
HWR AND FWR USING OP-AMP
AIM:
To set up and study a half wave rectifier and full wave rectifier using Op-
Amp.

3 CRO 1
4 Op-amp LM741 2
5 Resistor 1.2 K 4
6 Diode IN4001 2
7 Bread Board 1
Pin Diagram:

Half Wave Rectifier
Circuit Diagram:
Vin
Model Graph:
Vin
50mV
V1
-50mV
50mV
V2 t

THEORY:
Half Wave Rectifier
An inverting voltage follower can be converted into an ideal half wave
rectifier by adding two diodes as shown in figure. When Vin is positive, Vo
becomes negative and the diode D1 gets forward biased. At this moment, diode
D2 is reverse biased. When Vin becomes negative, Vo becomes positive and
diode D2 gets forward biased. If a sinusoidal wave is applied at Vin, output V1
gives positive going ripples and V2 gives negative going ripples.
PROCEDURE:
1. Verify whether the op-amp is in good condition by wiring it as ZCD or
voltage follower.
2. Set up half wave rectifier and feed 100 mVpp, sine wave at the input.
3. Observe the negative going and positive going half cycles of the output.
4. Observe the transfer characteristics by feeding Vin and V1 to X and Y
channels of CRO, keeping it in transfer characteristics mode.
5. Repeat step no. 4 by feeding Vin and V2.

FULL WAVE RECTIFIER
Circuit Diagram:
Vin
Model Graph:
Vin
50mV
-50mV
50mV
Vo t

Full Wave Rectifier
This circuit is also called absolute value circuit. Here amplifier A1
works as an inverting amplifier always and A2 works in two modes depending
upon the polarity of input voltage; one in inverting mode and other in the non-
inverting mode.
When Vin is positive, diode D1 conducts and diode D2 does not
conduct. A close examination will prove that both the amplifiers are functioning
in inverting mode. When Vin becomes negative, D1 turns off and D2 turns on.
The equivalent circuit diagram will show that A1 works as inverting amplifier and
A2 works as non-inverting amplifier. So irrespective of the polarity of input
voltage, output Vo turns to be positive always.
PROCEDURE:
1. Verify whether the op-amp is in good condition by wiring it as ZCD or

voltage follower.
2. Set up the full wave rectifier and feed 100 mVpp, sine wave at the
input.
3. Observe the input and output waveforms simultaneously on CRO
screen.
RESULT:

Exp. No.: 10 Date:
MONOSTABLE MULTIVIBRATOR USING 555IC
AIM :
To design a monostable multivibrator using 555 timer for a pulse width
of 1ms.
.
3 CRO 1
4 Timer LM555 1
5 Resistor 480ohm 1
6 Resistor 10k 1
7 Capacitor 0.01 μf 1
8 Capacitor 0.1μf 1
9 Diode IN4001 1
10 Bread Board 1

Design:
Let Vcc = 10V and T = 1ms
We have, T = 1.1 RC.
Let C = 0.1µf. Then R = 10 K
Design of triggering circuit
We have RiCi ≤ 0.0016Tt
where Tt is the time period of the trigger.
Let Tt = 3 msec
and Ci = 0.1µf.
Then Ri = 480 Ω. Choose Ri = 470 Ω
Choose Ci = 0.1µf
Pin Diagram:

THEORY:
In the stable state Q is high and in turn, Q1 is turned ON and output is
very low. When the negative going trigger passes through Vcc/3, the FF is set i.e.
Q = 0. This makes transistor Q1 off. The capacitor starts charging towards Vcc,
which was earlier clamped to zero. After a time period, the capacitor voltage is
greater than (2/3)Vcc and thereby discharging the capacitor C rapidly to ground
potential. The out put returns to the stable state.
The time duration of quasi-stable is given by the equation, T = 1.1 RC
seconds.
Though it is possible to apply the trigger pulse directly to pin 2, trigger
shown in figure is better, because it makes narrow trigger pulses applied to
trigger terminal. Also it prevents the possibility of mistriggering the monostable
multivibrator on positive pulse edges.

Circuit Diagram
Model Graph
Trigger 10V
Vo
Vc

PROCEDURE:
1. Set up the circuit after verifying the condition of the IC using analog IC
tester.
2. Use positive pulses of amplitude Vcc and frequency 300Hz as the
trigger.
3. Observe the waveforms at pin numbers 3 and 6 of the chip.
4. If pulse generator is not available, use square wave generator.
RESULT:

THANK YOU

Ic (Digital & Analog) Lab Manual by A.darwin Jose Raju

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Integrated Circuits Lab IC-01

A.DARWIN JOSE RAJU, M.E., SMIEEE,

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

Exp. No. : 1 Date :

STUDY OF LOGIC GATES

COMPONENTS AND EQUIPMENTS REQUIRED:

Sl.No. Items Range Quantity

TROUBLESHOOTING WITH DIGITAL ICs:

Experiments with digital integrated circuits are rather easy compared

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

The AND gate performs logical multiplication, more commonly known as

It performs a basic logic function called inversion or complementation.

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

A NOT gate following an AND gate is called NOT-AND or NAND gate.

A NOT gate following an OR gate is called NOT-OR or NOR gate. Its

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

IC trainer kit is mainly used to test and implement digital circuits.

Roll No. Submission Date Marks Remarks Staff Signature

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

Exp. No.: 2 Date:

COMPONENTS AND EQUIPMENTS REQUIRED:

Sl. No. Items Range Quantity

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

SR FLIP FLOP Using NOR Gates

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

Basic Flip flop:

Basic flip flop operates in asynchronous mode. It can be constructed from

Clocked SR Flip flop:

will be indeterminate. When the FF is switched ON its output state will be

The indeterminate output state of SRFF when S=R=1 is avoided by

Master Slave JK Flip Flop:

The race around condition of JKFF is rectified in master slave

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

It has only one input referred to as D input or data input. The

T stands for ‘toggle’. The output toggles when a clock pulse is

Flip Flop ICs:

7476 is dual negative edge triggered MSJKFF with preset and

1. Test all components and IC packages using multimeter and digital IC

Roll No. Submission Date Marks Remarks Staff Signature

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

Exp. No.: 3 Date:

To design and set up the following circuits.

1. A four-bit binary to Gray code converter.

2. A four-bit Gray to Binary code converter.

COMPONENTS AND EQUIPMENTS REQUIRED:

Sl.No. Items Range Quantity

1 Power supply (0-05) V 1

3 Resistor 330 Ohm 4

4 LED Different colors 4

6 Connecting Wires Required

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

FOUR BIT BINARY TO GRAY CODE CONVERTER

Dept. of EEE A.DARWIN JOSE RAJU, M.E., SMIEEE, SXCCE

Binary to Gray code

To convert a binary number to corresponding Gray code, the following rules

next Gray code digit. Disregard carries.

As the first step to design a binary to Gray code converter, set up a

truth table with binary numbers B3 B2 B1 B0 and corresponding Gray code

numbers G3 G2 G1 G0. Set up a circuit realizing the simplified logic expressions