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Digital Electronics
5.0 Sequential Logic
What you’ll learn in Module 5 Introduction
The logic circuits
Section 5.0 Introduction to Sequential
Logic Circuits. discussed in Digital
Electronics Module 4
Section 5.1 Clock Circuits.
had output states that
• RC Clock Generators.
depended on the
• Crystal Clock Generators.
particular combination
Section 5.2 SR Flip-flops. of logic states at the
• SR Flip-flops. input connections to the
• RS Latches. circuit. For this reason
• Clocked SR FlipFlops. these circuits are called
Section 5.3 D-Type Flip-flops. combinational logic
• D Type Flip-flop operation. circuits.
• Edge triggered flip-flops. Module 5 looks at
• Toggle flip-flops. digital circuits that use
• D Type master slave flip-flops. SEQUENTIAL LOGIC.
• Data timing in flip-flops.
In these circuits the output depends, not only on the
Section 5.4 JK Flip-flops. combination of logic states at its inputs, but also on the logic
• JK master slave flip-flop operation. states that existed previously. In other words the output
• Edge triggered JK flip-flops. depends on a SEQUENCE of events occurring at the circuit
• JK Type flip-flop ICs. inputs. Examples of such circuits include clocks, flip-flops,
• JK Type Flip-flop timing diagrams. bi-stables, counters, memories, and registers. The actions of
Section 5.5 CMOS Flip-flops. these circuits depend on a range of basic sub-circuits.
D Type & JK flip-flops using CMOS
technology.
Clock Circuits
Module 5.1 deals with clock oscillators,
Section 5.6 Counters
which are basically types of square wave
• Asynchronous (Ripple) Counters.
generators or oscillators that produce a
• Synchronous Counters.
continuous stream of square waves or a
• Counter ICs.
continuous train of pulses (a "square"
Section 5.7 Registers. wave whose mark to space ratio is NOT
• Parallel and serial loading. 1:1). These pulses are used to sequence
• Shift Registers. the actions of other devices in the
• Register ICs. sequential logic circuit so that all the actions taking place in
Section 5.8 Arithmetic & Logic Unit. the circuit are properly synchronised.
• Connecting digital components together.
Shift Registers
Also consisting of arrays of bi-stable elements,
the shift registers described in Module 5.7 are
temporary storage devices (memories) for multi-
bit digital data. The data can be stored in the
register either one bit at a time (serial input) or
as one or more bytes at a time (parallel input).
The register can then output the data in either serial or parallel form. Shift registers are vital to
receiving or transmitting data in digital communications systems. They can also be used in digital
arithmetic for operations such as multiplication and division.
A Simple ALU
A simple arithmetic and logic unit (ALU) is described in Module 5.8 and
combines many of the combinational and sequential logic circuits
described in modules 4 and 5 to demonstrate how a very complex
application is built by combining a number of much simpler digital sub
circuits.
1. Be constant in frequency.
Many clock oscillators use a crystal to control the frequency. Because crystal oscillators
generate normally high frequencies, where lower frequencies are required the original oscillator
frequency is divided down from a very high frequency to a lower one using counter circuits.
2. Have fast rising and falling edges to its pulses.
It is the edges of the pulses that are important in timing the operation of many sequential
circuits, the rise and fall times are usually be less than 100ns. The outputs of clock circuits will
typically have to drive more gates than any other output in a given system. To prevent this load
distorting the clock signal, it is usual for clock oscillator outputs to be fed via a buffer amplifier.
3. Have the correct logic levels.
The signals produced by the clock circuits must have appropriate the logic levels for the
circuits being supplied.
Some examples of clock oscillator circuits are given below.
Simple Clock Oscillator
Fig 5.1.1 is probably the simplest oscillator possible, having only
three components. Notice that the gate is a Schmitt inverter. This
device has an extremely fast change over between logic states. Also
the level at which it responds to an input change from 0 to 1 (Vt+)
is higher than the level at which it changes from 1 to 0 (Vt-). The
operation of the circuit is as follows.
Suppose the gate input is at logic 0, because the gate is an inverter,
Fig. 5.1.1 Basic Schmitt
the output must be at logic 1, and C will therefore charge up via R
Trigger Oscillator
from the output. This will happen with the normal CR charging
curve. Once Vt+ is reached at the gate input, the gate output will
rapidly switch to 0. The resistor is now connected effectively
between the positive plate of C and zero volts. Thus the capacitor
now discharges via R until the gate input voltage reduces to Vt-
when the output will change to logic 1 once more, starting the
charging and discharging cycle over again.
This Schmitt RC oscillator can produce a pulse waveform with an
excellent wave shape and very fast rise and fall times. The mark to
space ratio, as shown in Fig 5.1.2 is approximately 1:3.
Fig. 5.1.2 Typical Basic
Schmitt Oscillator Output
The frequency of oscillation depends on the time constant of R and C, but is also affected by the
characteristics of the logic family used. For the 74HC14 the frequency ( f )is calculated by:
1
f =
0.8RC
The active low PR and CLR inputs take no part in the operation
of this circuit so are also tied to logic 1. In toggle mode the Q output
of the JK flip-flop inverts the logic levels at Q and Q at every falling
edge of the clock (CK) input, also Q and Q always remain at
opposite logic states.
Fig. 5.1.6 illustrates the operation of Fig 5.1.5. Each of the NAND
gates will produce a logic 0 output whenever both its inputs are at
logic 1. The NAND gate producing 01 therefore creates a logic 0
pulse whenever CK and Q are at logic 1, and the NAND gate
Fig. 5.1.6 Producing Non-
producing 02 creates a logic 0 pulse whenever CK and Q are at Overlapping Clock Pulses
logic 1. Typical output waveforms are illustrated in Fig. 5.1.7.
If positive going clock pulses are required, the outputs from the
NAND gates may be inverted using Schmitt inverters, which
will also help to sharpen the rise and fall times of the clock
waveforms.
Distributing Clock Signals
For more demanding applications there are very many
specialised clock oscillator ICs available that are typically
optimised for a particular range of applications, such as
computer hardware, wireless communications, automotive or Fig. 5.1.7 Two Phase Clock
medical applications etc. Waveforms
Clock Fan-out
Whatever circuit is used to generate a clock signal, it is important that its output has sufficient fan-
out capability to drive the necessary number of ICs requiring a clock input, and that the clock signal
is not degraded in amplitude, speed of its rise and fall times or accuracy of its frequency. Also, by
maintaining fast rise and fall times, ringing on the waveform can become a problem. The waveform
should be kept as close as possible to a perfect square wave shape.
Circuit Capacitance
Because the clock must feed many gates, the small capacitance of each of these gates will add, to
become an appreciable capacitance, which loads the clock output tending to slow the rise and fall
time of the clock signal. To avoid this, the clock output must have a low enough impedance to
rapidly charge and discharge any natural capacitance in the circuit. The usual way to achieve this is
to feed the clock signal via a special clock buffer gate, which will have the necessary low output
impedance and a large fan out factor. Schmitt trigger gates may also be used to restore the shape
and integrity of clock signals before they are applied to gates in different parts of the circuit.
Cross-talk
Where the clock signal has to be distributed around large circuits, there is a greater chance of
introducing noise, and possible ‘cross-talk’ where data in one conductor is radiated into another
nearby conductor. Problems such as this will increase the likelihood of ‘skew’ errors, i.e. clock
signals arriving at different parts of the circuit at slightly different times, due to small changes in the
phase of some of the distributed clock signals. Miniaturisation brought about by surface mount
technology can help minimise these problems. Also when clock signals need to be sent from one
system to another over an external wired or wireless link it is common to use one of the several
ECL or LVDS logic families with their differential outputs to minimise interference, and there are
many application specific ICs (ASICS) using these technologies for high frequency clock
distribution.
5.2 SR Flip-flops
What you’ll learn in Module 5.2 Typical applications for SR Flip-flops.
The basic building bock that makes computer memories
After studying this section, you should
be able to:
possible, and is also used in many sequential logic circuits
is the flip-flop or bi-stable circuit. Just two inter-connected
Describe SR flip-flop circuits and can:
logic gates make up the basic form of this circuit whose
• Describe typical applications output has two stable output states. When the circuit is
for SR flip-flops.
triggered into either one of these states by a suitable input
• Recognize standard circuit pulse, it will ‘remember’ that state until it is changed by a
symbols for SR flip-flops.
further input pulse, or until power is removed. For this
• Recognize SR flip-flop reason the circuit may also be called a Bi-stable Latch.
integrated circuits.
The SR flip-flop can be considered as a 1-bit memory, since
Recognise alternative forms of SR flip-
flops. it stores the input pulse even after it has passed. Flip-flops
(or bi-stables) of different types can be made from logic
• Clocked SR flip-flop.
gates and, as with other combinations of logic gates, the
• High Activated SR flip-flops NAND and NOR gates are the most versatile, the NAND
(The RS Latch).
being most widely used. This is because, as well as being
• Compile truth tables for SR universal, i.e. it can be made to mimic any of the other
flip-flops.
standard logic functions, it is also cheaper to construct.
• Construct timing diagrams to
explain the operation of SR Other, more widely used types of flip-flop are the JK, the D
flip-flops. type and T type, which are developments of the SR flip-flop
Use circuit simulation software to and will be studied in Modules 5.3 and 5.4.
construct SR flip-flops.
The SR Flip-flop.
The SR (Set-Reset) flip-flop is one of the simplest sequential
circuits and consists of two gates connected as shown in Fig.
5.2.1. Notice that the output of each gate is connected to one
of the inputs of the other gate, giving a form of positive
feedback or ‘cross-coupling’.
The circuit has two active low inputs marked S and R , Fig 5.2.1 SR Flip-flop
(low activated)
‘NOT’ being indicated by the bar above the letter, as well as
two outputs, Q and Q . Table 5.2.1 shows what happens to the Q and Q outputs when a logic 0 is
applied to either the S or R inputs.
1. Q output is set to logic 1 by applying
logic 0 to the S input.
When SW1 is switched to the lower contact, there will be a short time (between times ‘b’ and ‘c’ in
Fig. 5.2.4) when neither S or R is connected to 0V. During this time S returns to logic 1,
therefore both inputs will be at logic 1 until time ‘c’, when SW1 connects R to 0V and Q is reset
to logic 0 completing the output pulse. The use of a ‘break before make’ rather than a ‘make before
break’ switch is important, as it ensures that during the changeover period (time ‘b’ to time ‘c’ in
Fig. 5.2.4) both inputs are at logic 1 rather than the non-allowed state where both inputs would be
logic 0. This ensures that outputs Q and Q are never at the same logic state.
Although, during the change over of SW1 both inputs are at logic 1, this does not produce the
indeterminate state described in Table 5.2.1, as one or other of the inputs is always at logic 0 before
both inputs become logic 1.
The RS Latch
Flip-flops can also be considered as latch circuits due to them
remembering or ‘latching’ a change at their inputs. A common form
of RS latch is shown in Fig. 5.2.5. In this circuit the S and R
inputs have now become S and R inputs, meaning that they will
now be ‘active high’.
Fig. 5.2.5 High Activated
They have also changed places, the R input is now on the gate RS Latch
having the Q output and the S input is on the Q gate.
These changes occur because the circuit is using NOR
gates instead of NAND.
The active high operation of the RS Latch is shown in
Table 5.2.2.
1. Q is set to 1 when the S input goes to logic 1.
2. This is remembered on Q after the S input returns to
logic 0.
3. Q is reset set to 0 when the R input goes to logic 1.
4. This is remembered on Q after the R input returns to logic 0.
5. If both inputs are at logic 1, Q is the same as Q (the non-allowed state).
6.The state of the outputs cannot be guaranteed if the inputs change from 1,1 to 0, 0 at the same
time.
Timing Diagrams
Truth tables are not always the best method for describing
the action of a sequential circuit such as the SR flip-flop.
Timing diagrams, which show how the logic states at various
points in a circuit vary with time, are often preferred.
Fig. 5.2.6 shows a timing diagram describing the action of
the basic RS Latch for logic changes at R and S. At time (a)
S goes high and sets Q, which remains high until time (b)
when S is low and R goes high, resetting Q. During period
(c) both S and R are high causing the non-allowed state
where both outputs are high. After period (c) Q remains high Fig. 5.2.6 Timing Diagram for a
until time (d) when R goes high, resetting Q. Period (e) is High Activated RS Latch
another non-allowed period, at the end of which both inputs
go low causing an indeterminate output condition in period (f).
DIGITAL ELECTRONICS MODULE 05.PDF 8 © E. COATES 2007-2014
www.learnabout-electronics.org Digital Electronics Module 5
D Type Flip-flops.
The major drawback of the SR flip-flop (i.e. its indeterminate output and non-allowed logic states)
described in Digital Electronics Module 5.2 is overcome by the D type flip-flop. This flip-flop,
shown in Fig. 5.3.1 together with its truth table and a typical schematic circuit symbol, may be
called a Data flip-flop because of its ability to ‘latch’ and remember data, or a Delay flip-flop
because latching and remembering data can be used to create a delay in the progress of that data
through a circuit. To avoid the ambiguity in the title therefore, it is usually known simply as the D
Type. The simplest form of a D Type flip-flop is basically a high activated SR type with an
additional inverter to ensure that the S and R inputs cannot both be high or both low at the same
time. This simple modification prevents both the indeterminate and non-allowed states of the SR
flip-flop. The S and R inputs are now replaced by a single D input, and all D type flip-flops have a
clock input.
Operation.
As long as the clock input is low, changes at the D input make no difference to the outputs. The
truth table in Fig. 5.3.1 shows this as a ‘don't care’ state (X). The basic D Type flip-flop shown in
Fig. 5.3.1 is called a level triggered D Type flip-flop because whether the D input is active or not
depends on the logic level of the clock input.
Provided that the CK input is high (at logic 1), then which ever logic state is at D will appear at
output Q and (unlike the SR flip-flops) Q is always the inverse of Q).
In Fig. 5.3.1, if D = 1, then S must be 1 and R must be 0, therefore Q is SET to 1.
Alternatively,
If D = 0 then R must be 1 and S must be 0, causing Q to be reset to 0.
Notice that there is now a subtle difference between the active low Set ( S ) and Reset ( R ) inputs,
and the D input. The D input is SYNCHRONOUS, that is its action is synchronised with the clock,
but the S and R inputs are ASYNCHRONOUS i.e. their action is
NOT synchronised with the clock. The SET and RESET inputs in Fig
5.3.4 are ‘low activated’, which is shown by the inversion circles at
the S and R inputs to indicate that they are really S and R .
The flip-flop is positive edge triggered, which is shown on the CK
input in Fig 5.3.4 by the wedge symbol. A wedge accompanied by an
inversion circle would indicate negative (falling) edge triggering, Fig. 5.3.4 Edge Triggered
though this is generally not used on D Type flip-flops. D Type Flip-Flop
Timing Diagram
The ‘Edge triggered D type flip-flop with asynchronous
preset and clear capability’, although developed from the
basic SR flip-flop becomes a very versatile flip-flop with
many uses. A timing diagram illustrating the action of a
positive edge triggered device is shown in Fig. 5.3.5.
At the positive going edges of clock pulses a and b, the D
input is high so Q is also high.
Just before pulse c the D input goes low, so at the positive
going edge of pulse c, Q goes low.
Between pulses c and d the asynchronous S input goes
low and immediately sets Q high.
Fig. 5.3.5 Positive Edge Triggered
The flip-flop then ignores pulse d while S is low, but as D Type Timing Diagram
S returns high, and D has also returned to its high state before pulse e, Q remains high during
pulse e.
D is still high at the positive going edge of pulse f, but because the flip-flop is positive edge
triggered, the change in the logic level of D during pulse f is ignored until the positive going edge
of pulse g, which resets Q to its low level.
At the positive going edge of pulse h, the low
level of input D remains, keeping Q low, but Edge Triggered D Type Flip-flop Summary:
• At the positive going edge of a CK pulse, Q will assume
between pulses h and i, the S input goes low, the same level as input D, unless either asynchronous
overriding any action of D and immediately input has control.
already high, no change in output Q occurs. • The action of the asynchronous inputs overrides any
effect of the D input.
Finally, just before pulse k, the asynchronous • Both asynchronous inputs should not be low at the same
reset input ( R ) goes low and resets Q to its time, as both Q and Q will then be at logic 1. This is a
non-allowed state.
low level (logic 0), which again causes the D
input to be ignored.
The actual input is now CK. The effect of this mode of operation is also shown in the timing
diagram in Fig. 5.3.8 using a positive edge triggered D type flip-flop.
Toggle Flip-flop Operation
Suppose that initially CK and Q = 0. Then Q and D must be 1. At the rising edge of a CK pulse,
the logic 1 at D is allowed into the flip-flop and, at the end of the flip-flop’s propagation delay,
appears at Q, and Q changes to logic 0 at the same time.
This logic 0 is now fed back to D, but it is important that it is not immediately accepted into the D
input, otherwise oscillation could occur with D continually changing between 1 and 0. However,
because of the flip-flop’s propagation delay, when the logic 0 from Q arrives at D, the very short
edge-triggering period will have completed, and the change in data at D will be ignored.
At the next CK rising edge of the clock signal, the 0 at D now passes to Q, making Q and D logic
1 again. The Q output of the flip-flop therefore toggles at each positive going edge of the CK pulse.
Because the Q output changes state at each clock pulse rising edge, the 0 period and the 1 period of
the Q output will always be of equal length, and the output will be a square wave with a 1:1 mark to
space ratio, its frequency will be half that of CK.
To use toggle flip-flops as simple binary counters, a number of toggle flip-flops may be connected
in cascade, with the Q output of the first flip-flop in the series, being connected to the CK input of
the next flip-flop and so on. This is also the principle of frequency division. How counters and
dividers can be constructed from toggle flip-flops is explained in Digital Electronics Module 5.6.
Data Timing
In practice however, using direct feedback from Q to D can cause problems as, to ensure stable
operation and avoid unwanted oscillation, it is important in any digital circuit, that any changes in
logic level taking place at D must be both stable, (free from any overshoot or ringing etc.) and at a
valid logic level during a short period, before and after the clock signal causes a change. These
periods are called the set up and hold times.
Although it is easy to think of the clock signal
initiating a change at a particular time, e.g.
when its rising edge occurs, data is actually
clocked into input D when the CK waveform
reaches a certain voltage level. In 74HC series
gates, this level is 50% of VDD, as illustrated in
Fig 5.3.9. This shows in expanded time detail,
the transitions taking place at the D and CK
inputs of a D type positive edge triggered flip- Fig. 5.3.9 Clocked Logic Set Up and Hold Times
flop.
To guarantee correct triggering, it is important that the data at the D input has settled at a valid logic
level before the clock signal triggers any change. Therefore there must be some time allowed from
when the D input first becomes valid to allow time for any slow rising pulse, any overshoot or
ringing to occur before the clock pulse samples the logic level.
For example, the time between point (a) in Fig.5.3.9, where D initially falls below 50% of VDD and
the time when CK rises to its trigger threshold of 50% VDD (point b) is called the set up time (tsetup
or tsu), and in 74HC series ICs this will typically be between 5ns and 15ns.
After the trigger point there must be a further period (b to c in Fig. 5.3.9) where the data at D must
remain at the same valid logic level to ensure that the correct logic level has been accepted. This is
called the hold time (thold or th) and is typically around 3ns in 74HC series ICs.
In sequential logic circuits precise timing is vitally important. The design of a circuit must take into
consideration not only set up and hold times but also the propagation times of gates or flip-flops in
each path that a digital signal takes through a circuit. Failure to get the timing right can lead to
problems such as ‘glitches’ i.e. sudden sharp spikes, as a device such as a flip-flop momentarily
produces a change from one logic level to another and back again. Such glitches may be very short
(a few nanoseconds) but sufficient to trigger another device to a wrong logic level.
With devices such as flip-flops using both triggering and feedback, incorrect timing can also lead to
instability and unwanted oscillations. Avoiding such problems is a major reason for the use of edge
triggering and master slave devices.
5.4 JK Flip-Flops
What you’ll learn in Module 5.4 A Universal Programmable Flip-flop
After studying this section, you should The JK Flip-flop is a programmable flip-flop because,
be able to: depending on the logic states applied to its inputs, J, K, S
Understand JK Flip-flop circuits and can: and R, it can be made to mimic the action of any of the
• Describe typical applications other flip-flop types.
for JK flip-flops.
• Recognize standard circuit
symbols for JK flip-flops.
• Recognise JK Flip-flop
integrated circuits.
• Describe alternative forms of
JK flip-flops.
Understand timing diagrams to explain
the operation of JK flip-flops.
Use circuit simulation software to
construct JK flip-flops. Fig.5.4.1 Basic JK Flip-flop Circuit
Fig. 5.4.1 shows the basic configuration for a JK flip-flop (without S and R inputs) using only four
NAND gates. The circuit is similar to the clocked SR flip-flop shown in Fig. 5.2.7, (Digital
Electronics Module 5.2) but in Fig. 5.4.1, it can be seen that although the clock input is the same as
in the clocked SR flip-flop, gate NAND 1 in Fig. 5.4.1 is now a three input gate and the set input
(S) has been replaced by an input labelled J, and the third input provides feedback from the Q
output.
On NAND 2 the reset input (R) of Fig 5.2.7 has been replaced by input K and there is an additional
feedback connection from Q. The purpose of this feedback is to eliminate the indeterminate state
that occurred on the SR flip-flop when both inputs were made logic 0 at the same time.
Operation
As a starting point, assume that both J and K are at logic 1 and the outputs Q = 0 and Q = 1, this
will cause NAND 1 to be enabled, as it has logic 1 on two (J and Q ) of its three inputs, requiring
only a logic 1 on its clock input to change its output state to logic 0. At the same time, NAND 2 is
disabled, because it only has one of its inputs (K) at logic 1, its feedback input is at logic 0 because
of the feedback from Q.
On the arrival of a clock pulse, the output of NAND 1 therefore becomes logic 0, and causes the
flip-flop to change state so that Q = 1 and Q = 0. This action enables NAND 2 and disables
NAND 1.
As this change of state at the outputs occurs however, there is a problem. If the clock pulse is still
high, or in its thold period when the flip-flop changes state, the output of NAND 2 may instantly go
to logic 0 and the flip-flop will reset back to its original state. This can then set up a situation where
the flip-flop will rapidly oscillate between its two states.
These problems caused by the output data ‘racing’ round the feedback lines from output to input
before the end of the clock pulse are known as RACE HAZARDS and of course must be avoided.
This can be done however, by using a more complex version of the circuit.
JK Master-Slave Operation
A theoretical schematic circuit diagram of a JK
master slave flip-flop is shown in Fig 5.4.3. Gates
G1 and G2 form a similar function to the input
gates in the basic JK flip-flop shown in Fig. 5.4.1,
with three inputs to allow for feedback
connections from Q and Q .
Fig 5.4.3 JK Master-Slave Flip-Flop
Schematic Diagram
Gates G3 and G4 form the master flip-flop and gates G7 and G8 form the slave flip-flop. Two
further gates, G5 and G6, are included between the master and slave flip-flops to transfer data from
the master to the slave. The way this transfer happens is that the output of the master flip-flop is
delayed for the duration of the clock pulse, by storing it, temporarily in the master flip-flop, whilst
the CK pulse is high. The operation (in toggle mode) is as follows:
Loading the Master Flip-flop
With J and K both at logic 1 (the toggle mode setting), suppose that Q = 0 and Q = 1, gate G2 will
be disabled as, although there are two logic 1 states on its J and CK inputs, the feedback (bottom)
input of G2 will be at logic 0 due to the feedback from Q.
G1 however has a logic 1 fed back from Q , which ensures that gate G1 is enabled, as all three of
its inputs are now logic 1. G1 output will therefore be at logic 0 (NAND gate rules), which will
cause the master flip-flop (G3 and G4) to set its q1 output to logic 1, and its q1 output to logic 0.
During the time the CK input remains at logic 1, q1 and q1 will remain at q1 = 1 and q1 = 0, but
the transfer gates G5 and G6 are inhibited because for example, if Q is currently at logic 0 and Q
is at logic 1, gate G1 will have all three of its inputs at logic 1, and so its output will be 0. Because
G1 output is also the active low SET input of G3, as the CK pulse went to logic 1, G3 output went
to logic 0, setting the master flip-flop output q1 to logic 1.
Controlling the Transfer Gates
The logic 0 on G1 output will cause transfer gate G5 to be disabled, and combined with the logic 1
at q1 this will cause Q5 output to remain at logic 1 for the duration of the CK pulse. The input to G6
from G2 output however will be at logic 1, but as q1 will now be at logic 0, transfer gate G6 will
also be disabled, making its output logic 0. The data at the outputs q1 and q1 cannot now be
passed to the slave flip-flop for the duration of the clock pulse.
The Clock Pulse Falling Edge
Once the clock input goes low however, logic 0 is applied to the clock inputs of gates G1 and G2.
The output of G1 now returns to logic 1, making both inputs to gate G5 logic 1, and causing its
output to fall to logic 0. As q1 is still at logic 0, gate G6 is still disabled, and so the output of G6 is
at logic 1.
The Slave Flip-flop
With the output of Gate G5 at logic 0 and G6 output at logic 1, gates G7 and G8, which form a low
activated SR flip-flop is set, and so Q becomes logic 1 and Q becomes logic 0.
The output conditions are now inverted, and this change is fed back to the input gates G1 and G2.
However these are now both disabled because the clock input is already low, so the master flip-flop
is not affected.
The arrival of the rising edge of the next clock pulse then allows the new logic levels at Q and Q
into the feedback inputs to gates G1 and G2 to be fed into the master flip-flop as before, but this
time Q is at logic 1, so it is gate G2 that will be enabled at the rising edge of the clock pulse.
Now, as the clock pulse goes to logic 1 the master flip-flop will be reset, q1 will go to logic 0 and at
the falling edge of the clock pulse the transfer gates will pass the data to the slave flip-flop setting Q
back to logic 0, so the Q and Q outputs toggle once more.
CMOS Flip-flop
Fig 5.5.2 shows a basic circuit for a single flip-flop,
which operates as a level triggered D Type flip-flop.
Apart from the NOT gate (N1) and the buffer (B1)
controlling the CK input, the basic flip-flop uses only
two NOT gates (N2 and N3) and two transmission
gates (TG1 and TG2).
Fig. 5.5.2 Basic CMOS Flip-flop Circuit
CMOS Flip-flop Operation
The inverter N1 and the Buffer B1 create clock pulses CK and inverted clock pulses CK , which
(because N1 and B1 have identical propagation delays), will exactly coincide in time when applied
to the transmission gates of the flip-flop circuit.
Initially, assuming that the CK and D are both at logic 0, CK will be at logic 1, so transmission
gate TG1 will be in its high impedance state, preventing D from having any effect upon the flip-
flop.
When CK is logic 1 and CK is logic 0, TG1 will conduct and the logic 0 from D will be inverted
by N2, so the output Q will become logic 1. The logic 1 at Q will be inverted by N3 to become
logic 0 at the Q output.
The logic 1 at Q will not affect the logic 0 at the input to N2 as TG2, connected in opposite polarity
to the CK and CK clock signals will be turned off. This condition will remain stable irrespective
of any further clock pulses being applied, as whenever TG1 is turned on, TG2 is turned off.
If input D is now changed to logic 1 between the occurrence of clock pulses, the rising edge of the
first clock pulse after the change at D will turn on TG1, transmitting the logic 1 from D to the input
of N2, causing Q to change to logic 1 and (via N3) Q to change to logic 0.
Whilst the CK input is high, any changes at D will be transmitted via TG1 and N2 to the outputs,
indicating that the flip-flop is level triggered, but the moment the falling edge of the clock pulse
occurs, TG1 will turn off and TG2 will turn on, isolating N1 and N2 from any further changes at the
D input and leaving the output of N3 connected via TG2 to the input of N1.
As both these points will be at the same logic state (the logic state existing at D before the falling
edge of the CK pulse) the flip-flop outputs will remain in a stable mode until the next clock pulse,
when Q will take up the same state as input D once more.
Practical CMOS Flip-flop Circuits
Fig. 5.5.3 illustrates a CMOS D Type Positive
Edge Triggered Master Slave Flip-flop. Notice
that each pair of transmission gates TG1/ TG2 in
the master flip flop, and TG3/TG4 in the slave
flip-flop are connected to the clock lines in the
opposite sense to each other, so that as soon as
the master flip-flop accepts data from D at the
rising edge of the CK pulse, the slave flip-flop is
inhibited, preventing any further change at the
outputs, effectively giving positive edge, rather
than level triggering. Fig. 5.5.3 CMOS D Type Positive Edge
Triggered Master Slave Flip-flop
The RESET input ( R ) works in the same way, by forcing the NAND gates G1 and G4 to have
logic 1 outputs.
5.6 Counters
What you’ll learn in Module 5.6
After studying this section, you should
be able to:
Understand the operation of digital
counter circuits and can:
Describe the action of asynchronous Fig. 5.6.1 Four-bit Asynchronous Up Counter
(ripple) counters using D Type flip flops.
• Up counters.
• Down counters.
• Frequency division
Understand the operation of Synchronous
counters.
Describe common control features used
in synchronous counters.
• BCD counters.
• Up/down control.
• Enable/disable.
• Preset and Clear.
As Q 0 (and the CK input of FF1 goes high) this will now make Q1 high, indicating a value of 21
(210) on the Q outputs.
The next (third) CK pulse will cause Q0 to go to logic 1 again, so both Q0 and Q1 will now be high,
making the 4-bit output 11002 (310 remembering that Q0 is the least significant bit).
The fourth CK pulse will make both Q0 and Q1 return to 0 and as Q 1 will go high at this time, this
will toggle FF2, making Q2 high and indicating 00102 (410) at the outputs.
Reading the output word from right to left, the Q outputs therefore continue to represent a binary
number equalling the number of input pulses received at the CK input of FF0. As this is a four-stage
counter the flip-flops will continue to toggle in sequence and the four Q outputs will output a
sequence of binary values from 00002 to 11112 (0 to 1510) before the output returns to 00002 and
begins to count up again as illustrated by the
waveforms in Fig 5.6.2.
Four Bit Asynchronous Down Counter
To convert the up counter in Fig. 5.6.1 to count
DOWN instead, is simply a matter of modifying
the connections between the flip-flops. By taking
both the output lines and the CK pulse for the
next flip-flop in sequence from the Q output as
shown in Fig. 5.6.3, a positive edge triggered Fig 5.6.3 Four-bit Asynchronous
counter will count down from 11112 to 00002. Down Counter
Although both up and down counters can be built, using the asynchronous method for propagating
the clock, they are not widely used as counters as they become unreliable at high clock speeds, or
when a large number of flip-flops are connected together to give larger counts, due to the clock
ripple effect.
Clock Ripple
The effect of clock ripple in asynchronous counters is illustrated in
Fig. 5.6.4, which is a magnified section (pulse 8) of Fig. 5.6.2.
Fig. 5.6.4 shows how the propagation delays created by the gates in
each flip-flop (indicated by the blue vertical lines) add, over a
number of flip-flops, to form a significant amount of delay between
the time at which the output changes at the first flip flop (the least
significant bit), and the last flip flop (the most significant bit).
As the Q0 to Q3 outputs each change at different times, a number of
different output states occur as any particular clock pulse causes a
new value to appear at the outputs.
At CK pulse 8 for example, the outputs Q0 to Q3 should change from
11102 (710) to 00012 (810), however what really happens (reading the
vertical columns of 1s and 0s in Fig. 5.6.4) is that the outputs change,
over a period of around 400 to 700ns, in the following sequence:
11102 = 710
01102 = 610
Fig.5.6.4 Timing Diagram
00102 = 410
Detail Showing Clock Ripple
00002 = 010
00012 = 810
At CK pulses other that pulse 8 of course, different sequences will occur, therefore there will be
periods, as a change of value ripples through the chain of flip-flops, when unexpected values appear
at the Q outputs for a very short time. However this can cause problems when a particular binary
value is to be selected, as in the case of a decade counter, which must count from 00002 to 10012
(910) and then reset to 00002 on a count of 10102 (1010).
These short-lived logic values will also cause a series of very short spikes on the Q outputs, as the
propagation delay of a single flip-flop is only about 100 to 150ns. These spikes are called ‘runt
spikes’ and although they may not all reach to full logic 1 value every time, as well as possibly
causing false counter triggering, they must also be considered as a possible cause of interference to
other parts of the circuit.
Although this problem prevents the circuit being used as a reliable counter, it is still valuable as a
simple and effective frequency divider, where a high frequency oscillator provides the input and
each flip-flop in the chain divides the frequency by two.
Synchronous Counters
The synchronous counter provides a more reliable circuit for counting purposes, and for high-speed
operation, as the clock pulses in this circuit are fed to every flip-flop in the chain at exactly the
same time. Synchronous counters use JK flip-flops, as the programmable J and K inputs allow the
toggling of individual flip-flops to be enabled or disabled at various stages of the count.
Synchronous counters therefore eliminate the clock ripple problem, as the operation of the circuit is
synchronised to the CK pulses, rather than flip-flop outputs.
Synchronous Up Counter
(Note: In the diagrams under this heading only the
connections essential to toggle operation and the clock are
shown.)
Fig. 5.6.5 shows how the clock pulses are applied
in a synchronous counter. Notice that the CK input Fig.5.6.5 Synchronous Clock Connection
is applied to all the flip-flops in parallel. Therefore,
as all the flip-flops receive a clock pulse at the same instant,
some method must be used to prevent all the flip-flops
changing state at the same time. This of course would result
in the counter outputs simply toggling from all ones to all
zeros, and back again with each clock pulse.
However, with JK flip-flops, when both J and K inputs are
logic 1 the output toggles on each CK pulse, but when J and Fig. 5.6.6 The First Two Stages
K are both at logic 0 no change takes place. of a Synchronous Counter
Fig. 5.6.6 shows two stages of a synchronous
counter. The binary output is taken from the Q
outputs of the flip-flops. Note that on FF0 the J and
K inputs are permanently wired to logic 1, so Q0 will
change state (toggle) on each clock pulse. This
provides the ‘ones’ count for the least significant bit.
On FF1 the J1 and K1 inputs are both connected to Q0 so that
FF1 output Table 5.6.1will only be in toggle mode when Q0 is
also at logic 1. As this only happens on alternate clock pulses,
Q1 will only toggle on even numbered clock pulses giving a
‘twos’ count on the Q1 output.
Table 5.6.1 shows this action, where it can be seen that Q1
toggles on the clock pulse only when J1 and K1 are high, Fig. 5.6.7 Adding a Third Stage
giving a two bit binary count on the Q outputs, (where Q0 is
the least significant bit).
In adding a third flip flop to the counter however, direct connection from J and K to the previous Q1
output would not give the correct count. Because Q1 is high at a count of 210 this would mean that
FF2 would toggle on clock pulse three, as J2 and K2 would be high. Therefore clock pulse 3 would
give a binary count of 1112 or 710 instead of 410.
To prevent this problem an AND gate is used, as
shown in Fig. 5.6.7 to ensure that J2 and K2 are high
only when both Q0 and Q1 are at logic 1 (i.e. at a count
of three). Only when the outputs are in this state will
the next clock pulse toggle Q2 to logic 1. The outputs
Q0 and Q1 will of course return to logic 0 on this
pulse, so giving a count of 0012 or 410 (with Q0 being
the least significant bit). Fig. 5.6.8 Four Bit Synchronous
Fig. 5.6.8 shows the additional gating for a four stage Up Counter
synchronous counter. Here FF3 is put into toggle
mode by making J3 and K3 logic 1, only when Q0 Q1 and
Q2 are all at logic 1.
Q3 therefore will not toggle to its high state until the eighth
clock pulse, and will remain high until the sixteenth clock
pulse. After this pulse, all the Q outputs will return to zero.
Note that for this basic form of the synchronous counter to
work, the PR and CLR inputs must also be all at logic 1,
(their inactive state) as shown in Fig. 5.6.8.
Synchronous Down Counter
Converting the synchronous up counter to count down is
simply a matter of reversing the count. If all of the ones and
zeros in the 0 to 1510 sequence shown in Table 5.6.2 are
complemented, (shown with a pink background) the
sequence becomes 1510 to 0.
Down Counter Circuit
As every Q output on the JK flip-flops has its
complement on Q , all that is needed to convert the
up counter in Fig. 5.6.8 to the down counter shown in
Fig 5.6.9 is to take the JK inputs for FF1 from the Q
output of FF0 instead of the Q output. Gate TC2 now Fig. 5.6.9 Four Bit
takes its inputs from the Q outputs of FF0 and FF1, Synchronous Down Counter
DeMorgan equivalent NAND gate circuit. This is necessary to provide the correct logic state for the
next data selector.
The Q and Q outputs of flip-flops FF0, FF1 and FF2 are connected to what are, in effect, the A
and B data inputs of the data selectors. If the control input is at logic 1 then the CK pulse to the next
flip-flop is fed from the Q output, making the counter an UP counter, but if the control input is 0
then CK pulses are fed from Q and the counter is a DOWN counter.
Synchronous BCD Up Counter
A typical use of the CLR inputs is illustrated in the
BCD Up Counter in Fig 5.6.11. The counter outputs
Q1 and Q3 are connected to the inputs of a NAND
gate, the output of which is taken to the CLR
inputs of all four flip-flops. When Q1 and Q3 are
both at logic 1, the output terminal of the limit
detection NAND gate (LD1) will become logic 0
and reset all the flip-flop outputs to logic 0.
Because the first time Q1 and Q3 are both at logic 1
during a 0 to 1510 count is at a count of ten (10102), Fig. 5.6.11 Synchronous BCD
this will cause the counter to count from 0 to 910 Up Counter
and then reset to 0, omitting 1010 to 1510.
The circuit is therefore a BCD8421 counter, an extremely useful device for driving numeric displays
via a BCD to 7-segment decoder etc. However by re-designing the gating system to produce logic 0
at the CLR inputs for a different maximum value, any count other than 0 to 15 can be achieved.
If you already have a simulator such as Logisim installed on your computer, why not try designing
an Octal up counter for example.
Enable Inputs
ENABLE ( EN ) inputs on counter ICs may have a
number of different names, e.g. Chip Enable ( CE ),
Count Enable ( CTEN ), Output Enable ( OE ) etc.,
each denoting the same or similar functions.
Count Enable ( CTEN ) for example, is a feature on
counter integrated circuits, and in the synchronous
counter illustrated in Fig 5.6.13, is an active low
input. When it is set to logic 1, it will prevent the
count from progressing, even in the presence of clock
pulses, but the count will continue normally when Fig. 5.6.13 Synchronous Up Counter
with Count Enable and Clear Inputs
CTEN is at logic 0.
A common way of disabling the counter, whilst retaining any current data on the Q outputs, is to
inhibit the toggle action of the JK flip-flops whilst CTEN is inactive (logic 1), by making the JK
inputs of all the flip-flops logic 0. However, as the logic states of the JK inputs of FF1, FF2 and FF3
depend on the state of the previous Q output, either directly or via gates T2 and T3, in order to
preserve the output data, the Q outputs must be isolated from the JK inputs whenever CTEN is
logic 1, but the Q outputs must connect to the JK inputs when CTEN is at logic 0 (the count
enabled state).
This is achieved by using the extra (AND) enable gates, E1, E2 and E3, each of which have one of
their inputs connected to CTEN (the inverse of CTEN ). When the count is disabled, CTEN and
therefore one of the inputs on each of E1, E2 and E3 will be at logic 0, which will cause these
enable gate outputs, and the flip-flop JK inputs to also be at logic 0, whatever logic states are
present on the Q outputs, and also at the other enable gate inputs. Therefore whenever CTEN is at
logic 1 the count is disabled.
When CTEN is at logic 0 however, CTEN will be logic 1 and E1, E2 and E3 will be enabled,
causing whatever logic state is present on the Q outputs to be passed to the JK inputs. In this
condition, when the next clock pulse is received at the CK input the flip-flops will toggle, following
their normal sequence.
Preset and Clear
Fig. 5.6.13 also makes use of the CLR input to allow the counter outputs to be reset to zero at any
time. Asynchronous PRESET ( PR ) and CLEAR ( CLR ) are inputs available on most JK and D
type flip-flops and are very useful in the design of counters. The CLR inputs of several flip-flops
can be used together to reset the count to zero by making the CLR inputs of the flip-flops logic 0 at
any time, independently of the logic state of the clock input. This was done in the BCD up counter
in Fig. 5.6.10.
Alternatively the PR inputs of the flip-flops could be used in a BCD down counter to set all of the
Q outputs to logic 1 when a count of 0000 is sensed.
However, using the asynchronous inputs in a synchronous circuit design must be done with care, as
it is possible, depending on the exact time during the clock cycle at which either asynchronous input
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causes a change, that unwanted spikes, and/or timing errors could be generated. A preferable, and
more flexible method of setting or resetting each of the Q outputs separately uses a parallel loading
method, where the individual flip-flops within the counter can be set or reset, depending on the
logic states at data inputs (one per flip-flop). ICs are available that support either synchronous or
asynchronous loading to suit various design requirements.
Asynchronous Parallel Load
While common PR and CLR inputs can
produce outputs of 0000 or 1111, a PARALLEL
LOAD ( PL ) input will allow any value to be
loaded into the counter. Using a separate DATA
input for each flip-flop, and a small amount of
extra logic, a logic 0 on the PL will load the
counter with any pre-determined binary value
before the start of, or during the count. A method
of achieving asynchronous parallel loading on a
synchronous counter is shown in Fig. 5.6.14.
Fig. 5.6.14 Asynchronous Parallel Load
Load Operation
The binary value to be loaded into the counter is applied to inputs D0 to D3 and a logic 0 pulse is
applied to the PL input. This logic 0 is inverted and applied to one input of each of the eight
NAND gates to enable them. If the value to be loaded into a particular flip-flop is logic 1, this
makes the inputs of the right hand NAND gate 1,1 and due to the inverter between the pair of
NAND gates for that particular input, the left hand NAND gate inputs will be 1,0.
The result of this is that logic 0 is applied to the flip-flop PR input and logic 1 is applied to the
CLR input. This combination sets the Q output to logic 1, the same value that was applied to the D
input. Similarly if a D input is at logic 0 the output of the left hand NAND gate of the pair will be
Logic 0 and the right hand gate output will be logic 1, which will clear the Q output of the flip-flop.
Because the PL input is common to each pair of load NAND gates, all four flip-flops are loaded
simultaneously with the value, either 1 or 0 present at its particular D input.
Multiple Inputs and Outputs
Modifications such as those described
in this module make the basic
synchronous counter much more
versatile. Both TTL and CMOS
synchronous counters are available in
the 74 series of ICs containing usually
4-bit counters with these and other
modifications for a wide variety of
applications. Fig 5.6.15 shows how all
the input functions described above,
plus some important outputs such as
Ripple Carry ( RC ) and Terminal
Count (TC) can be combined to form a
single synchronous counter IC.
Fig. 5.6.15 Synchronous Up/Down Counter with
Multiple Inputs and Outputs
upsetting the count if adequate decoupling is not provided. This problem is reduced in ripple
counters due to the lower frequencies in most of the stages.
Also, because the clock pulses applied to synchronous counters must charge, and discharge the
input capacitance of every flip-flop simultaneously; synchronous counters having many flip-flops
will cause large pulses of charge and discharge current in the clock driver circuits every time the
clock changes logic state. This can also cause unwelcome spikes on the supply lines that could
cause problems elsewhere in the digital circuitry. This is less of a problem with asynchronous
counters, as the clock is only driving the first flip-flop in the counter chain.
Asynchronous counters are mostly used for frequency division applications and for generating time
delays. In either of these applications the timing of individual outputs is not likely to cause a
problem to external circuitry, and the fact that most of the stages in the counter run at much lower
frequencies than the input clock, greatly reduces any problem of high frequency noise interference
to surrounding components.
Counter ICs
Asynchronous (Ripple) Counters:
74HC390 - Dual decade ripple counter.
74HC393 - Dual 4-stage binary ripple counter.
74HC4040 - 12-Stage binary ripple counter.
74HC93 - 4-Bit binary ripple counter.
CD4060 - 14-Stage binary counter plus oscillator.
HEF4042B - 7-Stage binary ripple counter.
Synchronous Counters:
74HC160 - Pre-settable synchronous BCD counter with asynchronous reset.
74HC161 - 4-Bit synchronous BCD counter with asynchronous reset and synchronous load.
74HC163 - 4-Bit synchronous binary counter with asynchronous reset and synchronous load.
74HC191 - 4-bit synchronous binary up/down counter with asynchronous reset and load.
74HC192 - 4-Bit synchronous BCD counter with asynchronous reset and load.
74HC193 - 4-Bit synchronous binary counter with asynchronous reset and load.
CD4017/4022B - 4-Stage synchronous counters with Decade (1 of 10) or Octal (1 of 8) outputs.
5.7 Registers
What you’ll learn in Module 5.7
After studying this section, you should
be able to:
Understand the operation of digital
parallel in/parallel out (PIPO) registers.
Describe the action of serial and parallel
shift registers.
• Serial in/Serial out (SISO).
• Serial in/Parallel out (SIPO).
• Parallel in/Serial out PISO.
Understand the operation of
bi-directional shift registers.
Recognise common features used in shift
registers.
Recognise register ICs
Registers
An electronic register is a form of memory that
uses a series of flip-flops to store the individual
bits of a binary word, such as a byte (8 bits) of
data. The length of the stored binary word
depends on the number of flip-flops that make
up the register. A simple 4-bit register is
illustrated in Fig. 5.7.1 and consists of four D
Type flip-flops, sharing a common clock input,
providing synchronous operation ensuring all
bits are stored at exactly the same time.
The binary word to be stored is applied to the Fig. 5.7.1 Parallel In/Parallel Out
four D inputs and is remembered by the flip- (PIPO) Register
flops at the rising edge of the next clock (CK)
pulse. The stored data can then be read from the Q outputs at any time, as long as power is
maintained, or until a change of data on the D inputs is stored by a further clock pulse, which
overwrites the previous data.
Different types of register are generally classified by the method of storage and readout used; this
basic form of register is therefore classified as a ‘Parallel In/Parallel Out’ (PIPO) register.
Shift Registers.
Shift registers have a similar structure to the PIPO register but have the added ability to shift the
stored binary word left or right, one bit at a time. This makes them extremely useful for many
applications. They are used in handling serial data and converting it to parallel form or back again
to serial form, and therefore are an essential component in communication systems. Shift registers
are also essential in arithmetic circuits where binary numbers may be shifted right (and so divided
by two), or left (multiplied by two) as part of a calculation. Shift registers can be used to delay the
passage of data at a particular point in a circuit. As the data is shifted one bit at a time from input to
output, the amount of delay will depend on the number of flip-flops in the register and the
frequency of the clock pulses driving the shift register. Because a number of serial bits of data are
stored as they enter the input, and are then recovered from the output at some later time, this action
can also be described as a serial memory, or as a digital delay line.
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SIPO
In Fig. 5.7.4 the shift register is modified
to include additional Q outputs from each
flip-flop, so allowing the register to output
data in parallel form. The register could
therefore now be called a ‘Serial In/Parallel
Out’ or SIPO register. This format is the
basis for converting serial data to parallel Fig. 5.7.4 Serial In/Parallel Out (SIPO)
data. Shift Register
PISO
If use is also made of the Q output,
and the additional preset and clear
inputs available on many flip-flops,
the shift register could be made
more versatile still.
Fig. 5.7.5 shows a shift register
modified to enable it to be loaded
with a 4-bit parallel number, which
may then be shifted right to appear
at the serial output one bit at a time.
As the ‘Parallel In/Serial Out’ or
PISO register also has a serial
input, it can also be used as a SISO
register, and if extra outputs from Fig. 5.7.5 Multiple Mode (SISO, SIPO, PISO, PIPO)
each Q output were also included, Shift Register
the register would also have Serial
In/Parallel Out (SIPO) operation.
Loading Parallel Data
If the LOAD input is taken to logic 0, the LOAD control line connected to the four pairs of
NAND gates associated with the four flip-flops will be at logic 1, and all four pairs of NAND gates
will be enabled. Therefore a logic 1 appearing on any of the D inputs will be inverted by the NOT
gate connected to the D input, making the inputs to the left hand NAND gate of the relevant pair of
gates, logic 1 and logic 0. This will cause logic 1 to be applied to the CLR input of the flip-flop.
The right hand NAND gate of the pair will have both inputs at logic 1, due to the logic 1 on LOAD
line and logic 1 on the D input, and so will output logic 0 (NAND gate rules) to the PR input of the
flip-flop, setting the Q output to logic 1.
If the D input is at logic 0, the left hand gate of the NAND gate pair will output logic 0 and the right
hand NAND gate will output logic 1, causing the CLR input to clear the Q output of the relevant
flip-flop to logic 0.
Notice that as JK flip-flops are being used in this design, a NOT gate is connected between J and K
of the first flip-flop of the chain to make the JK flip-flop mimic a D Type. The remaining flip-flops
of the shift register have J and K connected to the previous Q and Q outputs, so will also be at
opposite logic states.
A 4-bit reversible shift register.
The shift register in Fig 5.7.5 could be operated as:
• A parallel in/parallel out register. (PIPO)
• A Serial in/serial out register. (SISO)
• A serial in/parallel out register. (SIPO)
• A parallel in/serial out register. (PISO)
However Fig 5.7.5 can only shift data in one direction, i.e. left to right. To be truly versatile it could
be an advantage to be able to shift data in both directions and in any of the four shift register
operating modes. Fig. 5.7.6 achieves this by adding data steering circuitry.
The gating arrangement at the bottom of Fig 5.7.6 (gates G1 to G13) is exactly the same as that
described above in Fig. 5.7.5, and these gates control the loading of parallel data.
Gates G14 to G28 in Fig 5.7.6 control the direction of data flow through the register. The JK flip-
flops use the inverter gates G29 to G32 to ensure that J and K are at opposite logic states, so the
flip-flops are mimicking D Type operation, with J being used as the data input. Notice also that the
clock is connected in the familiar synchronous mode.
Operation.
In any of the modes involving serial operation, data may be shifted left or shifted right by the
application of a suitable logic level at the shift control (R/ L ) input.
With a logic 1 at this input the register is in the shift right mode, and data is taken into the ‘Serial in
R’ input to be shifted right by application of successive clock pulses, appearing as parallel data,
changing with each clock pulse, on the flip flop Q outputs. After four clock pulses the data begins
to appear in serial form on the Q3 output, which is also the ‘Serial Out R’ output.
The logic 1 on the shift control (R/ L ) enables gates G18, 20, 22 & 24, but because the logic 1 is
inverted by G27, gates G19, 21, 23 & 25 are disabled.
The path of serial data (e.g. a logic 1) from left to right is as follows; the logic 1 appearing at the
input to G26 is inverted and passes through G18 which re-inverts it to logic 1 and, as g19 is
disabled its output must also be at logic 1. Both inputs to the AND gate G14 are at logic 1 and
therefore so is its output, making the J input of FF0 logic 1.
On the arrival of a clock pulse, the logic 1 input to FF0 will appear on the output Q0. Its inverse
(logic 0) will also appear on the Q output of FF0. This logic 0 forms the input to the next
multiplexer arrangement, gates G20, 21 & 15. As G20 is enabled (and G21 disabled) the logic 0
becomes logic 1 at G15 output and so is fed to the J input of FF1. This method is used to transfer
data to each flip-flop in the chain.
To achieve shift left operation, the shift control (R/ L ) is set to logic 0 and so enables gates G19,
21, 23 & 25 while disabling gates G18, 20, 22 & 24. Therefore the Q output of FF3 is connected
via G23 and G16 to the D input of FF2, the Q output of FF2 is connected to the J input of FF1 via
G21 and G15 (remember that G24 is disabled, so FF3 is isolated from this path). Finally, the Q
output of FF1 is connected via G19 and G14 to the J input of FF0, the Q0 output of which is also the
‘Serial Out L’ output. The ability to shift data in either direction, together with the parallel input and
output facilities make this register a very versatile device.
It is common to connect shift register ICs in cascade, using the serial output of one register to
connect to the serial input of the next register in the chain. For this reason both the data and clock
inputs and outputs of register ICs are normally buffered.
Some examples from the many commercially available IC registers using these and similar
methods, available in both CMOS and TTL versions, are listed below.
Putting the correct pattern of 1s and 0s (the control word) on the control lines will cause the ALU to
perform the required arithmetic or logical operation on the data being input at A and B. With a
control word of 8-bits, this could potentially allow up to 256 different combinations, or control
words, which would be more than ample, even for very complex microprocessors or micro
controllers. However this basic ALU needs only eight control words to control the different
operations available.
To see the ALU operate as described below, you can download our free, fully interactive Logisim
ALU circuit (assuming you have the free Logisim Digital Simulator installed on your desktop or
laptop computer), see our extra Logisim page for details.
Note: In this section the tilde character ~ is used where necessary to indicate NOT (e.g. ~LE = LE
) to match the usage in the Logisim simulations.
Multiplexers
MUX 1 and MUX 3 are
identical 8 bit multiplexers that
select either the input data
word A (MUX 1) or data word
B (MUX 3) or their internally
generated complement, as
shown in Fig. 5.8.3.
MUX 2 is a similar design but
selects either the data word B
or the zero value 00HEX , as Fig. 5.8.3 MUX 1 and MUX 3 Fig. 5.8.4 MUX 2
shown in Fig. 5.8.4.
8-Bit Adder Fig. 5.8.4 MUX 2
The adder component is an 8-bit ripple carry
adder; real ALUs would normally feature a
‘carry-look-ahead’ adder, allowing for high-
speed operation. However for this example the
much simpler ripple carry adder is adequate, as
the operation is totally manual.
The adder component is illustrated in Fig. 5.8.5
and consists of eight full-adder circuits with
additional logic consisting of an XOR gate to
detect overflow errors, and an 8-input NOR gate
to detect a zero result.
Negative results are indicated by sampling the
most significant bit of the ‘sum’ output, and a
‘carry’ is indicated by sampling the carry output
of the most significant full adder.
Four D type flip-flops are used as ‘flag’ outputs
to indicate the current state of the ALU after
each operation.
An additional JK flip-flop (mimicking a D type flip-flop) is placed between the ‘serial-right’ output
of the shift register and COUT to allow the ‘clear carry’ input (~CLC) to clear the carry flag.
Carry Logic and Rotate Select
The carry logic circuit shown in Fig. 5.8.7 prevents the carry flag
being set in rotate right mode, as bits rotate from bit 0 and re-enter
the shift register at bit 7, therefore allowing correct carry flag
operation in both left and right rotate modes.
When the ROTATE input is at logic 1, the Rotate Select circuit in
Fig 5.8.7 allows COUT from the shift register to be fed back to the
shift register CIN input for continuous bit rotation.
Fig.5.8.7 ALU Carry Logic
ALU Operation
Addition
To perform an addition, input data B is added to A. This is achieved by putting logic 1 on the
control inputs of multiplexers 1, 2 and 3. This causes data A and B to be applied to the adder inputs.
Also, to allow any carry bit from the CIN input to be included in the addition, the 1 bit carry
multiplexer must have logic 0 on its control input. The shift register is only used as a PIPO register
in addition mode, so its input lines R/~L and ROTATE must be at logic 0. SHIFT/~LE must also be
at logic 0 to enable parallel loading of the shift register, which will hold the result of the addition (A
plus B) after the application of a single CK pulse.
The Status Flags
The Flag flip-flops are special outputs from the adder circuit. They consist of four separate D type
flip-flops, each of which can be set to 1 or cleared to 0. They are set or cleared by the result in the
adder. They signal, or ‘flag’ to the user, that a particular event has occurred.
The Carry flag (C)
The carry flag will be set if the result of any arithmetic or logic event causes a logic 1 to be
carried over from bit 7 into the ‘carry bit’, (which is the carry flag). The carry flag can be
cleared at any time by making the ‘clear carry’ input (~CLC) logic 0.
The Overflow flag (V)
When carrying out twos complement arithmetic, errors can occur if large numbers are
involved. For example if two positive numbers less than 12710 are added and produce a
negative result (any value greater than 12710). This would cause the sign of the result
(indicated by bit 7) to be wrong. The overflow flag gives an indication that an error has
occurred by being set to 1 to indicate an ‘overflow error’. An error is sensed and the
overflow flag is set when either of two conditions occurs.
• There is a carry of logic 1 from bit 6 to bit 7 of the result, but the carry flip-flop is
not at logic 1.
• There is no carry from bit 6 to bit 7 of the result, but the carry flip-flop is at logic 1.
By using the carry-out from bit 6 and the carry-out from bit 7 of the result as inputs to
an XOR gate, the output of the gate will be set to logic 1 for either of the above error
conditions, signalling an overflow error at the overflow (V) flag.
The Zero flag (Z)
This flip-flop is set when every bit of the result is zero.
The Negative flag (N)
A negative result, i.e. bit 7 = 1 sets this flip-flop to logic 1.
Negation
Negation is simply the inverse of a value; therefore any value and its inverse will add to produce
zero. In binary arithmetic the additive inverse of a value is its twos complement. The ALU can be
used to negate (find the twos complement of) data A by complementing data A and then adding 1.
This involves a similar process to decrementing, except that data B is treated differently, as follows:
The control input of MUX 1 is set to logic 0, which complements data A, also data B is made zero
by putting logic 0 on MUX 2 control, and logic 1 on MUX 3. The Carry Select control input is set
at logic 1, to add 1 to data A in the adder.
The shift register is used as a simple PIPO register by applying logic 0 to the three shift controls and
logic 1 to the ~CLC input to make sure the carry is not cleared. This gives a final result of A + 1,
which is the twos complement of A.
The Shift Operations
Shift operations are controlled by the four lower order control lines, R/~L controls the direction of
shift or rotation, SHIFT/~LE has the dual purpose of enabling the shift operations if logic 1 is
applied, or acting as a LOAD ENABLE when at logic 0, allowing the shift register to be loaded or
reloaded with appropriate data. Each action of the shift register (shift, rotate or load) is actuated by
a single CK pulse. Also note that the shift register in this design does not affect the V, N or Z flags.
Shift Left (with Carry)
In this mode (with control word 10100101) input data B is kept at zero and, after the shift register is
loaded by temporarily making SHIFT/~LE logic 0 to move data from input A into the shift register,
shift is enabled by returning SHIFT/~LE to logic 1, and both ROTATE and ~CLC are disabled. The
data in the shift register will now shift one bit to the left with each CK pulse applied. This appears
to multiply the value of the data by two for each shift left, but it is a very limited multiplication
operation, because the result is reduced each time the left most bit is lost as it passes through the
carry bit. This action is therefore considered a logical, rather than an arithmetic shift.
Rotate Left (with Carry)
If rotate is activated by applying logic 1 to the ROTATE control input with SHIFT/~LE and ~CLC
also at logic 1, the data being shifted left from bit 7 and through the carry flag, is returned via the
CIN input of the shift register to re-enter at bit 0 by the action of the ROTATE MODE SELECT data
selector.
Rotate Right
When data in the shift register is rotated right, it leaves the register via bit 0 and is returned directly
to bit 7 via an internal link, without passing through the carry flag.
There are a number of other operations, such as performing 8 bit logic functions, commonly found
on microprocessors that this ALU is not designed to do. The purpose of this design is to illustrate
how the circuits described in Digital Electronics Modules 1 to 5 are really just part of a bigger
picture, they can be inter-connected in many ways to make many different circuits. This ALU
design is one example, but how you use what you learn from the pages of learnabout-electronics
and how you fit that knowledge into your own imagination is up to you.
1.
Which of the listed flip-flops is also known as a programmable flip-flop?
a) Clocked SR flip-flop.
b) JK flip-flop.
c) T-type flip-flop.
d) D-type flip-flop..
2.
Which of the following is a major advantage of the D-type flip-flop over the clocked SR type?
a) A shorter propagation delay.
6.
What type of device is shown in Fig. 5.9.1 if the waveforms illustrated are present at its CK and Q terminals?
a) Monostable.
b) Astable.
c) Bi-stable.
d) Latch.
7.
What type of circuit is illustrated in Fig. 5.9.2?
a) PIPO shift register.
8.
What type of circuit is illustrated by Fig. 5.9.3?
a) Synchronous up counter.
10.
Refer to Fig. 5.9.4. After 2 more clock pulses what will be the logic states on outputs A, B, C, D and E?
a) A=1, B=0, C=0, D=0, E=1.