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set_fix_hold [all_clocks]
set_max_area 0
psynopt -area_recovery
report_threshold_voltage_group >
/home/praveenvg/labs/temp/valcano_design/post_cts.rpt/cts_voltage_groups.rpt
Attributes:
d - dont_touch_network
f - fix_hold
p - propagated_clock
G - generated_clock
g - lib_generated_clock
Clock Period Waveform Attrs Sources
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
SYS_2x_CLK divide_by(2)
--------------------------------------------------------------------------------
****************************************
Report : clock_skew
Design : volcano
Version: M-2016.12-SP5-1
****************************************
--------------------------------------------------------------------------------
SD_DDR_CLK
SD_DDR_CLKn
****************************************
Design : volcano
Version: M-2016.12-SP5-1
****************************************
Information: Float pin scale factor for the 'max' operating condition of scenario 'default' is set to
1.000 (CTS-375)
... 20% ... 40% ... 60% ... 80% ... 100%
Clock: PCI_CLK
(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)
Clock arrival time is calculated from the source(s) of the master clock.
-----------------------------------------------------------------------------------
I_PCI_TOP/I_PCI_CORE/mega_enable_reg/CLK
0.7859 (L)
I_PCI_TOP/I_PCI_CORE/clk_gate_pad_out_buf_reg/latch/CLK (I)
Clock: v_PCI_CLK
(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)
Clock arrival time is calculated from the source(s) of the master clock.
Clock: SYS_2x_CLK
(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)
Clock arrival time is calculated from the source(s) of the master clock.
-----------------------------------------------------------------------------------
I_RISC_CORE/I_PRGRM_CNT_TOP/I_PRGRM_FSM/Current_State_reg[1]/CLK
1.0754 (L)
I_RISC_CORE/I_INSTRN_LAT/clk_gate_Crnt_Instrn_2_reg/latch/CLK (I)
Clock: SYS_CLK
Clock arrival time is calculated from the source(s) of the master clock.
-----------------------------------------------------------------------------------
I_BLENDER_1/clk_gate_rem_green_reg/latch/CLK (I)
Clock: SDRAM_CLK
(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)
Clock arrival time is calculated from the source(s) of the master clock.
-----------------------------------------------------------------------------------
I_SDRAM_TOP/I_SDRAM_READ_FIFO/SD_FIFO_CTL/U1/full_int_reg/CLK
0.9224 (L)
I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_0_reg[0]/latch/CLK (I)
Clock: v_SDRAM_CLK
(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)
Clock arrival time is calculated from the source(s) of the master clock.
Clock: SD_DDR_CLK
(L: longest arrival, S: shortest arrival, E: arrival derived from cts exceptions)
Clock arrival time is calculated from the source(s) of the master clock.
Clock: SD_DDR_CLKn
Clock arrival time is calculated from the source(s) of the master clock.
-----------------------------------------------------------------------------------------------------------------------------
****************************************
-type skew
-nworst 1
-setup
Design : volcano
Version: M-2016.12-SP5-1
****************************************
Clock: PCI_CLK
----------------------------------------------------------------------------
snps_clk_chain_0/U_shftreg_0/ff_0/q_reg/CLK
0.816 wfp-+
snps_OCC_controller/U_clk_control_i_3/pipeline_or_tree_l_reg/CLK
----------------------------------------------------------------------------
Clock: SDRAM_CLK
----------------------------------------------------------------------------
I_SDRAM_TOP/I_SDRAM_IF/mega_shift_1_reg[6][9]/CLK
0.914 wfp-+
I_SDRAM_TOP/I_SDRAM_IF/mega_shift_1_reg[5][0]/CLK
----------------------------------------------------------------------------
Clock: SD_DDR_CLK
No local skews.
Clock: SD_DDR_CLKn
No local skews.
Clock: SYS_2x_CLK
----------------------------------------------------------------------------
I_RISC_CORE/I_DATA_PATH/Oprnd_A_reg[9]/CLK
1.139 wrp-+
----------------------------------------------------------------------------
Clock: SYS_CLK
----------------------------------------------------------------------------
----------------------------------------------------------------------------
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : volcano
Version: M-2016.12-SP5-1
****************************************
Endpoint: I_PCI_TOP/I_PCI_CORE/d_out_i_bus_reg[0]
--------------------------------------------------------------------------
I_PCI_TOP/I_PCI_CORE/d_out_i_bus_reg[0]/D (SDFFARX1_LVT)
0.00 * 5.68 r
I_PCI_TOP/I_PCI_CORE/d_out_i_bus_reg[0]/CLK (SDFFARX1_LVT)
0.00 8.01 r
--------------------------------------------------------------------------
Startpoint: I_SDRAM_TOP/I_SDRAM_IF/control_bus_reg[3]
Endpoint: I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/latch
--------------------------------------------------------------------------
I_SDRAM_TOP/I_SDRAM_IF/control_bus_reg[3]/CLK (SDFFX2_HVT)
0.00 0.90 r
I_SDRAM_TOP/I_SDRAM_IF/control_bus_reg[3]/Q (SDFFX2_HVT)
0.29 1.19 r
I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/EN
(SNPS_CLOCK_GATE_LOW_SDRAM_IF)
0.00 1.68 f
I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/U1/Y (NBUFFX8_HVT)
0.11 * 1.80 f
I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/latch/EN (CGLNPRX2_HVT)
0.02 * 1.82 f
I_SDRAM_TOP/I_SDRAM_IF/clk_gate_mega_shift_1_reg[0]/latch/CLK (CGLNPRX2_HVT)
0.00 2.25 f
--------------------------------------------------------------------------
--------------------------------------------------------------------------
Startpoint: I_SDRAM_TOP/I_SDRAM_IF/DQ_out_0_reg[17]
Endpoint: sd_DQ_out[17]
--------------------------------------------------------------------------
I_SDRAM_TOP/I_SDRAM_IF/DQ_out_0_reg[17]/CLK (SDFFARX1_HVT)
0.00 0.90 r
I_SDRAM_TOP/I_SDRAM_IF/DQ_out_0_reg[17]/Q (SDFFARX1_HVT)
0.28 1.18 r
I_SDRAM_TOP/I_SDRAM_IF/sd_mux_dq_out_17/Y (MUX21X1_HVT)
0.15 * 1.43 r
--------------------------------------------------------------------------
--------------------------------------------------------------------------
Startpoint: I_RISC_CORE/I_DATA_PATH/Oprnd_B_reg[13]
Endpoint: I_RISC_CORE/R_31
I_RISC_CORE/I_DATA_PATH/Oprnd_B_reg[13]/CLK (SDFFARX1_LVT)
0.00 1.13 r
I_RISC_CORE/I_DATA_PATH/Oprnd_B_reg[13]/Q (SDFFARX1_LVT)
0.18 1.31 r
I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_3_1/CO (FADDX1_LVT)
0.07 * 1.68 f
I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_2_2/CO (FADDX1_LVT)
0.08 * 1.97 f
I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_1_2/CO (FADDX2_LVT)
0.08 * 2.26 r
I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_1_3/CO (FADDX1_LVT)
0.06 * 2.32 r
I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_0_1/CO (FADDX1_HVT)
0.17 * 2.69 r
I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_0_2/CO (FADDX1_HVT)
0.15 * 2.83 r
I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_0_3/CO (FADDX1_LVT)
0.08 * 2.91 r
I_RISC_CORE/div_4/u_div/u_fa_PartRem_0_0_4/CO (FADDX1_LVT)
0.06 * 2.97 r
--------------------------------------------------------------------------
--------------------------------------------------------------------------
Startpoint: I_BLENDER_0/s3_op2_reg[18]
Endpoint: I_BLENDER_0/s4_op2_reg[28]
--------------------------------------------------------------------------
--------------------------------------------------------------------------
--------------------------------------------------------------------------
Startpoint: I_PCI_TOP/R_687
Endpoint: pserr_n_out
-----------------------------------------------------------
-----------------------------------------------------------
-----------------------------------------------------------
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