2015 1st International Conference on Next Generation Computing Technologies (NGCT-2015)
Dehradun, India, 4-5 September 2015
Design of a Dynamic Depth High-Throughput
Multi-clock FIFO for the DSPIN
Rajeev Kamal∗ and Juan M. Moreno Arostegui†
∗ Phd Student Electronic Engineering Department Universitat Politecnica de Catalunya Barcelona, Spain
† Associate Professor Electronic Engineering Department Universitat Politecnica de Catalunya Barcelona, Spain
Abstract—The clock distribution within Chip-
Multiprocessors(CPMs) and System-on-chips (SoCs) come
to be difficult as the number of processing elements increasing
and the communication between those components are becoming
even more critical. In recent years, researchers proposed
Globally Synchronous Locally Synchronous (GALS) clocking
scheme to reduce clock skew, power, and energy consumption
in CPMs and SoCs. In this paper we have demonstrated
dynamic depth multi-synchronous first-in first-out (FIFO) buffer
which is useful for transferring data between two processing
elements within a Distributed Scalable Predictable Interconnect
Network(DSPIN).It also demonstrates dynamic calculation of
FIFO depth using two clock frequency and packet size of in
coming data.
Keywords: NOC, Asynchronous,FIFO, DSPIN, On-chip
interconnection networks, Router microarchitecture.
I. I NTRODUCTION
It is becoming more difficult and expensive to distribute
a global clock without skew within a System-on-Chip and
Chip Multiprocessors due to shrinking technologies and
design sizes. Globally Asynchronous Locally Synchronous
(GALS) systems provide a better alternative for the CMPs
and SoCs[1]. It contains different synchronous Island which
operates with their own clock frequencies and phases where
these synchronous Islands are connected of each other by
means of multi-synchronous FIFO. Achieving this task
consistently and efficiently are key challenges in GALS
system designs [2].
One structure that is best suited at the interface of different
synchronous blocks is bi-synchronous first-in first-out (FIFO)
buffer or multi-synchronous FIFO buffer [3]. The Basic
FIFO buffer must be improved to accommodate two different
self-regulating clock inputs. Data writing into the FIFO buffer
taking place with the reference of write clock domain and
data reading with the reference of read clock domain. In this
way, data can be passed smoothly between two clock domains
without issue of metastability [4]. The important application
of the bi-synchronous FIFO at the router-router interface and
the router-IP interface within DSPIN.
The presented architecture facilitates the transfer of data
between different modules, which are completely unrelated
clock domains and also provide dynamic depth calculation of
the buffer to save unwanted space of FIFO [5]. It is particularly
useful in applications where size of buffer is important rather
than latency which is critical such as in many NoC applications
[6].
978-1-4673-6809-4/15/$31.00 ©2015 IEEE
A. Previous related work
Dally, Poulten, and Balch present top-level view of bi-
synchronous FIFO architecture [7], but detail microarchitecture
is not available in the literature. Ebergen[8] and Molnar et.
al. often discuss fully asynchronous FIFO into the literature,
but these design do not utilize the clocks[9], thats why it
is difficult to apply synchronization between different clock
domain.
Table I provide information about the several different bi-
synchronous FIFO design. The work provided by Greenstreet,
the individual islands clock derived from global clock, which
have same frequency but different phase like mesosynchronous
[10]. Chakraborty et al. presented a FIFO design, it first
calculates time to develop a frequency difference estimate,
before transferring the data [11]. A linear FIFO architecture
is presented by Seizovic for data synchronization, it has
some limitation in term of initial latency [12]. Apperson et
al. represented a scalable and robust bi-synchronous FIFO
architecture but its memory size is fixed thats why it is not
provide high throughput and cost effective [13]. Similarly
Panades and Greinear proposed a FIFO architecture that
is well-suited for GALS system but does not good for
mesosynchronous system [14]. Chelcea and Nowick proposed
an alternative FIFO architecture for the application of GALS
system [15]. This designed is based on Register File and each
register has its own full and empty flags. This style is suitable
for small FIFO only.
This work uses a Register File as buffer elements, which
support speed and improve FIFO latency. Its also includes
configurable buffer depth or size, when compared with most
recent work. The proposed work has been implemented
using parametric HDL and Xilinx FPGA series. This paper is
organized as Section II describes the fundamental architectures
of all type of synchronous FIFO and their key parameters.
Section III introduces metastability and synchronization issues
and their solution. In the Section IV, the proposed design of
dynamic depth FIFO architecture is discussed. And Section V
describes HDL implementation of proposed bi-synchronous
FIFO.
II. SYNCHRONOUS FIFO
A. Serial input serial output FIFO or Linear FIFO
This section discusses the fundamental principle and prac-
tices of basic synchronous FIFO structure called Linear FIFO.
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2015 1st International Conference on Next Generation Computing Technologies (NGCT-2015)
Dehradun, India, 4-5 September 2015
TABLE I. COMPARISON OF VARIOUS BI-SYNCHRONOUS
FIFO
Fig. 1. Serial input serial output FIFO or Linear FIFO block diagram
The simplest form of FIFO consists of flip-flops which are
which are connected like a serial input serial output sift register
as shown in figure 1. Data is serially enters at the one end and
propagate through every flip-flop until it reaches at the end of
the register. Since all the movements of the data is controlled
by the single clock therefore it is called synchronous FIFO.
B. Elastic Buffer FIFO model
Alternatively the elastic buffer (EB) is the most primitive
form of a register (or buffer) that implements the ready/valid
handshake protocol [17]. The EB at the sender implements a
dual interface; it accepts new data from its internal logic and
transfers the available data to the link as shown in figure 2,
when the valid and ready signals are both equal to logic high,
so an EB can be built around a FIFO queue. An abstract
FIFO provides a push and a pop interface and informs its
connecting modules when it is full or empty. The abstract
FIFO model does not provide any guarantees on how a push
to a full queue or a pop from an empty queue is handled. The
AND gates outside the FIFO provide such protection. A push
(write) is done when valid data are present at the input of the
FIFO and the FIFO is not full.
At the read side, a pop (read) occurs when the upstream
channel is ready to receive new data and the FIFO is not
empty, i.e., it has valid data to send. In both sides of the EB
we can observe that a transfer to/from the FIFO occurs, when
the corresponding ready/valid signals are both asserted (as
implemented by the AND gates in front of the push and pop
interfaces).
C. Circular FIFO
There are major drawbacks of these available approaches
in terms of high latency, poor power efficiency and low
memory density with larger FIFO size. Since data must flow
through every element of the FIFO, therefore it increases
latency and power. It also required additional circuits for extra
control signals like ready and valid i.e. required large circuit
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Fig. 2. Elastic Buffer FIFO model block diagram
area per bit. In the recent Publications, many extension of
the basic FIFO architecture have been developed with some
elementary differences in term of datapath e.g. parallel FIFO,
square FIFO, tree FIFO and folded FIFO [18].
In the recent years, a new synchronous FIFO architecture
has been proposed called Circular FIFO as shown in figure
3. It comprises primarily circular buffer using an array
of arbitrary addressable memory elements supporting high
energy throughput and low latency, and its scalability is
radically improved due to the fact that data and clock signals
are not affected by FIFO size.
It generates two control flags called full and empty flag for
the valid data read and write into the FIFO memory. Using read
and write pointer alone to define the full and empty condition,
always comparison of pointer must be taking place. For the
empty condition the value of read pointer must be equal to the
value of the write pointer whereas for the full condition, firstly
increases the size of address by one bit then equivalence tests
of lower bits and Ex-or of MSB of address pointers. Following
inequalities must be satisfied for the correct operation of the
FIFO.
rptr ≤ wptr ≤ rptr + N (1)
where; rptr = read pointer wptr = write pointer and N =
number of words
III. SYNCHRONIZATION AND METASTABILITY
Synchronization is a fundamental problem in a digital
system, which missing a single global timing reference.
Synchronization is a process through which an ordering of
events performed on the signal lines. There are five way to
represents the classification of timing relationship between
signal and clock, their types and definitions are discussed in
[19]. Within a flip-flop, the input changes during the setup
or hold time window, the flip-flop enters a unstable state
called metastable state resulting output reveals an in-between
voltage value.
Metastable state is a fundamental problem of modern
digital systems, whenever flip-flop not receiving a stable input
value near the positive or negative edge of the system clock.
Metastability is resolved in the flip-flop itself after resolution
time Tr(time required to reach a stable state is called resolution
time). It is characterize by the PDF (probability distribution
function)
−Tr
p(Tr ) = e τ (2)
2015 1st International Conference on Next Generation Computing Technologies (NGCT-2015)
Dehradun, India, 4-5 September 2015

TABLE II. SAMPLE OF MTBF(T R ) COMPUTATION

Fig. 3. Circular FIFO model block diagram

Whereτ is the time decay constant and depend upon

the electrical property of flip-flop. The average time interval
between two synchronization failures is known as mean time
between synchronization failures (MTBR) and it is expressed
as a function of Tr .
−Tr
e τ
M T BR(Tr ) − (3)
ω ∗ fclk ∗ fd

where;ω = the susceptible time window fd = the rate

of change of input data and fc lk = the system clock
frequency Synchronization methods are used to remove
or reduce the probability of metastability. From table II it
can be seen that increasing the value of Tr , it increases Fig. 4. All type of synchronizers
the value of MTBR.Here consider fc lk is 50MHz, data
rate is 0.1fclk, ω of 0.1ns and τ of 0.5ns. There are three
types of synchronizer available called single-FF, Double-FFs depth in signal, FIFO memory fixes the size of the variable
and Triple-FFs synchronizer as shown in figure4.It can register file as shown in figure 5. Full flag generator and
remove metastability within a digital systems. In the diagram Empty flag generator, calculate the write address and read
syncronizer flip-flops provide the sufficient resolution time to address signal respectively for the FIFO memory. High level
move metatstable state to one of the stable state of input signal. diagram of blocks within the proposed bi-synchronous FIFO
is shown in figure 6.

IV. PROPOSED DYNAMIC DEPTH

BI-SYNCHRONOUS FIFO
The section describes a proposed architecture of dynamic
depth bi-synchronous FIFO supports data transfer between two
different arbitrary clock domains. It also describes, algorithm
of depth calculation of the proposed FIFO, the microarchi-
tectures of the different sub-modules as full-flag generation,
empty-flag generation, gray code pointer etc.
B. FIFO depth calculation
Bi-synchronous FIFO is very useful for synchronizing
between two different clock domains. Therefore, depth cal-
culation is very important to pass the data securely between
unrelated clock domains.Basically depth of the Bi-synchronous
FIFO depend upon three things, write clock frequency, read
clock frequency and the size of the input data packet.

A. Overall Architecture 1) formula to depth calculation :

fr clk
The working architecture of proposed bi-synchronous d = [p − ( ∗ (p) ∗ f rac1Rd )] (4)
FIFO is shown in figure 5, which is used to transfer data fw clk
between sender and receiver. The sender clock (wr clk) and where; d = depth of proposed FIFO;
receiver clock (rd clk) are not related to each other in term p = packet size of the input data;
of their phase and frequency. Before sending any data, the fr clk = read side clock frequency;
depth calculator, calculates the depth of FIFO on the basis fw clk = write side clock frequency;
of wr clk, rd clk and pkt size signal. Where wr clk, rd clk, and Rd = read side delay in .. between reads:
and pkt size are write clock frequency, read clock frequency 2) Example : Consider the situations here. Given data
and the packet size of the incoming data. On the basis of for the both sides of FIFO :

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2015 1st International Conference on Next Generation Computing Technologies (NGCT-2015)
Dehradun, India, 4-5 September 2015
Fig. 5. Over all architecture of the proposed FIFO
Write clock frequency = 15MHz (fw clk)
Maximum size of the Burst = 100 bytes (p)
Read clock frequency = 10MHz (fr clk)
Delay between reads = 2 clock cycles (Rd )
FIFO Depth(d)=[100-( 10 1
15 *100* 2 )]
500
=[100 - ( 15 )]
= 67
So we will need to design a FIFO 67 deep
V. DETAIL ARCHITECTURE OF PROPOSED FIFO
The complete architecture of the proposed bi-synchronous
FIFO is shown in figure 6. In this high-level diagram, there
are four major blocks namely, Register file array, Full flag
generation, Empty flag generation, and depth calculator. The
WRITE logic is shown on the left hand side where as READ
logic is on the right hand side of figure 6.
On the READ side FIFO calculates whether or not it is
empty, on the basis of Rd enable signal, receiver can consume
all the data available within the FIFO memory. On the WRITE
side, the FIFO indicates whether or not it is full. The sender
should only send data when the FIFO is not full and asserting
wr en signal. On the READ side FIFO indicates whether or
not it is empty for the receiving the data. Actually the sender
cannot write data within the FIFO memory when full signal
is generated and receiver cannot read from the FIFO memory
when empty signal is generated.
How FIFO pointers works, it is very useful for the better
understanding the FIFO design. There are two types of pointer
available called write pointer and read pointer where write
pointer always points to next word to be written and similarly
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Fig. 6. High-level block diagram of proposed bi-synchronous FIFO
read pointer always points to the current FIFO word to be read.
Initially or on reset both pointers set to be zero, in the case
of write operation, the write pointer is incremented to point
to the next location to be written once a memory location
that pointed by write pointer is written, similarly a location
that is indicated by read pointer is read, the read pointer is
incremented to point to the next location to be read.
A. Gray Coding and Address Pointers
The suggested architecture uses two pointers called READ
and WRITE address pointers to track vacancy of the FIFO.
The size of the pointer = log2 (N ) + 1, where N = memory
word size. The pointer requires one more bit for the generation
of full flag and empty flag.
Due to the metastability issue, the pointers are transferred
to a Gray code format before the clock cross domains.
The pointers again converted back to Binary representation
into other clock domain because arithmetic of binary
representation is quite easy and understandable. Since Gray
code representation is a single bit change code format, thats
why the chance of metastability issue will be very less in
case of clock domain crossing. In the case of Binary pointers,
trying to synchronize binary count value from one clock
domain to another clock domain is challenging. Consider an
example, when pointer value changes from 0111 to 1000, then
all bits changed and increase the probability of metastability.
The implementation of binary-to-gray conversion and grayto-
binary conversion requires special circuit that is based
on xoring operations. In the case of binary-to-gray, an
n-bit binary vector (bn − 1, bn − 2, ..., b2, b1) can be used to
convert to n-bit gray coded vector(gn − 1, gn − 2, ..., g2, g1) as
shown in given equation 5, where + indicate the XOR function.
gn − 1 = bn − 1, gn − 2 = bn − 1 + bn − 2, gn − 3
= bn − 2 + bn − 3, . . . , g1 = b2 + b1, g1 = b1 + b0 (5)
Similarly in In the case of binary-to-gray, an n-bit gray
coded vector (gn − 1, gn − 2, ..., g2, g1) can be used to convert
2015 1st International Conference on Next Generation Computing Technologies (NGCT-2015)
Dehradun, India, 4-5 September 2015
Fig. 7. Four bits binary sequence for the pointers
to n-bit binary coded vector (bn − 1, bn − 2, ..., b2, b1) as
shown in given equation 6, where + indicate the same XOR
function.
gn − 1 = bn − 1, bn − 2 = bn − 1 + gn − 2, bn − 3
= bn − 2 + gn − 3, . . . , b1 = b2 + g1, b1 = b1 + g0 (6)
B. Handling of pointers
This subsection deals with handling the binary pointers
as shown in figure 7. One can observe that from the basic
of binary number system, they are repeated sequence with
changed MSB. Consider an example, a 4 bit binary number
start with 0 to 7 with MSB 0 and this sequence repeats again
with MSB 1 as shown in figure 7. Using this concept, the full
flag and the empty flag can be easily generated.Here lower bits
are consider for the addressing the memory buffer location.
• Empty Flag Generation: In this proposed bisyn-
chronous FIFO architecture the empty flag will be
produced in the right side or read clock domain
whenever Register File is unoccupied, immediately
the empty flag is generated. From figure 7, when
synchronized write pointer is simply equal to the read
pointer, the FIFO is empty. The condition for the
empty flag generation in the read clock domain is
rptr[(n − 1)downto0] = syncw ptr[(n − 1)downto0]
(7)
• Full Flag Generation: Similarly in this proposed bisyn-
chronous FIFO architecture the full flag will be pro-
duced in the left side or write clock domain whenever
Register File is fully occupied, immediately the full
flag is generated. From figure 7, when synchronized
read pointer is equal to the write pointer except MSBs,
the FIFO is full. The condition for the full flag
generation in the write clock domain is
wptr[n − 1]! = syncr ptr[n − 1]
wptr[(n-2) downto 0] = syncr ptr[(n − 2)downto0](8)
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VI. CONCLUSION
The projected bi-synchronous FIFO design is well-matched
for the many applications especially at the interface of two
different clock domains. It can be utilized as a drop-in module
at the router interface of the multi-synchronous networkon-
chip. This design provides high sturdiness, variable size
register files, good energy proficiency, high frequency clock
support and good scalability.
This FIFO architecture is implemented using parametric
VHDL and synthesis is performed using Xilinx ISE 12.1.The
functional simulation and Verification is performed by the
Modelsim ISE 6.0d.
ACKNOWLEDGMENT: The authors are grateful to their
respective university and tutors for their help and support.
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