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Abstract—We investigate the manufacturability of 20-nm However, there are several challenges in building such
double-gate and FinFET devices in integrated circuits by pro- devices in CMOS technology. For a double-gate MOSFET
jecting process tolerances. Two important factors affecting the device with 20 nm or shorter gate length, in order to get
sensitivity of device electrical parameters to physical variations
were quantitatively considered. The quantum effect was computed nearly ideal subthreshold swing and small drain induced
using the density gradient method and the sensitivity of threshold barrier lower (DIBL) effect, the silicon body must be very thin
voltage to random dopant fluctuation was studied by Monte Carlo ( , where is the body thickness,
V
simulation. Our results show the 3 value of T variation caused is the effective channel length, and is the oxide thickness)
by discrete impurity fluctuation can be greater than 100%. Thus, and fully depleted [2]. The threshold voltage is insensitive to
engineering the work function of gate materials and maintaining a
nearly intrinsic channel is more desirable. Based on a design with channel doping except at very high concentration. We observed
an intrinsic channel and ideal gate work function, we analyzed less than a 50–mV shift of the threshold due to the channel
the sensitivity of device electrical parameters to several important doping up to cm for a double-gate device with 20–nm
physical fluctuations such as the variations in gate length, body gate length and 5-nm body thickness. On the other hand,
thickness, and gate dielectric thickness. We found that quantum excessive impurity concentrations can significantly degrade
effects have great impact on the performance of devices. As a
result, the device electrical behavior is sensitive to small variations the mobility of carriers, and we will see in the next section
of body thickness. The effect dominates over the effects produced that the statistical spread of the threshold voltage could be
by other physical fluctuations. To achieve a relative variation of very large due to random placement of discrete impurities
electrical parameters comparable to present practice in industry, in the channel. Another choice is to have a nearly intrinsic
we face a challenge of fin width control (less than 1 nm 3 value channel but engineer the work function of the gate materials
of variation) for the 20-nm FinFET devices. The constraint of the
for control. According to the ITRS roadmap, the absolute
1 2 A
gate length variation is about 10 15%. We estimate a tolerance
of 3 value of oxide thickness variation and up to 30% value of threshold voltage will be about 0.2 0.3 V for 20-nm,
front-back oxide thickness mismatch. low-power MOSFET devices. This means that we should have
Index Terms—Double gate, FinFET, Monte Carlo simulation, a gate work function such that the Fermi energy lies between
process variations, quantum effect, sensitivity. the conduction band edge and midgap of silicon for NMOS
devices, and between midgap and the valence band edge of
silicon for pMOS devices. Polysilicon with dual type doping
I. INTRODUCTION (N and P ) has conventionally been used as highly conduc-
tive gate materials for bulk MOSFETs. However, there are no
A S THE GATE length of MOSFET devices shrinks down
below 20 nm, double-gate device structures are emerging
as strong candidates despite the added process complexity
handy gate materials with the required work functions for us
to do similar things for fully depleted double-gate MOSFET
needed to build such devices. Compared with conventional devices with ultrashort channel length. Because of this reason,
single gate bulk MOSFETs, double-gate devices may be more there has recently been much research attempting to engineer
easily scaled down to 20 nm. This is because double-gate struc- the work function of existing materials. There is more freedom
tures have better control of the short-channel effect and near to adjust the threshold voltage of an asymmetric double-gate
ideal turn-off slope, thus lower leakage level can be maintained device (e.g., we can choose two different types of materials for
even with very short gate length. Double-gate MOSFETs are its front and back gates [3], or use two different gate dielectric
thus more appropriate for low-power or high-performance ap- thicknesses), but its manufacture will involve greater process
plication in the future. The FinFET devices, which are actually complexity. The large parasitic resistance between the channel
vertical double-gate MOSFET devices, have experimentally and source/drain (S/D)is another challenge to the performance
demonstrated such potential capability [1]. of FinFET devices [4].
In general, the fabrication process of double-gate MOSFET
devices (e.g., FinFET) is more complicated than that of single
gate devices, which will potentially bring more nonuniformity
during fabrication. For example, in FinFET devices, the gate
Manuscript received February 21, 2003; revised August 12, 2003. This work
was supported by the UC-SMART program under Grant 97-03. The review of oxide is on the etched sidewall of the fin, and its uniformity
this paper was arranged by Editor R. Shrivastava. is more difficult to control. The channel-oxide interface con-
The authors are with the Department of Electrical Engineering and Com- dition is determined by the sidewall roughness of the fin. In
puter Sciences, University of California, Berkeley, CA 94720 USA (e-mail:
xiongsy@eecs.berkeley.edu). this paper we first investigate the random and discrete nature
Digital Object Identifier 10.1109/TED.2003.818594 of dopant atoms in affecting the threshold voltage of symmetric
0018-9383/03$17.00 © 2003 IEEE
2256 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 11, NOVEMBER 2003
TABLE I
NOMINAL PARAMETERS OF 20-nm SYMMETRIC DOUBLE-GATE DEVICES WITH INTRINSIC CHANNEL
Fig. 10. NMOS I variation with body thickness. Fig. 12. Variation of DIBL (V 0 V ) with body thickness
(NMOS).
TABLE II
3 VALUES OF DEVICE ELECTRICAL PARAMETER VARIATIONS (IN EACH CASE, TWO NUMBERS
ARE GIVEN. THE FIRST IS FOR NMOS AND THE SECOND FOR pMOS DEVICES)
lithography processes have 10 larger CD variations. Applica- As a result, the threshold voltage and current more strongly
tion of FinFET devices in IC products will strongly depend on depend on the body thickness. For 20-nm physical gate length
the success in tight fin width control from emerging technolo- and 5-nm body thickness (or fin width), we predict that 3
gies. Our results show a 2 3 nm allowable gate length varia- values of body thickness variation must be controlled under
tion, which is less tight than the requirement on body thickness. 1 nm to meet the present logic circuit design requirement.
planar oxide thickness variation is now obtainable by The acceptable 3 value of gate length variation is 2 3 nm.
the industry. Excluding possible gate leakage current increase, the device
structure can tolerate 3 value of oxide thickness
variation and up to 30% front-back oxide thickness mismatch
without degrading the electrical performance greatly.
VII. MISMATCH OF THE OXIDE THICKNESS
Shiying Xiong received the B.S. and M.S. degrees in Jeffrey Bokor (S’75–M’90–SM’95–F’00) received
applied physics from Tsinghua University, Beijing, the B.S. degree in electrical engineering from the
China, in 1995 and 1998, respectively. From 2000, Massachusetts Institute of Technology, Cambridge,
he joined the University of California, Berkeley, to in 1975, and the M.S. and Ph.D. degrees in electrical
study for the Ph.D. degree in solid state devices. engineering from Stanford University, Stanford, CA,
He did research on semiconductor quantum well in 1976 and 1980, respectively.
structures and high-Tc superconducting materials He held management positions as Head of the
at Tsinghua University. From 1998 to 2000, he was Laser Science Research Department at Bell Labs,
studying at the Physics Department of the University Holmdel, NJ, from 1987 to 1990, and Head of the
of California, Berkeley. His research at Berkeley ULSI Technology Research Department at Bell
was on optimizing the performance of advanced Labs, Murray Hill, NJ, from 1990 to 1993. During
MOSFET transistors and investigating the impacts of process variations. His these years, he did research on novel sources of ultraviolet and soft X-ray
current research interests are electrical transport in ultrascaled devices and coherent radiation, advanced lithography, picosecond optoelectronics, semi-
nanocontacts. conductor physics, surface physics, MOS device physics, and integrated circuit
process technology. He was appointed Professor of electrical engineering and
computer sciences at the University of California, Berkeley, CA, in 1993, with
a joint appointment at the Lawrence Berkeley National Laboratory, Berkeley.
His current research activities include novel techniques for nanofabrication,
new devices for nanoelectronics, and extreme ultraviolet lithography.
Dr. Bokor is a Fellow of the APS and OSA.