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silicon
fin
polysilicon tsi
gate
gate
gate
W fully
depleted
partially
buried oxide depleted
box
Fig. 1 TEM photograph showing cross-section of FinFET
Fig. 3 Potential distribution in FD FinFET in inversion (VG ¼ 1.2 V) for
Experimental: Standard Unibond1 silicon-on-insulator (SOI) wafers VG2 ¼ 40 V
were used as starting material. The thickness of the SOI film and buried Top of fin fully depleted, bottom partially depleted with floating body
oxide (BOX) are 110 and 200 nm, respectively. After the growth of a
50 nm oxide ‘hard mask’ the SOI film was doped using a 22 keV boron
implant with a dose of either 5 1012 cm2 or 3 1013 cm2, resulting A floating body can be created in the fully depleted device by
in channel doping concentrations of 4 1017, which produced fully applying a negative back-gate bias. The potential distribution at the top
depleted FinFETs and 2 1018 cm3, which resulted in the formation of the fin is, however, unaffected by the application of the bias and the
of partially depleted FinFETs at the end of the process. Lithography and top of the fin remains fully depleted. Fig. 3 shows the potential
RIE were used to etch the hard mask and the SOI layer to define 60 nm- distribution in a device biased into front inversion (VG ¼ 1.2 V) and
wide silicon fins. All wafers received a 3 nm oxidation to repair the back accumulation (VG2 ¼ 40 V). The interfaces at the top and side-
damage from the RIE fin-etch. The wafers were then dipped in HF to walls of the device are at a potential of 0.95 V, and the back interface is
strip off the 3 nm oxide and subsequently annealed in hydrogen to at 0 V. Owing to the negative back-gate bias an accumulation layer and
smoothen the fin sidewalls and reduce gate leakage. A pre-gate oxide a floating body form at the bottom of the fin and the GIFBE becomes
HF dip was then carried out and a 1.8 nm gate oxide was grown by wet visible (Fig. 4). The subthreshold slope, however, does not increase
oxidation. Polysilicon was then deposited and doped N-type by phos- when the negative back-gate bias is applied as it would in single-gate
phorus ion implantation. Lithography and RIE trim-etch were used to SOI MOSFETs (Table 1). In the FinFET the top of the fin remains fully
define gate lengths down to 70 nm. Source and drain extensions were depleted when the back of the device is accumulated. The entire
formed by high angle (45 ) tilted arsenic ion implantation (7 keV, FinFET behaves as the parallel association of two transistors: a top
5 1014 cm2) followed by zero-tilt implantation for the S&D them- fully depleted device with lower threshold voltage, and a bottom
selves (60 keV, 3 1015 cm2). Impurity activation was achieved by a partially depleted device with higher VTH. The top of the device controls
10 s, 1000 C RTA step. Conventional Al=Si metallisation was used to the subthreshold current and, as a result, the overall subthreshold slope
complete the process. Devices with gate length ranging from 0.1 to has a value close to 60 mV per decade. Thus a fully depleted FinFET
10 mm (multi-fin devices) were fabricated. The TEM cross-section of a with back accumulation can simultaneously exhibit fully depleted
device is shown in Fig. 1. characteristics such as a 60 mV=dec subthreshold slope, and partially
The gate-induced floating body effect (GIBFE) is caused by the depleted characteristics such as the GIFBE. A FinFET that is initially
tunnelling of electrons from the valence band of a MOSFET into the partially depleted, on the other hand, does not display low subthreshold
conduction band of the polysilicon gate. The effect also sometimes slope values (Table 1).
transconductance, s ¥ 10-6
2
Conclusion: Full and partial depletion effects have been studied in
FinFETs. Unlike single-gate SOI MOSFETs, which exhibit either
fully depleted or partially depleted characteristics, FinFETs can
VG2 = 0, -20, -40 and -60 V
1 display both types of characteristics simultaneously. Fully depleted
FinFETs with back accumulation exhibit simultaneously FD features
VD = 0.05 V such as a low subthreshold slope and PD features such as the gate-
0
0 0.5 1.0 1.5
induced floating body effect.
gate voltage, V
Fig. 4 Measured transconductance of fully depleted FinFET for different # IEE 2005 21 January 2005
values of back-gate voltage Electronics Letters online no: 20050281
VD ¼ 50 mV, L ¼ 10 mm doi: 10.1049/el:20050281
W. Xiong, C. Rinn Cleavelin, R. Wise, S. Yu and M. Pas (SiTD, Texas
Instruments Incorporated, 13560 North Central Expressway, Dallas,
Table 1: Subthreshold slope, S, in partially depleted and fully
TX, USA)
depleted FinFETs with several back-gate bias values
R.J. Zaman, M. Gostkowski and K. Matthews (ATDF Inc., 2706
Fully VG2 ¼ 0 V VG2 ¼ 20 V VG2 ¼ 40 V VG2 ¼ 60 V Montopolis Drive, Austin, TX, USA)
depleted
S ¼ 63 mV=dec S ¼ 62 mV=dec S ¼ 62 mV=dec S ¼ 62 mV=dec C. Maleville and P. Patruno (SOITEC S.A., Parc Technologique des
Partially Fontaines—38190 Bernin, France)
depleted VG2 ¼ 0 V — — —
T.-J. King (Department of Electrical Engineering and Computer
S ¼ 78 mV=dec — — — Sciences, University of California, Berkeley, CA, USA)
J.P. Colinge (Department of Electrical and Computer Engineering,
University of California, Davis, CA, USA)
Table 2: Occurrence of GIFBE in partially depleted FinFETs with E-mail: colinge@ece.ucdavis.edu
different gate length and width
L (mm) W (mm) L W (mm2) GIFBE? References
0.1 0.065 0.0065 No
1 Cassé, M., Pretet, J., Cristoloveanu, S., Poiroux, T., Fenouillet-Beranger,
0.1 0.1 0.01 No F., Fruleux, F., Raynaud, C., and Reimbold, G.: ‘Gate-induced floating-
0.4 0.065 0.026 No body effect in fully depleted SOI MOSFETs with tunneling gate oxide
0.35 0.1 0.035 Yes and back-gate biasing’, Solid-State Electron., 2000, 48, (7), pp. 1243–
1247
2 Shino, T., Higashi, T., Kusunocki, N., Fujita, K., Ohshawa, T., Aoki, N.,
In single-gate SOI MOSFETs the GIFBE effect is observed only if Tanimoto, H., Minami, Y., Yamada, T., Morikado, M., Nakajima, H.,
the volume of the floating body is large enough, and the effect becomes Inoh, K., Hamamoto, T., and Nitayama, A.: ‘Fully depleted FBC (floating
more pronounced when the width, W, and=or the length of the device, L, body cell) with enlarged signal window and excellent logic process
is increased [2]. A similar observation can be made in FinFETs. Table 2 compatibility’, Tech. Dig. IEDM, 2004, pp. 281–284