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Abstract—An analytical approach for modeling the electrostatic the potential in triple-gate FETs, whose overview can be found
potential in nanoscale undoped FinFETs is derived. This method in [4]. To our knowledge, in the work published so far, the
uses a 2-D solution for this potential within a double-gate FET and results of this 3-D problem always led to an analytical solution
takes into account the top gate electrode as the third dimension
by applying the conformal mapping technique. Herewith, an an- with a converging infinite series formalism. In order to obtain
alytical closed-form model for the height of the potential barrier a compact model equation, for certain geometry scaling, e.g., if
below threshold is defined which includes 3-D effects. From that, the channel thickness is less than the channel length, this series
models for subthreshold slope and threshold voltage of nanoscale can be approximated by its first terms [2], [4]–[6]. However,
triple-gate FETs are derived. The results are in good agreement increasing deviations can be expected if the channel length is
with numerical device simulation results and measurements for
channel lengths down to 20 nm.
further scaled down. The approaches differ in the boundary
conditions defined at the bottom of the channel. In [2] and [6], it
Index Terms—Conformal mapping, FinFET, modeling, is assumed that no field lines enter the channel region from the
MOSFET, potential, threshold voltage, trigate.
buried oxide. On the other hand, in [4] and [5], the influence of a
back-gate bias is taken into account. The approaches presented
I. INTRODUCTION in [2], [5], and [6] solve the 3-D potential in a volume, including
the channel region and the gate oxide, whereas in [4], the
T HE ONGOING miniaturization of microelectronic de-
vices requires a continuous improvement of compact
models used for circuit simulations. Today, research on sub-
potential is solved only in the silicon channel while applying
boundary conditions at the silicon-to-oxide interface derived
50-nm technologies focuses on advanced devices with SOI-type from 1-D analysis. This avoids an accurate solution for corner
structures. These multiple-gate devices such as FinFETs [1], [2] effects in the silicon channel. However, the solution in [4]
are strongly influenced by 3-D effects [Fig. 1(a)]. A complete takes into account a mobile-charge term, making the approach
compact model for FinFETs, based on 3-D approximation, interesting for the near-threshold regime of undoped devices.
is currently missing. However, one is urgently needed, since In this paper, we like to contribute an analytical structure-
FinFETs are among the most promising nanoscale devices [3]. oriented model for the potential barrier in undoped FinFETs,
Electrical device parameters such as leakage current below which inherently includes short-channel and corner effects.
threshold and threshold voltage are controlled by the height Since we neglect mobile charge, our potential solution is only
of the potential barrier which the carriers have to surmount to accurate in the subthreshold regime. The analytical approach
enter the drift region of the channel. This barrier is located at is derived by applying the conformal mapping technique [7],
the minimum of the electrostatic potential along the direction which, in [8], was introduced in MOS transistor modeling for
from the source to the drain. Furthermore, the most leaky path the first time. The results of our model have already been pub-
in the channel cross section will be at the position with the lished in [9]. Here, for the first time, the details of the mathemat-
highest electron concentration and, hence, where the maximum ical approach and the derived model equations are presented.
potential is located. In the first step, a proper 2-D solution for the potential φdg
The potential barrier is defined by a 3-D potential problem. within a double-gate FET (DG-FET) is defined [10], [11].
There has already been a published work on analytically solving Therefore, the problem is reduced to 2-D. From this model, we
find the position of the potential barrier along the center line of
the channel.
Manuscript received July 23, 2008. Current version published November 26, In the second step, at this position, we solve the 3-D potential
2008. This work was supported by the German Federal Ministry of Education problem in a cross section of the triple-gate device, taking
and Research under Contract 1764X06. The review of this paper was arranged
by Editor C. McAndrew. into account the third gate electrode by applying again the
A. Kloes and M. Weidemann are with the University of Applied Sci- conformal mapping technique. Here, the same conformally
ences Giessen–Friedberg, 35390 Giessen, Germany (e-mail: alexander.kloes@ mapped structure, as defined in [8], will be used to model the
ei.fh-giessen.de).
D. Goebel is with LTi Drives GmbH, 35633 Lahnau, Germany. influence of the top gate on the potential barrier. We assume
B. T. Bosworth is with the Department of Electrical Engineering, Princeton that, in the triple-gate structure, the distance of the potential
University, Princeton, NJ 08544 USA. barrier from the source is nearly the same as in the DG-FET,
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org. which can be justified from numerical simulations. In the
Digital Object Identifier 10.1109/TED.2008.2006535 subthreshold regime of operation, the most leaky path is close
Vgs = Vgs − Vfb . (3) The 2-D solution from the DG model is used as a particu-
lar solution of the 3-D Laplace equation for the electrostatic
The center line from the source√to the drain (i.e., z = 0) is potential φ. Following the approach given in [8], we obtain
mapped upon a circle of radius 1/ k in upper plane W transformed boundary conditions for the structure, which define
the solution for the potential ϕ(x, y, z)
1
u = √ cos(θ) (4)
k ϕ(x, y, z) = φ(x, y, z) − φdg (x, z). (11)
1
v = √ sin(θ). (5) In the channel cross section, we get a 2-D potential problem
k
with a bias only applied to the top gate. We have to assure that
√
Here, θ is the angle along a half circle of radius 1/ k in the error introduced at boundary T [refer to Fig. 1(c)] can be
plane W . neglected. This is the case for a typical triple-gate FET where
At the position of the potential minimum, the conditions toxt is much less than the distance between the source end of the
channel and the position where the potential barrier is located.
∂φdg (x, z) ∂φdg (x, z) It should be noticed that, at this stage, the potential problem
= 0 and =0 (6) does not fulfill the 2-D Laplace equation, because the influence
∂x ∂z
xm z=0 in the x-direction has to be taken into account.
must be fulfilled. Conformal mapping scales the electric field
by the derivative of the mapping function [7]
C. Geometry Scaling to Include 3-D Effect
∂φdg (z) ∂φdg (w) ∂w
= · So far, potentials φ and ϕ are neither given by a 2-D Laplace
∂z ∂w ∂z . (7)
equation in the device cross section nor are they a solution of a
2-D potential problem. The field components in the x-direction
Therefore, we obtain the position of the potential barrier along have an increasing influence on the potential in the cross section
the center line of the channel as well in complex plane W by for decreasing channel length. The electric field components in
inserting (4) and (5) into (2) and solving for the root of its plane yz are reduced by this effect compared to a strictly 2-D
derivative with respect to θ potential problem, and hence, the influence of the top gate
increases.
∂φdg (θ) In order to include the effect of the third dimension, we
= 0. (8)
∂θ modify the device geometry in a special way. Following this
θm
approach discussed in this section, the conformal mapping tech-
This equation has been solved in closed-form nique can be applied in the channel cross section in plane yz
for solving a 2-D Laplace equation in ϕ while taking the 3-D
1
2 (k + 1)Vds effect into account.
θm = π − arccos √
. (9)
k 2Vgs − 2Vbi − Vds We start from the 3-D Laplace equation
Manipulation results in
2
∂2ϕ ∂2ϕ ∂2ϕ 1 ∂ ϕ
+ 2 + + − 1 · 2 = 0. (16)
∂x2 ∂y ∂z 2 a2 ∂y
In order to solve for the potential ϕ in plane zy by conformal
mapping, we have to fulfill
∂2ϕ ∂2ϕ
Δϕ = + =0 (17)
∂y 2 ∂z 2
so the scaling factor a results from the condition
2
∂2ϕ 1 ∂ ϕ
2
+ 2
− 1 · 2 = 0. (18)
∂x a ∂y
For transformed boundary conditions, near the top gate, we
obtain the largest absolute values for ∂ 2 ϕ/∂x2 and ∂ 2 ϕ/∂y 2 .
If Tch Hch , closer to the substrate, both terms become ≈ 0,
and (18) becomes valid for any value of a. That is reasonable
because, here, the 3-D solution for φ tends to be equivalent
to the potential within the DG-FET, and hence, ϕ ≈ 0 and is
independent of a.
That is the reason why we calculate the scaling parameter a
from the boundary at the top gate, showing a constant potential
φ. Here, from (11), we can follow
∂2ϕ ∂φ2dg Fig. 2. (a) Device cross section in plane Z and its conformally mapped
2
=− (19) representation in plane W . (b) Boundary condition along electrode B in
∂x ∂x2 plane W . The parabolic boundary condition in plane Z results in an elliptically
2
∂ ϕ ∂φ2dg shaped potential profile along axis u.
= − . (20)
∂z 2 ∂z 2
Hch + toxt Tch . Nevertheless, the approach can also be ap-
The second derivatives of the DG solution have been obtained plied to a four-corner structure, as given in [10].
in Section II-A from [10] and [11]. In the channel cross section, the gate oxide of thicknesses
From (17), we get toxs and toxt , having a dielectric constant εox , is replaced by
that of equivalent thicknesses t̃oxs and t̃oxt , respectively, with
∂2ϕ ∂2ϕ ∂φ2dg the same dielectric constant as the silicon body [8]
= − = . (21)
∂y 2 ∂z 2 ∂z 2
εs εs
t̃oxt = t̃ toxs = toxs . (25)
Now, we can solve (18) for parameter a εox oxt εox
∂2ϕ ∂2ϕ ∂φ2 Fig. 2(a) shows the 2-D structure of plane yz with the given
dg ∂φ2
1 ∂x2 + ∂z2 ∂x2 + ∂zdg boundary conditions in complex plane Z with ẑ = x̂ + iŷ. Ac-
=
2
= . (22)
a ∂2ϕ ∂φ2dg cording to (11), along electrodes A and C, we get the boundary
2 ∂z ∂z 2 condition ϕ = 0. The boundary condition along electrode B
results from the DG solution
With scaling of all dimensions and boundaries in direction y
by a factor of 1/a, we can describe the 3-D potential problem ϕ̄(x̂) = Vgs − φdg (xm , z). (26)
by a 2-D Laplace equation in the cross section. Therefore, in the
subsequent approach for solving the 2-D potential problem by The conformal mapping function which results in the rep-
conformal mapping, we use the following device parameters: resentation of the 2-D structure in complex plane W [refer to
Fig. 2(b)] with w = u + iv is given by [8]
Hch
Hch = (23)
a πẑ
toxt w = f −1 (ẑ) = cosh . (27)
toxt = . (24) Tch + 2t̃oxs
a
For calculation of the potential solution ϕ in the conformally
D. Solving 2-D Laplace Equation at Potential Barrier mapped geometry, the Poisson integral [7] in complex plane W
has to be solved
In the next step, we solve the 2-D Laplace equation (17)
by using the conformal mapping technique. In order to keep 1
1 v
the expression at a manageable level, we use the two-corner ϕ(u, v) = ϕ̄(ū)dū. (28)
π (ū − u)2 + v 2
structure introduced in [8]. For that, we have to assume that −1
KLOES et al.: MODEL FOR POTENTIAL BARRIER IN FinFETs RESULTING IN ANALYTICAL EQUATIONS 3471
Integration results in
1
1 v
ϕ(u, v) = ϕ̃(ū)dū
π (ū − u)2 + v 2
−1 Fig. 4. Potential φ for (a) Vds = 0 and various gate biases and for (b) Vgs =
−0.55 V and various drain biases along the trace, as defined in the upper plot
= Vgs − φdg,m in devices with a channel length of 20 nm. (Solid lines) Results calculated by
the model. (Dashed lines) Sentaurus. In both plots, the accuracy of the model is
1 better than 20 mV.
× 1 − (u − iv) + 1 − (u + iv) − v .
2 2
2
(31) For comparison with the numerical device simulation results
computed with Sentaurus [12], we compare the potential along
Using this result together with (27), we can calculate the the silicon surface and in the middle of the channel. In Fig. 4(a),
potential ϕ for each position (y , z)=(x̂,
ˆ iŷ). If we add the DG the trace is defined which is followed within the device cross
solution φdg (x, z) according to (11), we obtain the potential φ section in the subsequent plots.
in the channel cross section at position (y , z) and, finally, by Fig. 4(a) shows the potential along the trace in a device with
rescaling y according to (13), at position (y, z). 20-nm channel length and a bias of Vds = 0.05 V. We observe
very good agreement with the numerical results, even in the
corner regions of the device. In Fig. 4(b), we investigate the
III. RESULTS OF 3-D POTENTIAL SOLUTION
influence of an applied drain voltage on the potential. Even
For evaluation of our analytical result, we consider triple-gate for Vds = 1 V, we obtain good agreement along the trace. The
devices with toxs = toxt = 2 nm and εox = 7ε0 and aluminum accuracy in both plots is better than 20 mV.
gate (work-function difference: −0.55 V). In Fig. 3, the poten- Below threshold, the most leaky path will be located at
tial profile in the middle of the channel as it results from (31) the bottom middle of the channel. The height of the potential
is shown. Due to the approximation of ϕ̃ in (30), we notice a barrier φm at this position is essential for the calculation of
slight ripple along the boundary at the top gate. the subthreshold current or the threshold voltage in Sections IV
3472 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 12, DECEMBER 2008
and V, respectively. The position of the most leaky path in the where the total current is given by integration of (36) in the
channel cross section in plane Z is given by (refer to Fig. 2) cross section excluding the oxide
φ(y, z)
Tch Isth = isth dy dz ∼ ni exp dy dz. (38)
ẑm = Hch + t̃oxt + i + t̃oxs . (32) Vth
2
Due to the closed-form solution for the potential φ, the total
Using the conformal mapping function (27), we obtain in current can easily be obtained by computing (36) at discrete
complex plane W points in the cross section and herewith approximating (38).
Hence, by (37), the slope can be calculated without numerical
wm = um + ivm (33) iteration.
In order to arrive at a closed-form solution for (38), the poten-
where um = 0 and, considering (23) and (24) tial solution within the cross section including the oxide can be
approximated by the following function, which is parabolically
π Hch + t̃oxt shaped with respect to y and z:
vm = cosh · . (34)
a Tch + 2t̃oxs 2 2
y z
φ̃(y, z) = Vgs + φm − Vgs · 1 − · 1−
Now, using (11) and (31), we can write a compact expression y0 z0
for the height of the potential barrier at the most leaky path (39)
Fig. 6. Numerical results for potential φ with Vds = 0 V and gate bias below
(Vgs = −0.15 V) and above (Vgs = −0.05 V) threshold. The plot shows the
potential along the trace defined in Fig. 4 at the position of the potential barrier.
Below threshold, the most leaky path is at the end of the trace (bottom middle
of the channel), whereas above threshold, this path moves to the silicon surface
and, in particular, to the corner regions.
VI. CONCLUSION
An analytical approach to calculate the 3-D electrostatic
potential in undoped triple-gate SOI MOS devices was pre-
sented. It is valid below threshold and is based on transforming
a 3-D Laplace equation within a cross section by geometry
scaling into a 2-D Laplace equation. This equation has then
been solved by the conformal mapping technique. By this
approach, the height of the potential barrier was calculated
in a highly structure-oriented way, obtaining closed-form ex-
pressions, including corner effects. This result can be used as
starting point to define a current model for circuit simulation
purposes.
With this result, the degradation of the subthreshold slope by
geometry scaling can be calculated very efficiently. We defined
a simple threshold voltage model which is able to predict
the influence of channel length, width, and height, including
the DIBL effect. These results are in good agreement with
numerical device simulation results and can therefore be useful
for predictive device scaling investigations.
To our knowledge, with our model, for the first time, a
fully analytical approach is presented, which does not require
an infinite series formalism to expresses the bias-dependent
influence of 3-D effects on the barrier height in FinFETs in a
closed form. However, it should be noted that our solution does
not include mobile charge and therefore does not cover effects
such as volume inversion or quantization effects.
ACKNOWLEDGMENT
The authors would like to thank B. Iñiguez, Universitat
Fig. 7. (a) DIBL effect versus channel length L. The plot shows threshold Rovira i Virgili, Tarragona, Spain, and T. A. Fjeldly, Univer-
voltage shift dVT between Vds = 0.05 V and Vds = 1 V for two different sity Graduate Center, Kjeller, Norway, for the many useful
channel heights. (Line) Analytical model. (Symbols) Sentaurus. (b) Threshold
voltage VT of a FinFET with a channel length of 60 nm versus channel
discussions.
thickness Tch for various channel heights Hch ’s. For a height of 65 nm, (thick
line) the analytical model is compared to (symbols) measurements which were
taken from [2].
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[8] A. Kloes and A. Kostka, “A new analytical method of solving 2D Michaela Weidemann (M’06) received the Diploma degree from the Univer-
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threshold modeling,” Solid State Electron., vol. 39, no. 12, pp. 1761–1775, the M.S. degree in electrical engineering from the Universitat Rovira i Virgili,
Dec. 1996. Tarragona, Spain, in 2007, where she is currently working toward the Ph.D.
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[13] Q. Chen, B. Agrawal, and J. D. Meindl, “A comprehensive analytical He is with LTi Drives GmbH as Engineer R&D.
During his study, he was with the Device Model-
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Giessen–Friedberg, in various projects on numerical
device simulations.
Alexander Kloes (M’95) received the Diploma and
Ph.D. degrees in electrical engineering from the
Solid-State Electronics Laboratory, Darmstadt Uni-
versity of Technology, Darmstadt, Germany, in 1993
and 1996, respectively.
He was an R&D Project Manager with Braun Bryan T. Bosworth is currently working toward the
GmbH, Kronberg, Germany, from 1997 to 2002, B.S. degree in electrical engineering in the Depart-
where he focused on IR sensor technology in sili- ment of Electrical Engineering, Princeton University,
con. Since 2002, he has been a Professor with the Princeton, NJ.
University of Applied Sciences Giessen–Friedberg, He was an Intern Software Engineer with ARINC,
Giessen, Germany. His research interests include Inc., an Intern Electrical Engineer with Northrop
semiconductor device modeling, specifically for nanoscale MOS devices. Grumman Electronic Systems, and as a RISE
Prof. Kloes is an Associate Member of COMON (Compact Modelling Net- Intern with the University of Applied Sciences
work, European Union’s 7th Research Framework Programme), contributing to Giessen–Friedberg, Giessen, Germany. His general
the research group at the Universitat Rovira i Virgili, Tarragona, Spain. research interest includes semiconductor devices.