Project:

Designing an 8-Bit Arithmetic Logic

Unit Using ModelSim
Project Title:
Designing an 8-Bit Arithmetic Logic Unit Using
ModelSim

Group members:
 ARSLAN JAVAID
CMS # 27189
Project title:
Designing an 8-Bit Arithmetic Logic Unit Using ModelSim

ABSTRACT:
By increasing the demand of enhancing the ability of processors to handle the more complex and
challenging processors has resulted in the integration of a number of processor cores into one chip. Still
the load of on the processor is not less in generic system. An Arithmetic Logic Unit (ALU) is the heart of
all microprocessors. It is a combinational logic unit that performs its logical or arithmetic operations.
ALU is getting smaller and more complex nowadays to enable the development of a more powerful but
smaller computer.

In this project an 8-bit Arithmetic Logic Unit (ALU) is designed and implemented in ModelSim SE-64
10.5 using Verilog Programming language. It includes writing, compiling and simulating Verilog code in
ModelSim 10.5 on a Windows 8.1 platform.

Introduction:
Arithmetic Logical Unit (ALU)

It is a critical component of the microprocessor and core component of central processing unit. ALU
comprises the combinational logic that implements logic operations such as AND and OR, and arithmetic
operations such as Addition, Subtraction, and Multiplication.

In digital electronics, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and bit-
wise logical operations on integer binary numbers. It is a fundamental building block of the central
processing unit (CPU) found in many computers and microcontrollers.

Inputs to an ALU are the data to be operated on (called operands) and a code indicating the operation to
be performed, while the ALU’s output is the result of the performed operation. In many designs, the ALU
also exchanges additional information with a status register, which relates to the result of current or
previous operations. The pin diagram of the ALU is shown in Fig. 1 and its description in Table I.
 Fig 1 ALU Pin Diagram

Pin Pin Description

A 8-bit I/P signal A

B 8-bit I/P signal B

SEL 4-bit Selection Signal

S 8-bit O/P signal

O Output Carry signal

Table I: Pin Description of ALU

Relate Work
Most ALU can perform the following operations:

 Bitwise logic operations (NOT, AND, OR, XOR)

 Integer arithmetic operations (addition, subtraction, and sometimes multiplication

And division, though this is more expensive)

 Bit-shifting operations (shifting or rotating a word by a specified number of bits

to the left or right, with or without sign extension). Shifts can be seen as

Multiplications and divisions by a power of two.

Most of these operations have been accommodated in this project as well.

Designing 8 bit ALU

For design of ALU we have two operands. I.e. Primary operand A and secondary operand B. All
operations are performed between these two operands. From this operation whether generate carry,
zero or 1.

In 8 bit ALU there are two 8 bit operands A (7:0) and B (7:0) and result is stored in S (7:0).

OPCODE for ALU

Several operations are done in ALU so we defined opcode for each instruction.

The ALU function table with opcodes, instructions and operations performed are listed in Table II.
Table II: ALU FUNCTIONS
Opcode Instruction Operation
ARITHMETIC
UNIT
0000 A+B Addition
0001 A-B Subtraction
0010 A*B Multiplication
0011 A/B Division
0100 A<<1 Logical shift left
0101 A>>1 Logical shift right
0110 {A[6:0],A[7]} Rotate left
0111 {A[0],A[7:1]} Rotate right
LOGIC UNIT
1000 A&B Logical and
1001 A|B Logical or
1010 A^B Logical xor
1011 ~(A | B) Logical nor
1100 ~(A & B) Logical nand
1101 ~(A ^ B) Logical xnor
1110 (A>B)?8'd1:8'd0 Greater comparison
1111 (A==B)?8'd1:8'd0 Equal comparison
8-bit ALU Implementation in Verilog on ModelSim
1. First, install ModelSim on a Windows PC.
2. Double click ModelSim SE-64 10.5 icon from the desktop.
3. Dialogue box named “important information “will appear .Close this dialogue box as shown in
figure below:
4. Go to file option then change directory option and set working directory as shown in figure:
 5. Go to file ..new..source…Verilog as shown in figure below:

6. Write the Verilog code of ALU as given below:

// Verilog project: Verilog code for ALU

module alu(

input [7:0] A,B, // ALU 8-bit Inputs

input [3:0] ALU_Sel,// ALU Selection

output [7:0] ALU_Out, // ALU 8-bit Output

output CarryOut // Carry Out Flag

);

reg [7:0] ALU_Result;

wire [8:0] tmp;

assign ALU_Out = ALU_Result; // ALU out

assign tmp = {1'b0,A} + {1'b0,B};

assign CarryOut = tmp[8]; // Carryout flag

always @(*)

begin

case(ALU_Sel)

4'b0000: // Addition

ALU_Result = A + B ;

4'b0001: // Subtraction

ALU_Result = A - B ;

4'b0010: // Multiplication

ALU_Result = A * B;

4'b0011: // Division

ALU_Result = A/B;

4'b0100: // Logical shift left

ALU_Result = A<<1;

4'b0101: // Logical shift right

ALU_Result = A>>1;

4'b0110: // Rotate left

ALU_Result = {A[6:0],A[7]};

4'b0111: // Rotate right

ALU_Result = {A[0],A[7:1]};

4'b1000: // Logical and

ALU_Result = A & B;

4'b1001: // Logical or
 ALU_Result = A | B;

4'b1010: // Logical xor

ALU_Result = A ^ B;

4'b1011: // Logical nor

ALU_Result = ~(A | B);

4'b1100: // Logical nand

ALU_Result = ~(A & B);

4'b1101: // Logical xnor

ALU_Result = ~(A ^ B);

4'b1110: // Greater comparison

ALU_Result = (A>B)?8'd1:8'd0 ;

4'b1111: // Equal comparison

ALU_Result = (A==B)?8'd1:8'd0 ;

default: ALU_Result = A + B ;

endcase

end

endmodule

7. Save the code with name alu.v

8. Again goto file …new…source…Verilog
9. Write the code for test bench of ALU as given below:
// Verilog project: test bench for ALU

// `timescale 1ns / 1ps

module tb_alu;

//Inputs

reg[7:0] A,B;

reg[3:0] ALU_Sel;

//Outputs

wire[7:0] ALU_Out;

wire CarryOut;

// Verilog code for ALU

integer i;

alu test_unit(

A,B, // ALU 8-bit Inputs

ALU_Sel,// ALU Selection

ALU_Out, // ALU 8-bit Output

CarryOut // Carry Out Flag

);

initial

begin

// hold reset state for 100 ns.

A = 8'h0A;
// B = 4'h02;

B = 8'h02;

// ALU_Sel = 4'h0;

ALU_Sel = 4'b0000;

#100

for (i=0;i<=15;i=i+1)

begin

// ALU_Sel = ALU_Sel + 8'h01;

//#10

ALU_Sel = ALU_Sel + 1'b1;

#10;

end

A = 8'hF6;

B = 8'h0A;

end

endmodule

10. Save the file with name alu_tb.v

11. Compile both files separately

12. Message will appear work folder doesn’t exist. Do you want to create it click ok

13. The final workspace window is shown in Fig. below:

SIMULATION
1. Right click on tb_alu and click simulate as shown in figure:

2. Another window of simulation will appear. Click “Add wave” as shown in figure to observe the
waveforms results.
3. Run simulation from run button as shown in figure

4. Results of the waveforms of outputs of ALU based on input select lines is shown below:

Timing diagram
Conclusion
This project helps to understand how to implement 8-bit ALU in ModelSim using Verilog. After writing
ALU code, test bench was written to verify the functionality of ALU. On running simulation it was verified
that ALU is successfully built.