MID SEM SOLUTION-2018

Microprocessors & Microcontrollers EC3003]

Q.1. [1X5]

1.a) (i) [A] = F0H. (ii). MOV A, M and LDA 6100H or LXI H,6100H
MOV A, M

1.b)
Interrupt Vector Location
TRAP 0024H
RST5.5 002CH
RST6.5 0034H
RST7.5 003CH

1.c) [SP]=209EH, [DE]=47CCH.

1.d) 2764 (8Kx8)- 13 Address lines

62128(16Kx8)- 14 Address lines

1.e) For executing LDAX B, 7 T.states required which consumes 3.5µSec.

Hence 1.T. state consumes (3.5/7) µSec=0.5 µSec and clock frequency is 2MHz.

2. [1+2]

a) Program Counter: is a 16-bit register and is used to sequence the execution of the instructions.
PC always points to the memory location from which the next byte is to be fetched. When a byte is
being fetched, PC is incremented by one to point to the next memory location.

1
b)
FLAG REGISTER: 8085 MP
D7 D6 D5 D4 D3 D2 D1 D0
Z S - AC - P - CY
Example to set Zero flag:
SUB A, CMP A or MVI A,0C8H;
CPI 0C8H; Result discarded, [A]=0C8H; [ZF]=1 [1+1]
Q.3.
a) INA Machine cycle [3]

Signals used: ALE, IO/M, RD, WR, AD0-AD7, A8-A15, S1, S0

b) Operation performed by the Instructions: [2]

(i)DAA: Decimal-Adjust Accumulator – This instruction works on the content of the

accumulator and convert the result after ADD, ADC, ADI like instructions to binary coded
decimal value as follows:
1. If the value of the low-order four bits i.e., lower nibble (D3 - D0) of the result in the
accumulator is greater than 9 or if AC flag is set, the instruction adds 06.
2. If the value of the high-order four bits i.e., higher nibble (D7 - D4) in the accumulator is
greater than 9 or if C flag is set, the instruction adds 60.

Example. Addition of 12BCD and 39BCD should give 51BCD. Since 8085 only adds in
hexadecimal, we get
12 = 0 0 0 1 0 0 1 0
39 = 0 0 1 1 1 0 0 1
The result in accumulator is

2
 4B = 0 1 0 0 1 0 1 1
As lower nibble is greater than 9, we add 06.
4B = 0 1 0 0 1 0 1 1
06 = 0 0 0 0 0 1 1 0
And, we get the desired result in BCD form
51 = 0 1 0 1 0 0 0 1
ADDRESSING MODE: Implicit

(ii).CMP M: This instruction compares the content of memory location pointed by HL pair
with the content of Accumulator. The result after comparison is discarded only flags get
affected.

[Accumulator] [Accumulator] -[[HL]]

ADDRESSING MODE: Register Indirect

Q.4.
a) Necessity of selective masking: [2+1]
EI Instruction enables all Interrupts (except Trap, which is non-maskable and non-
disable and always enabled). Similarly, all Interrupts (except Trap) are disabled on Reset
or any Interrupt recognized, or through DI Instruction.
Hence, when an Interrupt (say on RST7.5) is recognized and the Interrupt service
routine for RST7.5 is on, if the Interrupt system is enabled with an EI Instruction, then a low
priority interrupt (like RST5.5) may force the Microprocessor to Interrupt when the Interrupt
Service Routine for a higher priority interrupt RST 7.5 is ON. However, if the Interrupt system
is not enabled at the beginning of the service routine and only enabled at the end of the RST7.5
service routine, then no other Interrupt can interrupt the Microprocessor. This may not be
desirable at times. It may be necessary that when RST7.5 interrupt service routine is on, then
Microprocessor may want to respond to only interrupt on RST6.5 pin but not on RST5.5. In
such a case, selective masking of interrupts is required with the help of SIM instruction which
is to be executed before using an EI Instruction.


After execution of MVI A,0EH;
SIM;
Accumulator reads as follows:
SOD SDE X R7.5 MSE M7.5 M6.5 M5.5
0 0 0 0 1 1 1 0

Result:
Unmask interrupt RST 5.5, mask RST 6.5 and RST 7.5.

b) [2]

3
 MVI D,48H ; Move immediate 48H Register D to.
MOV A, D ;48H is moved from Register D to Accumulator.
CMA ; Complement Accumulator.
ANI F0H ;Mask lower four bits of Accumulator.
STAX B ; Store Accumulator at memory pointed by BC.
HLT ;BCBCBBC
Halt

5 (a). Memory Interfacing [2+1]

4
(b). Delay Calculation:
Total exact time delay= 12017T.states*0.5 s ; [2]

= 6008.5 s  6.0ms
[N= 01F4H = 500D]

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