Abstract

This thesis work is devoted for the design of high speed 32 bit vedic multiplier. For arithmetic
multiplication various Vedic multiplication techniques like Urdhva tiryakbhyam, Nikhilam and
Anurupye has been thoroughly discussed. Multiplication unit is the main part of any arithmetic
logic unit for DSP and other digital applications It has been found that Urdhva tiryakbhyam
Sutra is efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of
numbers, either small or large. The 32 bit vedic Multiplier is design with ripple carry adder
which reduce the delay and reduce the complexity of the design. The design is implemented in
VHDL and synthesis and simulation is done with the help of Xylinx ISE tool. In this thesis the
multiplier is design with lower bit to higher bit. Firstly the 2 bit vedic multiplier should be
design. In ordered to design 4 bit vedic multiplier, four 2 bit vedic multiplier should be needed.
The 8 bit vedic multiplier is implemented with the help of 4 bit vedic multipliers. Similarly the
32 bit vedic multiplier is designed with the help of 16 bit vedic multipliers. The desired results is
achieved with the design proposed multipler. The 32 bit vedic multiplier using multiplexer adder
reduce the delay 4.7% from conventional multiplier.