VLSI MAJOR PROJECT LIST

PROJECT ID TITLE
EGT_BVLSI_001 Fault tolerant parallel ffts using error correction codes and parseval checks
EGT_BVLSI_002 Dlau a scalable deep learning accelerator unit on fpga
EGT_BVLSI_003 Design of defect and fault-tolerant nonvolatile spintronic flip-flops
EGT_BVLSI_004 Overloaded cdma crossbar for network-on-chip
EGT_BVLSI_005 Delay analysis for current mode threshold logic gate designs
EGT_BVLSI_006 Energy-efficient VLSI realization of binary64 division with redundant number
systems
EGT_BVLSI_007 Clock-gating of streaming applications for energy efficient implementations on
fpgas
EGT_BVLSI_008 Design of low-power high-performance 2–4 and 4–16 mixed-logic line decoders
EGT_BVLSI_009 Dual-quality 4:2 compressors for utilizing in dynamic accuracy configurable
multipliers
EGT_BVLSI_010 Low-power parallel chien search architecture using a two-step approach
EGT_BVLSI_011 A power efficient mixed signal smart ADC design with adaptive resolution and
variable sampling rate for low power applications
EGT_BVLSI_012 Scalable approach for power droop reduction during scan-based logic bist
EGT_BVLSI_013 Roba multiplier a rounding-based approximate multiplier for high-speed yet energy-
efficient digital signal processing
EGT_BVLSI_014 Design of efficient bcd adders in quantum dot celluar automata
EGT_BVLSI_015 Design of power and area efficient approximate multipliers
EGT_BVLSI_016 Chip Design for Turbo Encoder Module for In-Vehicle System
EGT_BVLSI_017 A low-power incremental delta-sigma adc for cmos image sensors
EGT_BVLSI_018 MAES: modified advanced encryption standard for resource constraint environment
EGT_BVLSI_019 Probability-driven multibit flip-flop integration with clock gating
EGT_BVLSI_020 A bit plane decomposition matrix based vlsi integer transform architecture for
HEVC
EGT_BVLSI_021 A Structured Visual Approach to GALS Modeling and verification of
communication circuits
EGT_BVLSI_022 Concept, Design, and Implementation of Reconfigurable CORDIC
EGT_BVLSI_023 Exploiting Addition Schemes for the Improvement of Optimized Radix-2 and
Radix-4 FFT Butterflies
EGT_BVLSI_024 Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height
Reduction
EGT_BVLSI_025 Sign-Magnitude Encoding for Efficient BVLSI Realization of Decimal
Multiplication
EGT_BVLSI_026 High Performance Ternary Adder using CNTFET
EGT_BVLSI_027 Fast Energy Efficient Radix-16 Sequential Multiplier
EGT_BVLSI_028 A Generalized Algorithm and Reconfigurable Architecture for Efficient and
Scalable Orthogonal Approximation of DCT
EGT_BVLSI_029 A Method to Design Single Error Correction Codes With Fast Decoding for a
Subset of Critical Bits
EGT_BVLSI_030 Dual Use of Power Lines for Design-for-Testability—A CMOS Receiver Design
EGT_BVLSI_031 Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation

CONTACT US: +91-9618366311

EMAIL ID:EDUGENETECHNOLOGIES@GMAIL.COM
 VLSI MAJOR PROJECT LIST
EGT_BVLSI_032 FPGA Implementation of LMS-based FIR Adaptive Filter for Real Time Digital
Signal Processing Applications
EGT_BVLSI_033 Low-Power ASK Detector for Low Modulation Indexes and Rail-to-Rail Input
Range
EGT_BVLSI_034 Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through
Scheme
EGT_BVLSI_035 One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked
Elements
EGT_BVLSI_036 Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy
Block
EGT_BVLSI_037 AN Efficient High-Speed and Less Energy Consumption Carry Skip Adder Using
Skip Logic
EGT_BVLSI_038 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable
Applications
EGT_BVLSI_039 Design And Analysis Of 32x32 Bit Alu Using High-Speed Vedic-Wallace
Multiplier Based On Vedic Mathematics
EGT_BVLSI_040 Design and Implementation of Enhanced Leakage Power Reduction Technique in
CMOS BVLSI Circuits
EGT_BVLSI_041 Implementation of high speed low power combinational and sequential circuits
using reversible logic gates
EGT_BVLSI_042 Aging-aware reliable multiplier design with adaptive hold logic
EGT_BVLSI_043 An efficient and double-adjcent error correcting parallel decoder for the (24,12)
extended golay code
EGT_BVLSI_044 Low-power parallel chien search architechure using a two-step approach
EGT_BVLSI_047 High-throughput finite field multipliers using redundant basis for fpga and asic
implementation
EGT_BVLSI_049 Pre-encoded multipliers based on non redundent radix-4 signed-digit encoding
EGT_BVLSI_050 A high throughput list decoder architecture for polar codes
EGT_BVLSI_051 Area- delay power efficient fixed point lms adaptive filter with low adaptation-
delay
EGT_BVLSI_052 Fully reused vlsi architecture of fmo manchester encoding using sols technique for
dsrc application
EGT_BVLSI_053 Flexbile dsp accelerator archittecture exploiting carry save arithmetic
EGT_BVLSI_054 Berger check and fault tolerant reversible arithmetic component design
EGT_BVLSI_055 Fault tolerant parallel filters based on error correction codes
EGT_BVLSI_056 Low- cost high performance vlsi architecture for montogomery modular
multiplication
EGT_BVLSI_058 On efficient retiming of fixed point circuits
EGT_BVLSI_059 A low power single phase clock distribution using vlsi technology
EGT_BVLSI_060 Digital multiplierless realization of two-coupled biological hindmarsh–rose neuron
model
EGT_BVLSI_061 A modified partial product generator for redundant binary multipliers
EGT_BVLSI_062 Scan test bandwidth management for ultra large-scale system-on-chip architectures
EGT_BVLSI_063 Low power pulse triggered flip flop design based on a signal feed through scheme

CONTACT US: +91-9618366311

EMAIL ID:EDUGENETECHNOLOGIES@GMAIL.COM
 VLSI MAJOR PROJECT LIST
EGT_BVLSI_064 Vlsi design for convolutive blind source separation
EGT_BVLSI_065 Low complexity tree architecture for finding first two minima
EGT_BVLSI_066 A high-performance filter architecture for fixed and reconfigurable applications
EGT_BVLSI_067 Low power programmable prpg with test compression capabilities
EGT_BVLSI_068 High speed hybrid double multiplication architectures using new serial out bit level
mastrovito multiplier
EGT_BVLSI_070 Reliable low power multiplier design using fixed width replica redundancy block
EGT_BVLSI_071 High-performance pipelined architecture of elliptic curve scalar multiplication over
gf(2m)
EGT_BVLSI_073 Fault tolerant parallel filters based on error correction codes
EGT_BVLSI_074 Hybrid lookup tables on multiplexer fpga logic architectures
EGT_BVLSI_075 Data encoding technique for reducing energy consumption in network on chip
EGT_BVLSI_076 Low delay single symbol error correcion codes based on rs code
EGT_BVLSI_078 Partially parallel encoder architecture for long
EGT_BVLSI_079 Recursive approach to the design of a parallel self timed adder
EGT_BVLSI_083 Pns-fcr: flexible charge recycling dynamic circuit technique for low-power
microprocessors
EGT_BVLSI_085 Full-swing local bitline sram architecture based on the 22-nm finfet technologyfor
low-voltage operation

CONTACT US: +91-9618366311

EMAIL ID:EDUGENETECHNOLOGIES@GMAIL.COM