2608
11, NOVEMBER 2013
Low-Power On-Chip Charge-Recycling DC-DC
Conversion Circuit and System
Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Member, IEEE, and
Kazutami Arimoto, Fellow, IEEE
Abstract—A charge-recycling circuit and system that reuses the
energy between two or more stacked CPUs is proposed in order
to double the life of a battery. In this architecture, CPUs are di-
vided into upper and lower load groups, and electrical charges are
shared among the stacked CPUs and a tank capacitor. Charges are
temporarily stored in the tank capacitor and are then reused. To
control divided loads, a high-speed and energy-efficient regulator
is needed. Internal circuit voltage variation between the upper and
lower modules is determined by seven low-drop-out (LDO) regu-
lators, a voltage-boosting capacitor circuit, and the tank capacitor.
As a result, stable voltage can be supplied to each CPU, even if the
upper and lower loads are different or a battery is being used. The
LDOs improve the margin of collection in the tank capacitor or
task schedule operation, and power efficiency is raised even fur-
ther. The circuit can be implemented on silicon without a large ex-
ternal control circuit and inductor such as a switching regulator.
This circuit was applied to an in-vehicle lock-step system because
the upper and lower loads and tasks are the same. Additionally, by
using the proposed task scheduling to maximize efficiency, this cir-
cuit can be applied not only to lock-step systems but also to general
systems. Test chips were fabricated using 90-nm standard CMOS
technology. Although the maximum power efficiency of a conven-
tional circuit with a simple LDO is 44.4%, efficiency of the pro-
posed charge-recycling circuit turned out to be as high as 87.1%
with the test chips.
Index Terms—Charge-recycling, CPU, dc–dc conversion, in-ve-
hicle LSI, lock-step system, low drop out (LDO), task scheduling.
I. INTRODUCTION
A S we enter the smart grid age, high energy efficiency has
attracted much attention. Likewise, for low power con-
sumption by an electronic device, semiconductor technology
is indispensable. To improve the power efficiency of such de-
vices, many researches, i.e., low-voltage MOS, power-gating,
and so on, have continued to make progress. Also, reduction of
CPU voltage has become possible by lower power consumption
and high-speed operation. On the other hand, battery voltage is
constant due to system restrictions. A linear regulator which is
Manuscript received February 03, 2013; revised May 16, 2013; accepted July
05, 2013. Date of publication August 15, 2013; date of current version October
19, 2013. This paper was approved by Guest Editors Hong June Park and Chang-
Hyun Kim.
K. Ueda, F. Morishita, and S. Okura are with Renesas Electronics Corpora-
tion, Hyogo 664-0005, Japan (e-mail: kazuhiro.ueda.nx@renesas.com).
L. Okamura and T. Yoshihara are with Waseda University, Fukuoka 814-
0180, Japan.
K. Arimoto is with Okayama Prefectural University, Okayama 719-1197,
Japan.
Digital Object Identifier 10.1109/JSSC.2013.2274829
0018-9200 © 2013 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO.
commonly called low drop out (LDO) has widely been used in
system miniaturization. If voltage scaling of LSI, the voltage
drop by LDO will also be substantial. Since the LDO drop is
let out as thermal energy, electric power efficiency is low. As
heat generation increases, problems with the package and board
mounting arise. This study seeks to effectively use the voltage
drop by LDO for high-power efficiency [1]. Just as remarkable
as power generated from sunlight or wind, energy recycling in
an electronic device is expected to increase energy efficiency.
The idea for this system comes from, in part, the charge-recy-
cling techniques applied in data buses [2] and the highly capac-
itive lines of memories [3], [4]. In a multicore LSI, high-speed
and low-power consumption become compatible. For an in-ve-
hicle LSI, the fault-tolerant machine of the lock-step system car-
ries out multiplexing-transmission for each task [5]. The lock-
step system ensures safety by executing the same task between
two or more CPUs and matches the comparison of results.
In this paper, a low-power consumption system which reuses
energies among lock-step CPUs is proposed to realize high en-
ergy efficiency. In this system, CPUs are divided into upper and
lower load groups, and electrical charges are shared among the
CPUs and a tank capacitor. The circuit consists of seven LDOs,
a voltage-boosting switched capacitor circuit, and a tank ca-
pacitor. A super capacitor is used for the tank capacitor. For
example, a poly acenic semiconductor (PAS) capacitor is suit-
able for input or output voltage range and capacity value. If the
power consumption of the loads is sufficiently low, a MOS ca-
pacitor or a MIM (Metal Insulator Metal) capacitor can be used
as the on-chip capacitor of the tank. The tank temporarily stores
the electrical charge for reuse and promotes charge recycling.
The LDOs control the super capacitor and the flows of the elec-
trical charge of the loads, so exact charge and discharge oper-
ations are carried out. High stabilization of mid-voltage poten-
tial of the charge-recycling circuit, which is divided into upper
and lower loads, is also provided. A voltage-boosting capacitor
circuit maintains mid-potential stability. The charge-recycling
circuit’s regulator operates with AMP, which consists of a two-
step level shifter and a high-speed comparator. High speed and
low-power consumption is possible by the proposed coupling
interface system. Currently, the semiconductor evolves from
hardware directivity to software loading. Multicore technology
to prolong battery life has been proposed [6]. Task scheduling
techniques for multicore circuits in order to increase power ef-
ficiency is further applied to the charge-recycling circuit. Since
the ratio of the upper and lower CPU loads can be maintained by
assigning two CPUs of a lock-step system, the task scheduling
is suitable for the charge-recycling system. Even in applications
UEDA et al.: LOW-POWER ON-CHIP CHARGE-RECYCLING DC–DC CONVERSION CIRCUIT AND SYSTEM 2609

Fig. 2. Power supply system by a linear regulator.

Fig. 1. Power supply system by a switching regulator.

when the battery voltage 2.7 V and the in-

other than a lock-step system, the upper and lower CPU loads’ ternal circuit voltage 1.2 V. These can be expressed as
ratio remains stable with high efficiency by the proposed task
scheduling technique, and a small system area are realized.
The contents of this paper are as follows. In Section II, ex-
traction of the conventional LSI power system and its problems
are described. In Section III, the lock-step system LSI with high
energy efficiency using a charge-recycling circuit is proposed. (1)
Furthermore, the task-scheduling technique for maximizing the
energy efficiency is applied for the circuit. In Section IV, the
high-speed and power-efficient interface between CPUs in the
charge-recycling circuit is proposed. In addition, the high-speed
comparator-type LDO applied for the recycling circuit is ex-
(2)
plained. Measurement results and conclusions are described in
Sections V and VI, respectively. Here, each equation variables are defined as follows.
energy efficiency of a linear regulator system;
II. CONVENTIONAL POWER SYSTEM
energy loss of a linear regulator system;
A. General Power System energy consumed by loads from t0 to t1;
Generally, the voltage in LSI is supplied through a power workload which a battery carries out from t0
supply circuit from a power source such as a battery connected to t1;
outside of LSI on a board. Since the capacity of batteries, such as
a portable device, is limited, high efficiency of the power supply output voltage and current of a battery;
circuit is required. A fan to mitigate heat is often used for LSI,
and the power supply circuit which is small in size, lightweight, B. Stack-Type Power Circuit
and with low heat generation is also required. Here, we proposed a stack-type power circuit which requires
Due to their high power efficiency and low heat generation, small area and has high efficiency (Fig. 3) [7]. The stack circuit
switching regulators are widely used. With the switching regu- first sets the mid-voltage potential by a linear
lator circuit, a proper power supply voltage is provided to LSI regulator from the battery voltage . The following defini-
by turning the switch of a current path on and off, which makes tions are given.
necessary charges to flow to LSI loads from the battery and 1) Upper module’s power domain:
stabilizes the supply voltage (Fig. 1). Their power efficiency
is approximately 85%–90%. However, an inductor and a con-
trol circuit like a dc–dc convertor device must be set as external
2) Lower module’s power domain:
devices. As a result, this switching regulator approach has its
problem of an increased system area.
To avoid having the external devices, the linear regulator can
be used (Fig. 2). For the linear regulator, an appropriate power The internal circuit is divided into two or more smaller
supply voltage is provided to internal loads by adjusting the partial circuits, and each partial circuit belongs to either the
value of a variable resistor which is set between internal loads upper system or the lower one. Then, a power supply voltage
and external voltage from the battery. The variable resistor con- of is given to each partial circuit. Thus, electric power
sists of AMP and MOS. However, voltage potential difference efficiency is improved by connecting the upper and lower
causes large heat generation and low power effi- circuit and reusing the current to flow to both the upper and
ciency at a maximum of approximately 44.4%. It is equal to lower loads. Each module is connected to the upper or lower
2610
Fig. 3. Simple stack-type power circuit.
Fig. 4. Proposed stack-type charge-recycling power circuit.
sides by switches. However, high efficiency is achieved only
if the upper and lower loads are equal. Also, upper and lower
system voltages are and depend on a battery. When
the battery voltage drops during its operation, the power supply
voltage of the upper and lower system also drops, and operation
margin decreases.
III. CHARGE-RECYCLING POWER CIRCUIT
A. Charge-Recycling Architecture
The proposed charge-recycling power circuit is shown in
Fig. 4. The circuit can improve efficiency for a system by tem-
porarily storing the electrical charge in the tank capacitor, even
when the upper and the lower loads aren’t equal. This circuit
consists of two mid-voltage potentials and and a
tank capacitor. The tank capacitor temporarily stores surplus
electric power and enables reuses of the electrical charge.
Characteristics of the simple stack-type circuit at the time of
power potential drop when using a battery, and the proposed
charge-recycling circuit, are explained in Fig. 5. Since the
simple stack-type circuit has only one mid-voltage potential
, there is no margin in the voltage drop of the battery. The
battery and a reference voltage which determines the conven-
tional fall at the same time. A regulator which is connected
directly to a battery has to be the simple circuit. With the
proposed circuit, two mid-potentials and are used as
the ground side potential of the upper part of the power supply
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 11, NOVEMBER 2013
Fig. 5. Prolonging the battery life with two mid-voltage potentials of proposed
circuit.
Fig. 6. Detail of proposed charge-recycling circuit.
system , and the power supply side potential of
the lower power supply system , respectively. A
battery and a reference voltage which determines also
fall simultaneously. However, it is a premise that the reference
voltage which determines does not fall because it is sup-
plied from another regulator. High stability of the mid-voltage
potential realizes a longer battery life because it can operate
properly even when the voltage level generated by the battery
somewhat deteriorates after long usage. This circuit can be
connected directly to a battery. One or more modules which
consist of CPUs and memories are connected to the upper and
lower parts of a power supply system. The current used by
the upper module is sent to the lower module, and the lower
module reuses it. Therefore, high energy efficiency is achieved.
B. Principle of the Charge-Recycling Circuit
Details of charge-recycling circuit are shown in Fig. 6. Since
a conventional recycling circuit [8] has a small margin of
mid-voltage potential variation, LDOs, and a voltage-boosting
capacitor circuit are refined. The new circuit consists of seven
LDOs (LDO1-LDO7) and a voltage-boosting capacitor circuit
to control the two mid-potentials and . The circuit is
controlled as follows. The upper and lower modules are con-
nected by LDO1. The lower modules also use the current which
flowed through the upper modules through LDO1. Surplus
charge which flowed from the upper modules are temporarily
stored in the tank capacitor and then reused in the lower mod-
ules. In Case 1, the current consumed by the upper modules
is larger than the current consumed by the lower modules. In
UEDA et al.: LOW-POWER ON-CHIP CHARGE-RECYCLING DC–DC CONVERSION CIRCUIT AND SYSTEM
Fig. 7. Voltage boosting capacitor circuit and the sequence of switches.
Case 2, the lower current is conversely larger. These cases are
explained as follows.
Case 1) Upper modules current lower modules current:
electric charge used by the upper modules is reused
by the lower modules. The electrical charge which is
not consumed by the lower modules is temporarily
stored in the tank capacitor. When the tank is not
full, part of the surplus is charged by the tank (LDO2
turns on). If the tank is full, the electrical charge is
passed to the ground (LDO3 turns on).
Case 2) Upper modules current lower modules current:
the electrical charge used by the upper modules is
reused by the lower modules. When the tank has a
charge, the current from the tank will be used (LDO4
turns on). If the tank is empty, the lower modules
will be directly supplied by the battery (LDO5 turns
on).
At start-up, and when the potential of significantly drops,
is brought up to the setting voltage potential by LDO6.
When the potential of is too high, it is brought back to the
setting potential by LDO7. Since the voltage boosting capacitor
circuit can operate even if battery voltage drops, the system is
stable before standby shift. Also, decoupling capacitors, which
are MOS capacitors, are placed between and and
between and . The voltage-boosting capacitor and the
decoupling capacitors stabilize mid-node and . The
boosting capacitor circuit is used for this recycling circuit and is
shown in Fig. 7. The principles of operation are explained using
the sequence of this circuit and a switch diagram. It is switched
on and off in the order from 1 to 4. By charge conservation,
is raised to , as shown as
(3)
The value shows boost efficiency and potential in-
creases to a maximum high voltage as potential. falls
mainly by the parasitic capacitance of switches. This is con-
trolled to maintain a constant potential of and . All
LDOs are turned off at power-off and are controlled to keep the
potential of and constant. The efficiencies of various
cases of the charge-recycling circuit are shown in Fig. 8. If the
loads and tasks are focused on the upper part [Fig. 8(a)], the
tank will overflow, and efficiency will decrease. On the other
hand, if the loads are focused on the lower part [Fig. 8(b)], effi-
ciency will decrease because the tank is drained and the battery
is directly used. To solve this, we applied a circuit to the system
2611
Fig. 8. Decline in power efficiency of charge-recycling circuit.
Fig. 9. Charge-recycling circuit for lock-step system.
where the upper and lower loads and tasks are the same and bal-
anced. A technique to control the order of the upper and lower
tasks was considered.
C. Lock-Step System and Charge-Recycling Circuit
In the lock-step fault tolerant system, the same task is as-
signed to two or more CPUs, and safety is secured by carrying
out a coincidence comparison of the results with a spare CPU.
The outline of the lock-step made by the proposed recycling cir-
cuit is explained in Fig. 9. The lock-step LSI consists of a master
CPU, a checker CPU, a hardware comparator, an address, data,
and a control signal. In the lock-step operation, both the master
and the checker CPU execute the same code with a time lag.
Both CPUs acquire the same signal from flash, RAM, periph-
erals, and interrupts. The comparison operation is executed and
all output signals of both CPUs are supervised. If any differ-
ence in output signals is detected in the hardware comparator, an
error signal is generated. In the lock-step system, the same task
is consecutively executed by both the master and the checker
CPU. In the lock-step LSI with the charge-recycling circuit, the
master CPU is arranged to the upper side and the checker CPU
is arranged to the lower side. The task order of each CPU and
the relation of the charge level of tank capacitor are shown in
Fig. 10. Since the same task is consecutively executed by the
upper and lower CPUs, the current consumed by the upper CPU
is always reused to the lower CPU. As a result, high efficiency
is possible.
D. Simulation Results
The specifications for the simulation are shown in Table I and
the simulation result is shown in Fig. 11(a). The mid-voltage
2612 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 11, NOVEMBER 2013

(bus-inverting coding [9], gated clock [10], dynamic voltage

and frequency scaling [11]) and leakage power reduction
technologies (variable-threshold CMOS [12], multithreshold
CMOS, and PVT controlling [13]) can be combined with the
proposed charge-recycling circuit to further achieve low-energy
operation.

E. Task-Scheduling Technique
In the multicore LSI of a mobile phone or a server, a task-
scheduling process determines which CPU will take charge of
which task. In the case of many conventional multicore systems,
task scheduling is provided to improve operation speed. How-
Fig. 10. Task flow and tank charge potential of charge-recycling lock-step ever, the proposed task-scheduling technique minimizes power
circuit. consumption. By combining the charge-recycling circuit and
this task-scheduling technique, efficiency can be raised further.
TABLE I Systems other than lock-step, whose upper and lower tasks and
SIMULATION SPECIFICATIONS OF POWER CIRCUIT loads are not the same, are also considered. When all of the tasks
are arranged to be sent to the upper CPUs, the energy efficiency
can be given by

(6)

When all of the tasks are arranged to be sent to the lower,

is

potential and is correctly controlled by % varia-

tions from the ideal setting potential, and the proposed power
circuit worked out correctly. The energy consumptions of the
upper CPU, the lower CPU, the battery and the tank capacitor
in each period of lock-step LSI are shown in Fig. 11(b). is the
power efficiency of this system. and are the energy con-
sumptions by the upper and lower modules, respectively.
is the workload carried out by the battery, and is the en-
ergy stored in the tank. The energy consumed by the upper CPU
is reused by the lower CPU, and power efficiency is 88.9%. The
energy efficiency of the system is considered. The efficiency
of this system from to is calculated by using (4)
and (5), shown at the bottom of the page. and are the
current consumption of a upper and lower modules. When
is replaced with , it turns out that and improve
the total efficiency compared with that of (1) and (2).
Since the charge-recycling circuit is controlled by the amount
of modules currents, which is equal to charges, the proposed
recycling circuit can be applied to a composition where the
clock frequency of each CPU changes or differs from one an-
other. Moreover, active electric power-reduction technologies
(7)
Power efficiency can be as low as approximately
; battery voltage,
; internal CPUs voltage) nearly the same as a
simple LDO system. Charge recycling is not activated, and the
tank capacitor circuit is not used. An example of scheduled
tasks is shown in Fig. 12. Until task #6, a heavy load is assigned
to the upper modules and the tank capacitor is charged. Then,
light task #7 is assigned to the upper modules, and heavy task
#8 is assigned to the lower modules to prevent overflow in the
tank. After task #7 is completed, task #10 can be assigned to
the upper modules. However, since it is more efficient to assign
heavy tasks to the lower modules to prevent tank overflow, task
#10 is assigned to the lower modules.
Simulation of systems other than the lock-step, whose upper
and lower tasks and loads are not the same, was also carried out.
Without task-scheduling technique, overflow in the tank with
a surplus electrical charge and a shortage of tank charge oc-
curs and supply to the lower modules is not sufficient (Fig. 13).

(4)

(5)
UEDA et al.: LOW-POWER ON-CHIP CHARGE-RECYCLING DC–DC CONVERSION CIRCUIT AND SYSTEM 2613

Fig. 11. Simulation result of the charge-recycling lock-step circuit (at 1 uF). (a) Transient response of the internal voltage. (b) Energy consumption and
efficiency.

Fig. 12. Example of task-scheduling flow and tank charge potential.

However, with task scheduling (Fig. 14), since the shortage or 1) Upper modules:
overflow of the tank’s charge does not occur, efficiency is im-
proved. Efficiency of the scheduling system has been improved
by 18.9% over a nonscheduling system. `` '' `` ''

2) Lower modules:
IV. INTERFACE CIRCUIT AND HIGH-SPEED LDO `` '' `` ''

A. Capacitor Coupling Interface
The interface technique between the upper and lower mod-
ules in the charge-recycling circuit is described. The signals of
interface circuits and the definition of potential are as follows.
As mentioned above, since the potential levels of the power
supply node and the ground node differ between the upper mod-
ules and the lower modules, it is necessary to match the signal
potential before the signal interfaces between upper and lower
modules. This chapter proposes a technique which changes the
2614 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 11, NOVEMBER 2013

Fig. 13. Simulation result of charge-recycling circuit efficiency without task scheduling.

Fig. 14. Simulation result of charge-recycling circuit with task scheduling.

Fig. 15. Interface circuit for the charge-recycling circuit and system.

Fig. 16. Simulation result of proposed interface circuit at 100 MHz.

potential of the or when the power supply voltages of
each upper and lower module are equal
. The interface circuit is shown in Fig. 15. Although no and the latency is 1.63 ns. The principle of the interface system
charge-recycling power supply circuit is shown for simplicity is as follows.
in the figure, the actual implementation was the circuit with i) Transmission from the upper to the lower module: by set-
charge-recycling. the upper modules and ting Signal “ ” to High “1,” the anode P of
the lower modules of the charge-recycling circuit correspond is charged to , and the cathode Q is charged to .
to the figure. Since the voltage is matched between the upper After the charging, the chg is set to Low “0,” and the
and lower modules, the capacitor coupling interface works out level conversion of a data is made. The data through D-FF
high speed operating and low power consumption compared to can be correctly received by a lower module.
simple level shift interface. Simulation result of the data trans- ii) Transmission from the lower to the upper module: with
mission from an upper to a lower module is shown to Fig. 16. signal “ , , the anode of is charged to , and
The upper wave shows sent data while the lower wave shows the cathode is charged to . Since the level conversion
the received data, which passed through the level conversion, of a data is made by capacitor coupling, data are received
transmission, and the buffer. All send data is received correctly by an upper module.
UEDA et al.: LOW-POWER ON-CHIP CHARGE-RECYCLING DC–DC CONVERSION CIRCUIT AND SYSTEM
Fig. 17. High-speed LDO circuit for the charge-recycling circuit.
A level shifter is also necessary to connect with the peripheral
circuit, which is a single power supply. When the power supply
of peripheral is , the proposed circuit is used to
connect between upper CPUs and peripheral.
B. High-Speed LDO
The high-speed LDO [13], [14] schematic shown in Fig. 17
is used for the recycling circuit LDO1–LDO7. The LDO op-
erates by two-stage AMP which consists of a level shifter and
a high-speed comparator. The principle of operation is as fol-
lows. In the beginning, the first-stage amp changes the level of
the input signal to the high sensitivity level of the second-stage
AMP. Next, the difference in the input voltage of the first-stage
is immediately transferred by the feed-forward capacitor
and to a second-stage comparator. The two capacitors
function competently. is a kick capacitor, which transmits
the voltage change directly to the second stage AMP which is
a comparator stage. Because of that transient response is im-
proved. is a dummy capacitor, which is used to sup-
press the noise caused by . The value and layout pattern of
is the same as those of . The simulation result of a
transient response waveforms of the output voltage of LDO with
high-speed comparator circuit and with a conventional circuit
are shown in Fig. 18. It is clear from Fig. 18 that the period of
output voltage vibration is smaller in the high-speed LDO com-
pared with conventional LDO. Furthermore, the output voltage
convergence time of the high-speed LDO is decreased by 52%.
Power lines can be operated stably at high speed by using this
LDO.
V. FABRICATION AND MEASURED RESULTS
A test chip of proposed charge-recycling prototype was fab-
ricated using 90-nm standard CMOS technology. In upper and
lower modules, PLLs are placed as the load for testing. Since
the chip is a prototype, it does not have the scheduler for task
control. However, the upper and lower loads balance is change-
able by setting the power down of some PLLs. Although it is
a prototype, the ratio of upper and lower loads can be changed
and efficiency can be evaluated. When the number of active PLL
loads is the same at the upper and lower or the PLL’s active state
and the PLL’s power down state are repeated by turns, the effi-
ciency is a maximum. It is the same as a lock-step system. PAS
2615
Fig. 18. Simulation result of the proposed LDO’s output transient response.
Fig. 19. Microphotograph of test chip. PLLs for the test loads are arranged
upper and lower modules.
TABLE II
TEST CHIP SPECIFICATIONS
capacitors were used for the tank capacitor of the chip. The ex-
periment is carried out by using the external capacitors values
of 1 F, 47 F, 30 mF, and 9 F. The 30-mF and the 9-F are PAS
capacitors. Reference voltage potential, which is 1.2 or 1.5 V
of each LDO, is assumed to be the same as that supplied by
the external chip, and the offset from the ideal voltage of each
LDO is small. The wells of the upper and lower modules are
divided by a triple-well process. The charge-recycling circuit
does not work well in a normal bulk CMOS due to body ef-
fect. Because nMOSs in the upper modules are still connected to
ground, they are heavily body affected. This problem is avoided
in a triple-well process where the nMOSs are constructed in a
p-well within an n-well. These p-wells are then connected to
the virtual ground of the modules; similarly, the pMOS n-wells
are connected to the virtual supply of the modules. When the
LDOs operations are properly arranged, power efficiency can be
measured in the test chip. A microphotograph of the test chip is
shown in Fig. 19. PLL for the test loads, instead of the CPUs,
are arranged in the upper and lower modules. Specifications of
the chip are shown in Table II. The load PLLs’ current state
of the upper and lower sides of the prototype test chip and the
measurement transient waveform of mid-voltage potential
2616
Fig. 20. Measurement result of the proposed charge-recycling circuit’s output
transient response (at 1 F). The load PLLs currents state and mea-
surement mid-voltage node voltage.
TABLE III
ENERGY CONSUMPTION AND EFFICIENCY
and were shown in Fig. 20.The power-down of the upper
and lower PLLs is performed by prior programming for every
5 ms. The variation of the experimental mid-node voltage poten-
tial against the ideal value is 5%. The simulation was 3%. The
error of measurement due to the noise of the evaluation system
is considered. The area of one LDO is 0.032 mm , and the whole
LODs area overhead in our charge-recycling system is smaller
than 5%–6%. The current consumption of each LDO is 1–5 mA
in the test chip. The LDO’s power consumption depends on the
loads, and the power consumption overhead of seven LDOs is
1% or less of the whole charge-recycling system’s consumption,
which is sufficiently small and can be a negligible value. Effi-
ciency is measured including the loss of LDOs. The efficiency
was calculated by measuring the current of PLL of the upper and
lower, and the potential of the VDD and GND. PADs for mea-
suring the PLLs are separated from other PADs. The efficiency
measured in the chip was 87.1% when the upper and lower load
PLLs are the same like a lock-step. The simulation result was
88.9% (Table III). Degradation of efficiency was assumed to be
caused mainly by resistance of the power supply layout pattern
taken from the internal circuit to the battery of external LSI. The
relation between tank capacitor value and efficiency is shown in
Fig. 21. The efficiency is the maximum when upper and lower
loads are same (5:5). Efficiency drops when upper and lower
loads’ ratios are not the same. Because efficiency improves with
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 48, NO. 11, NOVEMBER 2013
Fig. 21. Measurement results of the proposed charge-recycling circuit. The ef-
ficiency is the maximum when upper and lower loads are the same (5:5) and
1 F.
the tank capacitor of 1 F or more, it is recommended to choose
the capacitor considering area and cost.
VI. CONCLUSION AND FUTURE WORK
A charge-recycling circuit and system were proposed. In this
architecture, electrical charges are shared among the stacked
CPUs and the tank capacitor. Internal voltage variation was de-
termined by LDOs, a boosting capacitor circuit, and a tank ca-
pacitor circuit. The LDOs improved the margin of accumula-
tion in the tank and further raised efficiency. As a result, the
stable voltage could be supplied to each CPU, even if upper and
lower loads were different. Additionally, a task-scheduling tech-
nique to improve efficiency was also proposed. The test chip
was fabricated using 90-nm standard CMOS technology. When
applying the system to the lock-step of an in-vehicle LSI, power
efficiency improved to 88.9% (Table III), while a conventional
simple LDO system has a maximum of 44.4% during simula-
tion. Measured power efficiency of the test chip was 87.1%.
Therefore, battery life can be more than doubled by this system.
In addition, internal CPUs’ voltage can be freely set up by ex-
panding the three or four stages of stacks or by setting an internal
voltage division. This does not choose the battery voltage, but
caters to future low-voltage MOS device circuits.
REFERENCES
[1] K. Ueda, S. Okura, F. Morishita, K. Arimoto, L. Okamura, and T.
Yoshihara, “Green semiconductor technology with ultra-low power
on-chip charge-recycling power circuit and system,” in Proc. Asian
Solid-State Circuits Conf., 2012, pp. 105–108.
[2] H. Yamauchi, H. Akamatsu, and T. Fujita, “An asymptotically zero
power charge-recycling bus architecture for battery-operated ultrahigh
data rate ULSI’s,” IEEE J. Solid-State Circuits, vol. 30, no. 4, pp.
423–431, Apr. 1995.
[3] B.-D. Yang and L.-S. Kim, “A low-power ROM using charge recycling
and charge sharing techniques,” IEEE J. Solid-State Circuits, vol. 38,
no. 4, pp. 641–653, Apr. 2003.
[4] K. W. Mai, T. Mori, B. S. Amruter, R. Ho, B. Wilburn, M. A. Horowitz,
I. Fukushi, T. Izawa, and S. Mitarai, “Low-power SRAM design using
half-swing pulse-mode techniques,” IEEE J. Solid-State Circuits, vol.
33, no. 11, pp. 1659–1671, Nov. 1998.
[5] Renesas Electoronics Corp., “The future of the car-electronics with
in-vehicle semiconductor,” May 5, 2012. [Online]. Available: http://
special.nikkeibp.co.jp/ts/article/0i0h/103477/safety.html
[6] S. Tomonori, “A smart-phone battery life is prolonged. Next-genera-
tion multi-core technology,” Nikkei Electron., Jan. 9, 2012.
UEDA et al.: LOW-POWER ON-CHIP CHARGE-RECYCLING DC–DC CONVERSION CIRCUIT AND SYSTEM
[7] S. Rajapandian, S. Member, Z. Xu, K. L. Shepard, and S. Member,
“Implicit DC-DC downconversion through charge-recycling,” IEEE J.
Solid-State Circuits, vol. 40, no. 4, pp. 846–852, Apr. 2005.
[8] L. Okamura, F. Morishita, K. Arimoto, and T. Yoshihara, “High effi-
ciency autonomous controlled cascaded ldos for green battery system,”
in Proc. IEEE 8th Int. Conf. ASIC, 2009, pp. 336–339.
[9] M. R. Stan and W. P. Burleson, “Bus-invert coding for low-power I/O,”
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 3, no. 1, pp.
49–58, Jan. 1995.
[10] M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou,
“Precomputation-based sequential logic optimization for low power,”
IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 2, no. 4, pp.
426–436, Apr. 1994.
[11] M. Nakai, S. Akui, K. Seno, T. Meguro, T. Seki, T. Kondo, A.
Hashiguchi, H. Kawahara, K. Kumano, and M. Shimura, “Dynamic
voltage and frequency management for a low-power embedded mi-
croprocessor,” IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 28–35,
Jan. 2005.
[12] M. Mizuno, K. Furuta, S. Narita, H. Abiko, I. Sakai, and M. Yamashina,
“Elastic-Vt CMOS circuits for multiple on-chip power control,” in 43rd
Solid-State Circuits Conf. Dig. Tech, Papers, Feb. 1996, pp. 300–301,
462.
[13] T. Gyohten, F. Morishita, M. Okamoto, K. Dosaka, and K. Arimoto,
“An On-chip PVT control system for worst-caseless lower voltage SoC
design,” in Proc. Asian Solid-State Circuits Conf., 2005, pp. 313–316.
[14] L. Okamura, F. Morishita, K. Dosaka, K. Arimoto, and T. Yoshihara,
“An automatic source/body level controllable 0.5 V level SOI circuit
technique for mobile and wireless network applications,” in Proc. Int.
Symp. Commun. Inf. Technol., 2006, vol. 200, pp. 771–774.
Kazuhiro Ueda received the B.S. and M.S. degrees
in information engineering from Hiroshima City
University, Hiroshima, Japan, in 1998 and 2000,
respectively.
He joined the ULSI Development Center, Mit-
subishi Electric Corporation, Hyogo, Japan, in 2000.
Since then, he has been engaged in the development
of process integration for system LSI. He transferred
to Renesas Technology Corporation and Renesas
Electronics, Hyogo, Japan, in 2003 and in 2010,
respectively, where he has been engaged in the
design and development of CMOS image sensor and interface IPs for system
LSI. Currently, his research interests include low-voltage design circuits and
analog-to-digital conversion.
Fukashi Morishita was born in Kyoto, Japan, in
1969. He received the B.S. degree in electrical en-
gineering and M.S. degree in material science from
Keio University, Tokyo, Japan, in 1991 and 1993,
respectively, and the Ph.D. degree from Waseda
University, Fukuoka, Japan, in 2005.
In 1993, he joined the ULSI Development Center,
Mitsubishi Electric Corporation, Hyogo, Japan.
Since then, he has been engaged in the research
and development of MOS DRAMs and embedded
DRAMs. He was transferred to Renesas Technology
Corporation and Renesas Electronics Corporation, Hyogo, Japan, in 2003 and
2010, respectively, where he is currently involved with the development of
CMOS image sensors.
2617
Shunsuke Okura received the B.S., M.S., and Ph.D.
degrees from Osaka University, Osaka, Japan, in
2003, 2005, and 2010, respectively.
From 2007 to 2009, He was with the Rosnes Cor-
poration, Kyoto, Japan, where he has been engaged
in the development of CMOS image sensors. He was
a Research Scientist with Osaka University in 2009.
Since 2010, he has been with Renesas Electronics
Corporation, Hyogo, Japan.
Dr. Okura is a member of the Institute of Image
Information and Television Engineers in Japan.
Leona Okamura receives B.S. degree in electric and
electronic engineering from Kyoto University, Japan
in 2005. He receives M.S. degree in information,
production and systems from Waseda University,
Fukuoka, Japan in 2007.
Tsutomu Yoshihara (M’09) received the B.S. and
M.S. degrees in physics and Ph.D. degree in elec-
tronic engineering from Osaka University, Osaka,
Japan, in 1969, 1971, and 1983, respectively.
In 1971, he joined the ULSI Laboratory of Mit-
subishi Electric Corporation, Hyogo, Japan, where
he has been engaged in the research and develop-
ment of MOS LSI memories. Since April 2003, he
has been a Professor with the Graduate School of In-
formation, Production and Systems, Waseda Univer-
sity, Fukuoka, Japan, where he is currently involved
in research on system LSI.
Dr. Yoshihara is a member of the IEEE Solid-State Circuits Society, the In-
stitute of Electronics, Information and Communication Engineering (IEICE) of
Japan, and the Institute of Electrical Engineers of Japan.
Kazutami Arimoto (M’88–SM’05–F’10) received
the B.S., M.S., and Ph.D. degrees in electric en-
gineering from Osaka university, Osaka, Japan, in
1979, 1981, and 1993, respectively.
He joined the LSI Laboratory, Mitsubishi Electric
Corporation, Hyogo, Japan, in 1981. Since then, he
has been engaged in the design and development
of DRAMs and IPs for system LSI. He transferred
to Renesas Technology Corporation, Renesas
Electronics, and Okayama Prefectural University,
Okayama, Japan, in 2003, 2010, and 2012, respec-
tively. He holds 192 U.S. patents and 69 Japanese patents. Currently, he focused
on image processing IPs, communication IPs, sensor interface, memory based
IPs and re-configurable IPs for multimedia, security, auto mobile, network,
sensor network, energy management, and future intelligent embedded systems.
Dr. Arimoto is a Senior Member of the Institute of Electronics, Information
and Communication Engineering (IEICE) of Japan. He is also a TPC member
of ISSCC and A-SSCC.