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Image Edge Detection in FPGA

Tejas Khairnar, Harikiran, Avinash Chandgude, Sivanantham S*, Sivasankaran K

School of Electronics Engineering,
VIT University,
Vellore, India
ssivanantham@vit.ac.in

Abstract—Processing of images plays a very important role in
communication systems. So this paper describes the edge
detection algorithm in image processing. The main aim behind
this is to process the image and extract accurate edge line to
reduce the size acquired by the original image. The image is
converted in black and white color to reduce the memory that it
will acquire. The image of 512*512 pixels is converted into text
file using MATLAB and is given as input to verilog code to
perform the edge detection operation
Index Terms— MATLAB, Verilog, FPGA, SOBEL
Operator.Introduction (Heading 1)
.
I. INTRODUCTION
Digital image processing becomes more and more important
in the areas of communication, management, remote-sensing,
medicine industrial-automation, seismology, robotics,
aerospace, and education. FPGA is a reconfigurable device.
This reduces the market cost and it also becomes easy for
verification and debugging process.
As from [1] we come to know that the image processing
requires more data which slowdowns the process. Hence
FPGA is the best solution for this problem as it increases the
speed. The speed can be increased more if we reduce the
memory acquired by the image that is processed. This can be
done by making a color image into a black and white image
and we can even use edge detected image. Hence the research
was done in the field of edge detection technique for
images.[6]
Reference [2] gives an algorithm which is a combination of
detection as well as evaluation of the edge detectors of the
segmentation. Edge detection can be done by using SOBEL
operator as specified in [3]. It is researched for parallelism and
the boundaries produced by SOBEL operator are not sensitive
to noise. But SOBEL operator cannot locate the complex
edges accurately[8].
The parallel processing capability of FPGA makes an
advantage of using it for image processing[4]. The main
concept is to apply the fixed mask values of SOBEL
OPERATOR on image. This reduces the complexity of
algorithm. FPGA is a reconfigurable device and because of
use of such devices the time to market cost reduces[7][10].
Also it becomes easy for verification and debugging. Actually
in sobel operator the input image received as hex file is given
to the operator[7]. This operator uses kernal matrix to produce
gradient values of pixels. This gradient values of various
pixels are compared with threshold to produce the output
image.
In this paper a similar kind of technique is used with a
different logic to achieve a value that will be compared with
threshold value
II. ARCHITECTUE
The heart of all these image processing applications is
the edge detection f the images. The image processing data
is reduced by only processing the edges of the image[5].
Fig1 shows the block diagram of image edge detection
using FPGA. The image cannot be given directly as input to
the FPGA. due to this reason MATLAB is used to convert
image to hex.txt file and again hex to image after modifying
it in FPGA system.
OUTPUT
INPUT
MATLAB FPGA MATLAB
. Fig.1.Block diagram of Edge Detection
Fig .2. Shows the initial process done with the input
image[6]. The image is resize to 512*512 pixels as the code
designed is only for 512*512 image. Then the image is
converted to binary format and then from binary to
hexadecimal format. Each pixel is presented in hexadecimal
format and this values are stored in a .txt file in 1 column and
262144 rows.
IMAGE OUTPUT
RESIZE IMAGE TO BINARY BINARY TO HEX
Fig.2.Processing in MATLAB
Fig.3. shows that the text file is taken as input from the test
bench designed for edge detection. one by one the pixels are

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 2015 Online International Conference on Green Engineering and Technologies (IC-GET 2015)
taken as input and are then compared with a threshold value. If
the pixel value is less than the threshold value then the edge is
detected else it is not an image. When edge is detected the
output variables are assigned a '0' value else they are assigned START
'255' value.

OUTPUT Input image to hex file

TXT RECEIVE PIXEL COMPARE THEM GENERATE A EDGE conversion
ONEBY ONE WITH THRESHOLD DETECTED HEX

Fig.3.Image processing module

Consider variabels:i-
Fig1 shows how the file generated by verilog code is 0,j=0,Rin,Gin.Bin,Temp
processed in MATLAB. The hexadecimal file generated by
verilog code contains only 255 or 0 hex values. The
MATLAB code converts this hexadecimal values back to
image.
If i<262144

Then the original image is converted to edge detected

image. The converted image is in black and white colours
only. This also helps in increasing the speed of image
processing {Rin,Gin,Bin}=temp[i];
i=i+1;process values

III. FLOW CHART

The flowchart shown indicates the flow of operations

carried out in VERILOG and MATLAB. The input image is
If j<24
converted to hex file and given as input in verilog. Declare all
the integers, reg and wires required. As it is a 512 by 512
image we execute the loop 262144 times to access the pixel
values stored in the file with 262144 rows and 1 column. If i is j=j+1;
less than 262144 then the ith value is assigned to the temp output values are stored
variable that transfers those values in inputs Rin, Gin, Bin in outputreg
equally. Increment i by 1.
Now process values means consider the input pixel. As the
pixel is stored in 3 registers we take average of all the values in
store the reg values in
this registers and store the result in some other variable.
temp
value2 = (Rin + Gin + Bin) / 2 (1)
value4 = (Rin + Gin + Bin) / 4 (2)
value = (value2 + value4) / 2 (3)
write this hex values in a
This value is compared with threshold value and if edge is .txt file
detected the Rout, Bout and Gout contain zero else 255.
Now consider integer j to receive the outputs in some
registers. As one pixel is of maximum 24 bits this loop will
execute 24 times. Then this values are stored in tempc After the
execution of both loops that is the false condition will indicate convert .hex to image
that the operation in verilog is finished.
Using write memory command get the new pixel values in
a new file with .txt format. Then use MATLAB to convert hex
file to image.Hence we get the image with edges.
Note that the equation is centered using a center tab stop. Be STOP
sure that the symbols in your equation have been defined
Fig.4.Operations carried out in Verilog
before or immediately following the equation. Use “Eq. 1” or
“Equation 1”, not “(1)”, especially at the beginning of a
sentence: “Equation 1 is . . .”
 
2015 Online International Conference on Green Engineering and Technologies (IC-GET 2015)

IV. RESULT AND DISCUSSION

The system is designed using Verilog HDL and ilplemented

using Quartus Cyclone II FPGA.The waveform obtained
explains that when the 'data_in_ready' is set ON the pixel
values of size 24 bits will be stored in 'temp' variable and this
bits will be passed to Rin, Gin, Bin inputs which are of size 8
bits. Then the average of the three inputs is achieved. This
average is compared with the given threshold value
80(01010000). If the value is less than threshold then we get
output as zero else we get output as 255. The output values are
stored in Rout, Gout and Bout. When 'ready' is set output
operation takes place. The output waveform is shown in the
figure below.

Fig.7.Result for threshold=80

Fig.5.Output waveform

Fig.8.Result for threshold=200

Fig.6.Original Image

Fig.9.Result for threshold=100

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[6] Sunanda Gupta, Charu Gupta, S.K. Chakarvarti "Image Edge

The original image contains more data which slows
the image processing down. The high intensity pixels have
high value. Hence these values do not show the edge. fig 6
shows that the threshold value set is 80 due to this more
pixels will show the image and the others will indicate the
edge. Hence as compared to figure7 figure 6 shows
accurate edges.
As we can see in Fig.8. that for threshold of 100 the
number of pixels with 255 value increases as compared to
threshold of 80. As compared to threshold of 200 the
pixels with 0 value are more. This makes the image
sharper at the edges. Hence by varying threshold we can
achieve different types of edge detected images that will
contain some different information. The edge detection of
the input image received in hexadecimal values is carried
out in MODEL SIM using Verilog coding.
Detection: A Review", International Journal of Advanced
Research in Computer Engineering & Technology
Volume 2, Issue 7 ,pp:2246-2251,July 2013
[7] D 76DHJXVD 70DUX\DPD <<DPDJXFKL ʊ+RZ IDVW LV an
FPGA in image processing, IEICE Technical Report,
Vol.108. No.48, 2008, pp.83–88
[8] G. Anusha1 , Dr.T. JayaChandra Prasad2 , Dr.D. Satya
Narayana “Implementation of SOBEL Edge Detection on
FPGA” International Journal of Computer Trends and
Technology- volume3 Issue3- 2012,pp472-475
[9] Chunhua Li; Kun He; Jiliu Zhou, "Edge Detection of Image on
the Local Feature," in Intelligent Information Technology
Application, 2008. IITA '08. Second International Symposium
on , vol.2, no., pp.326-330, 20-22 Dec. 2008
[10] Steve Kilts, Advanced FPGA Design: Architecture,
Implementation, and Optimization , John Tiley & Sons.
//output waveform not clear

V. CONCLUSION

Hence we can conclude that the image with color

intensity and more data leads to slow down the image
processing. The best option left is to keep the same data by
just detecting the edge of a image. This will produce an
image of 512*512 with only two values 0 and 255. These
reduces the data that is to be processed. Hence the speed of
image processing increases. We can also vary threshold
value to compare with pixels and get the required edge
detected image that is according to the information that
needs to be processed the threshold value can be varied to
achieve it.

REFERENCES

[1] Rajesh Mehra, Rupinder Verma “Area Efficient FPGA

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