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ADC0803, ADC0804
Ordering Information
PART NUMBER ERROR EXTERNAL CONDITIONS TEMP. RANGE (oC) PACKAGE PKG. NO
ADC0803LCN ±1/2 LSB VREF/2 Adjusted for Correct Full Scale 0 to 70 20 Ld PDIP E20.3
Reading
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
ADC0803, ADC0804
Functional Diagram
2 READ
RD
DAC Q
LSB
AGND 8 VOUT
CLK A
V+
D
COMP DFF2
6 + - Q
VIN (+) ∑ +
- Q
11 12 13 14 15 16 17 18
8 X 1/f
DIGITAL OUTPUTS
THREE-STATE CONTROL
“1” = OUTPUT ENABLE
2
ADC0803, ADC0804
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
3
ADC0803, ADC0804
Timing Waveforms
tr = 20ns
tr
V+ 2.4V
90%
RD 50%
RD DATA 0.8V 10%
OUTPUT
CS t1H
VOH
CL 10K 90%
DATA
OUTPUTS
GND
4
ADC0803, ADC0804
tr = 20ns
tr
V+ V+
2.4V 90%
50%
RD
10K 0.8V 10%
RD DATA t0H
OUTPUT V+
CS
CL DATA
OUTPUTS
VOI 10%
1.7
400
DELAY (ns)
1.6
300
1.5
200
1.4
1.3 100
4.50 4.75 5.00 5.25 5.50 0 200 400 600 800 1000
V+ SUPPLY VOLTAGE (V) LOAD CAPACITANCE (pF)
FIGURE 2. LOGIC INPUT THRESHOLD VOLTAGE vs SUPPLY FIGURE 3. DELAY FROM FALLING EDGE OF RD TO OUTPUT
VOLTAGE DATA VALID vs LOAD CAPACITANCE
3.5 1000
CLK IN THRESHOLD VOLTAGE (V)
R = 10K
3.1
VT(+)
R = 50K
2.7
fCLK (kHz)
-55oC TO 125oC
2.3
1.9
VT(-) R = 20K
1.5 100
4.50 4.75 5.00 5.25 5.50 10 100 1000
V+ SUPPLY VOLTAGE (V) CLOCK CAPACITOR (pF)
FIGURE 4. CLK IN SCHMITT TRIP LEVELS vs SUPPLY FIGURE 5. fCLK vs CLOCK CAPACITOR
VOLTAGE
5
ADC0803, ADC0804
16
7 VIN(+) = VIN(-) = 0V
14 ASSUMES VOS = 2mV
6
FULL SCALE ERROR (LSBs)
FIGURE 6. FULL SCALE ERROR vs fCLK FIGURE 7. EFFECT OF UNADJUSTED OFFSET ERROR
8 1.6
V+ = 5V fCLK = 640kHz
7 POWER SUPPLY CURRENT (mA) 1.5
DATA OUTPUT
OUTPUT CURRENT (mA)
BUFFERS V+ = 5.5V
6 1.4
5 ISOURCE
1.3
VOUT = 2.4V
V+ = 5.0V
4 1.2
Timing Diagrams
CS
WR
tWI
ACTUAL INTERNAL tW(WR)I “BUSY”
STATUS OF THE DATA IS VALID IN
CONVERTER “NOT BUSY” OUTPUT LATCHES
1 TO 8 x 1/fCLK INTERNAL TC
(LAST DATA READ)
INTR INTR
(LAST DATA NOT READ) ASSERTED
tVI 1/ f
2 CLK
6
ADC0803, ADC0804
INTR RESET
INTR
CS tRI
RD
tACC
t1H , t0H
+1 LSB
DIGITAL OUTPUT CODE
1 3 5
D+1 +1/2 LSB
5 6
ERROR
D 0 * QUANTIZATION ERROR
3 4
-1 LSB
A-1 A A+1 A-1 A A+1
+1 LSB
DIGITAL OUTPUT CODE
5 1
D+1
6
ERROR
3 3 6
D 0 * QUANTIZATION
4 ERROR
1
D-1 2
4
2
-1 LSB
A-1 A A+1 A-1 A A+1
7
ADC0803, ADC0804
Understanding A/D Error Specs connecting INTR to the WR input with CS = 0. To ensure start-
up under all possible conditions, an external WR pulse is
A perfect A/D transfer characteristic (staircase wave-form) is
required during the first power-up cycle. A conversion-in-
shown in Figure 11A. The horizontal scale is analog input
process can be interrupted by issuing a second start
voltage and the particular points labeled are in steps of 1
command.
LSB (19.53mV with 2.5V tied to the VREF/2 pin). The digital
output codes which correspond to these inputs are shown as Digital Operation
D-1, D, and D+1. For the perfect A/D, not only will center- The converter is started by having CS and WR simultaneously
value (A - 1, A, A + 1, . . .) analog inputs produce the correct low. This sets the start flip-flop (F/F) and the resulting “1” level
output digital codes, but also each riser (the transitions resets the 8-bit shift register, resets the Interrupt (INTR) F/F
between adjacent output codes) will be located ±1/2 LSB and inputs a “1” to the D flip-flop, DFF1, which is at the input
away from each center-value. As shown, the risers are ideal end of the 8-bit shift register. Internal clock signals then
and have no width. Correct digital output codes will be transfer this “1” to the Q output of DFF1. The AND gate, G1,
provided for a range of analog input voltages which extend combines this “1” output with a clock signal to provide a reset
±1/2 LSB from the ideal center-values. Each tread (the range signal to the start F/F. If the set signal is no longer present
of analog input voltage which provides the same digital (either WR or CS is a “1”), the start F/F is reset and the 8-bit
output code) is therefore 1 LSB wide. shift register then can have the “1” clocked in, which starts the
The error curve of Figure 11B shows the worst case transfer conversion process. If the set signal were to still be present,
function for the ADC080X. Here the specification guarantees this reset pulse would have no effect (both outputs of the start
that if we apply an analog input equal to the LSB analog F/F would be at a “1” level) and the 8-bit shift register would
voltage center-value, the A/D will produce the correct digital continue to be held in the reset mode. This allows for
code. asynchronous or wide CS and WR signals.
Next to each transfer function is shown the corresponding After the “1” is clocked through the 8-bit shift register (which
error plot. Notice that the error includes the quantization completes the SAR operation) it appears as the input to
uncertainty of the A/D. For example, the error at point 1 of DFF2. As soon as this “1” is output from the shift register, the
Figure 11A is +1/2 LSB because the digital code appeared AND gate, G2, causes the new digital word to transfer to the
1/ LSB in advance of the center-value of the tread. The Three-State output latches. When DFF2 is subsequently
2
error plots always have a constant negative slope and the clocked, the Q output makes a high-to-low transition which
abrupt upside steps are always 1 LSB in magnitude, unless causes the INTR F/F to set. An inverting buffer then supplies
the device has missing codes. the INTR output signal.
8
ADC0803, ADC0804
successive approximation register. A correction is made to input at 5V, this DC current is at a maximum of approximately
offset the comparison by 1/2 LSB (see Figure 11A). 5µA. Therefore, bypass capacitors should not be used at
the analog inputs or the VREF/2 pin for high resistance
Analog Differential Voltage Inputs and Common-
sources (>1kΩ). If input bypass capacitors are necessary for
Mode Rejection
noise filtering and high source resistance is desirable to
This A/D gains considerable applications flexibility from the minimize capacitor size, the effects of the voltage drop across
analog differential voltage input. The VlN(-) input (pin 7) can this input resistance, due to the average value of the input
be used to automatically subtract a fixed voltage value from current, can be compensated by a full scale adjustment while
the input reading (tare correction). This is also useful in 4mA the given source resistor and input bypass capacitor are both
- 20mA current loop conversion. In addition, common-mode in place. This is possible because the average value of the
noise can be reduced by use of the differential input. input current is a precise linear function of the differential input
The time interval between sampling VIN(+) and VlN(-) is 41/2 voltage at a constant conversion rate.
clock periods. The maximum error voltage due to this slight Input Source Resistance
time difference between the input voltage samples is given by:
Large values of source resistance where an input bypass
4.5
∆V E ( MAX ) = ( V PEAK ) ( 2πf CM ) ------------ capacitor is not used will not cause errors since the input
f CLK
currents settle out prior to the comparison time. If a low-
where:
pass filter is required in the system, use a low-value series
∆VE is the error voltage due to sampling delay, resistor (≤1kΩ) for a passive RC section or add an op amp
RC active low-pass filter. For low-source-resistance
VPEAK is the peak value of the common-mode voltage,
applications (≤1kΩ), a 0.1µF bypass capacitor at the inputs
fCM is the common-mode frequency. will minimize EMI due to the series lead inductance of a long
wire. A 100Ω series resistor can be used to isolate this
For example, with a 60Hz common-mode frequency, fCM , and
capacitor (both the R and C are placed outside the feedback
a 640kHz A/D clock, fCLK , keeping this error to 1/4 LSB (~5mV)
loop) from the output of an op amp, if used.
would allow a common-mode voltage, VPEAK , given by:
∆V E ( MAX ) ( f Stray Pickup
CLK )
V PEAK = -------------------------------------------------- , The leads to the analog inputs (pins 6 and 7) should be kept
( 2πf CM ) ( 4.5 )
as short as possible to minimize stray signal pickup (EMI).
or Both EMI and undesired digital-clock coupling to these inputs
–3 3
( 5 × 10 ) ( 640 × 10 ) can cause system errors. The source resistance for these
V PEAK = ---------------------------------------------------------- ≅ 1.9V .
( 6.28 ) ( 60 ) ( 4.5 ) inputs should, in general, be kept below 5kΩ. Larger values of
The allowed range of analog input voltage usually places source resistance can cause undesired signal pickup. Input
more severe restrictions on input common-mode voltage bypass capacitors, placed from the analog inputs to ground,
levels than this. will eliminate this pickup but can create analog scale errors as
these capacitors will average the transient input switching
An analog input voltage with a reduced span and a relatively
currents of the A/D (see Analog Input Current). This scale
large zero offset can be easily handled by making use of the
error depends on both a large source resistance and the use
differential input (see Reference Voltage Span Adjust).
of an input bypass capacitor. This error can be compensated
Analog Input Current by a full scale adjustment of the A/D (see Full Scale
The internal switching action causes displacement currents to Adjustment) with the source resistance and input bypass
flow at the analog inputs. The voltage on the on-chip capacitor in place, and the desired conversion rate.
capacitance to ground is switched through the analog Reference Voltage Span Adjust
differential input voltage, resulting in proportional currents
For maximum application flexibility, these A/Ds have been
entering the VIN(+) input and leaving the VIN(-) input. These
designed to accommodate a 5V, 2.5V or an adjusted voltage
current transients occur at the leading edge of the internal
reference. This has been achieved in the design of the IC as
clocks. They rapidly decay and do not inherently cause errors
shown in Figure 12.
as the on-chip comparator is strobed at the end of the clock
perIod. Notice that the reference voltage for the IC is either 1/2 of the
voltage which is applied to the V+ supply pin, or is equal to
Input Bypass Capacitors
the voltage which is externally forced at the VREF /2 pin. This
Bypass capacitors at the inputs will average these charges allows for a pseudo-ratiometric voltage reference using, for
and cause a DC current to flow through the output resistances the V+ supply, a 5V reference voltage. Alternatively, a
of the analog signal sources. This charge pumping action is voltage less than 2.5V can be applied to the VREF/2 input.
worse for continuous conversions with the VIN(+) input voltage The internal gain to the VREF/2 input is 2 to allow this factor
at full scale. For a 640kHz clock frequency with the VIN(+) of 2 reduction in the reference voltage.
9
ADC0803, ADC0804
R R 6 20
VIN ±5V VIN(+) V+
9 +
VREF/2
10µF
DIGITAL ADC0803-
CIRCUITS ADC0804
7
VIN(-)
10
ADC0803, ADC0804
function. IC voltage regulators may be used for references if Loads less than 50pF, such as driving up to 7 A/D converter
the ambient temperature changes are not excessive. clock inputs from a single CLK R pin of 1 converter, are
allowed. For larger clock line loading, a CMOS or low power
Zero Error
TTL buffer or PNP input logic should be used to minimize the
The zero of the A/D does not require adjustment. If the loading on the CLK R pin (do not use a standard TTL buffer).
minimum analog input voltage value, VlN(MlN) , is not ground, a
zero offset can be done. The converter can be made to output Restart During a Conversion
0000 0000 digital code for this minimum input voltage by If the A/D is restarted (CS and WR go low and return high)
biasing the A/D VIN(-) input at this VlN(MlN) value (see during a conversion, the converter is reset and a new
Applications section). This utilizes the differential mode conversion is started. The output data latch is not updated if
operation of the A/D. the conversion in progress is not completed. The data from
the previous conversion remain in this latch.
The zero error of the A/D converter relates to the location of
the first riser of the transfer function and can be measured by Continuous Conversions
grounding the VIN(-) input and applying a small magnitude In this application, the CS input is grounded and the WR
positive voltage to the VIN(+) input. Zero error is the difference input is tied to the INTR output. This WR and INTR node
between the actual DC input voltage which is necessary to should be momentarily forced to logic low following a power-
just cause an output digital code transition from 0000 0000 to up cycle to insure circuit operation. See Figure 17 for details.
0000 0001 and the ideal 1/2 LSB value (1/2 LSB = 9.8mV for
VREF/2 = 2.500V). 10K 5V (VREF)
VMAX = the high end of the analog input range, and FIGURE 17. FREE-RUNNING CONNECTION
VMIN = the low end (the offset zero) of the analog range.
(Both are ground referenced.) Driving the Data Bus
Clocking Option This CMOS A/D, like MOS microprocessors and memories,
will require a bus driver when the total capacitance of the
The clock for the A/D can be derived from an external source
data bus gets large. Other circuItry, which is tied to the data
such as the CPU clock or an external RC network can be
bus, will add to the total capacitive loading, even in three-
added to provIde self-clocking. The CLK IN (pin 4) makes
state (high-impedance mode). Back plane busing also
use of a Schmitt trigger as shown in Figure 16.
greatly adds to the stray capacitance of the data bus.
11
ADC0803, ADC0804
Finally, if time is short and capacitive loading is high, external significant bits (MS) and one with the 4 least-significant bits
bus drivers must be used. These can be three-state buffers (LS). The output is then interpreted as a sum of fractions
(low power Schottky is recommended, such as the 74LS240 times the full scale voltage:
series) or special higher-drive-current products which are MS LS
V OUT = --------- + ---------- ( 5.12 )V .
designed as bus drivers. High-current bipolar bus drivers 16 256
with PNP inputs are recommended.
10kΩ
Power Supplies
Noise spikes on the V+ supply line can cause conversion 150pF 1 20 5.120V
+
10µF
errors as the comparator will respond to this noise. A 2 19 TANTALUM
low-inductance tantalum filter capacitor should be used 3 18 LSB
N.O.
close to the converter V+ pin, and values of 1µF or greater 4 17
START
are recommended. If an unregulated voltage is available in 5 ADC0803- 16
the system, a separate 5V voltage regulator for the converter VIN (+) 6 ADC0804 15
(and other analog circuitry) will greatly reduce digital noise 0.1µF 5V
7 14
on the V+ supply. An lCL7663 can be used to regulate such AGND 8 13
a supply from an input as low as 5.2V. 2.560V
VREF/2 9 12
Wiring and Hook-Up Precautions 0.1µF 10 11 MSB
1.3kΩ LEDs
Standard digital wire-wrap sockets are not satisfactory for DGND (8) (8)
breadboarding with this A/D converter. Sockets on PC
boards can be used. All logic signal wires and leads should FIGURE 18. BASIC TESTER FOR THE A/D
be grouped and kept as far away as possible from the
For example, for an output LED display of 1011 0110, the
analog signal leads. Exposed leads to the analog inputs can
MS character is hex B (decimal 11) and the LS character is
cause undesired digital noise and hum pickup; therefore,
hex (and decimal) 6, so:
shielded leads may be necessary in many applications.
11 6
A single-point analog ground should be used which is V OUT = ------ + ---------- ( 5.12 ) = 3.64V.
16 256
separate from the logic ground points. The power supply
bypass capacitor and the self-clockIng capacitor (if used) Figures 19 and 20 show more sophisticated test circuits.
should both be returned to digital ground. Any VREF/2
bypass capacitors, analog input filter capacitors, or input 8-BIT VANALOG OUTPUT
10-BIT
signal shielding should be returned to the analog ground A/D UNDER
DAC
TEST
point. A test for proper grounding is to measure the zero R
error of the A/D converter. Zero errors in excess of 1/4 LSB R
can usually be traced to improper board layout and wiring ANALOG “B” -
INPUTS A1 + “C”
(see Zero Error for measurement). Further information can
R
be found in Application Note AN018. 100R
R
- 100X ANALOG
Testing the A/D Converter “A” +
A2 ERROR VOLTAGE
12
ADC0803, ADC0804
This converter has been designed to directly interface with Interfacing 6800 Microprocessor Derivatives (6502,
8080/85 or Z-80 Microprocessors. The three-state output etc.)
capability of the A/D eliminates the need for a peripheral The control bus for the 6800 microprocessor derivatives does
interface device, although address decoding is still required not use the RD and WR strobe signals. Instead it employs a
to generate the appropriate CS for the converter. The A/D single R/W line and additional timing, if needed, can be derived
can be mapped into memory space (using standard from the φ2 clock. All I/O devices are memory-mapped in the
memory-address decoding for CS and the MEMR and 6800 system, and a special signal, VMA, indicates that the
MEMW strobes) or it can be controlled as an I/O device by current address is valid. Figure 23 shows an interface
using the I/OR and I/OW strobes and decoding the address schematic where the A/D is memory-mapped in the 6800
bits A0 → A7 (or address bits A8 → A15, since they will system. For simplicity, the CS decoding is shown using 1/2
contain the same 8-bit address information) to obtain the CS DM8092. Note that in many 6800 systems, an already decoded
input. Using the I/O space provides 256 additional 4/5 line is brought out to the common bus at pin 21. This can be
addresses and may allow a simpler 8-bit address decoder, tied directly to the CS pin of the A/D, provided that no other
but the data can only be input to the accumulator. To make devices are addressed at HEX ADDR: 4XXX or 5XXX.
use of the additional memory reference instructions, the A/D
should be mapped into memory space. See AN020 for more In Figure 24 the ADC080X series is interfaced to the MC6800
discussion of memory-mapped vs I/O-mapped interfaces. An microprocessor through (the arbitrarily chosen) Port B of the
example of an A/D in I/O space is shown in Figure 21. MC6820 or MC6821 Peripheral Interface Adapter (PlA). Here
the CS pin of the A/D is grounded since the PlA is already
The standard control-bus signals of the 8080 (CS, RD and memory-mapped in the MC6800 system and no CS decoding
WR) can be directly wired to the digital control inputs of the is necessary. Also notice that the A/D output data lines are
A/D, since the bus timing requirements, to allow both starting connected to the microprocessor bus under program control
the converter, and outputting the data onto the data bus, are through the PlA and therefore the A/D RD pin can be grounded.
met. A bus driver should be used for larger microprocessor
systems where the data bus leaves the PC board and/or
must drive capacitive loads larger than 100pF. Application Notes
It is useful to note that in systems where the A/D converter is NOTE # DESCRIPTION
1 of 8 or fewer I/O-mapped devices, no address-decoding AN016 “Selecting A/D Converters”
circuitry is necessary. Each of the 8 address bits (A0 to A7)
can be directly used as CS inputs, one for each I/O device. AN018 “Do’s and Don’ts of Applying A/D Converters”
Interfacing the Z-80 and 8085 AN020 “A Cookbook Approach to High Speed Data Acquisition
and Microprocessor Interfacing”
The Z-80 and 8085 control buses are slightly different from
that of the 8080. General RD and WR strobes are provided AN030 “The ICL7104 - A Binary Output A/D Converter for
and separate memory request, MREQ, and I/O request, Microprocessors”
IORQ, signals have to be combined with the generalized
strobes to provide the appropriate signals. An advantage of
operating the A/D in I/O space with the Z-80 is that the CPU
will automatically insert one wait state (the RD and WR
strobes are extended one clock period) to allow more time
for the I/O devices to respond. Logic to map the A/D in I/O
space is shown in Figure 22. By using MREQ in place of
IORQ, a memory-mapped configuration results.
13
ADC0803, ADC0804
INT (14)
I/O WR (27) (NOTE)
ADC0803 - ADC0804
+
1 CS V+ 20 10µF
5V
2 RD CLK R 19
3 WR DB0 18 LSB DB0 (13) (NOTE)
4 CLK IN DB1 17 DB1 (16) (NOTE)
5 INTR DB2 16 DB2 (11) (NOTE)
5V
NOTE: Pin numbers for 8228 System Controller: Others are 8080A.
FIGURE 21. ADC080X TO 8080A CPU INTERFACE
14
ADC0803, ADC0804
ADC0803 - ADC0804 +
10µF
1 CS V+ 20
ABC
2 RD CLK R 19 5V (8) 1 2 3
3 WR DB0 18 LSB D0 (33) [31]
RD 4 CLK IN DB1 17 D1 (32) [29]
RD
2 ANALOG 5 INTR DB2 16 D2 (31) [K]
INPUTS
6 VIN (+) DB3 15 D3 (30) [H]
7 VIN (-) DB4 14 D4 (29) [32]
IORQ ADC0803-
ADC0804 8 AGND DB5 13 D5 (28) [30]
FIGURE 22. MAPPING THE A/D AS AN FIGURE 23. ADC080X TO MC6800 CPU INTERFACE
I/O DEVICE FOR USE
WITH THE Z-80 CPU
18
CB1
19
CB2
10K
15
ADC0803, ADC0804
Die Characteristics
DIE DIMENSIONS PASSIVATION
101 mils x 93 mils Type: Nitride over Silox
Nitride Thickness: 8kÅ
METALLIZATION
Silox Thickness: 7kÅ
Type: Al
Thickness: 10kÅ ±1kÅ
WR
VREF/2
RD
DGND
CS
DB7 (MSB)
DB6
V+ OR VREF
V+ OR VREF
DB5
CLK R
16
ADC0803, ADC0804
N
E20.3 (JEDEC MS-001-AD ISSUE D)
20 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.210 - 5.33 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.115 0.195 2.93 4.95 -
PLANE A2
-C- A
B 0.014 0.022 0.356 0.558 -
SEATING
PLANE L C B1 0.045 0.070 1.55 1.77 8
L
D1 A1 eA C 0.008 0.014 0.204 0.355 -
D1
B1 e D 0.980 1.060 24.89 26.9 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
NOTES: e 0.100 BSC 2.54 BSC -
1. Controlling Dimensions: INCH. In case of conflict between English
eA 0.300 BSC 7.62 BSC 6
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eB - 0.430 - 10.92 7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 L 0.115 0.150 2.93 3.81 4
of Publication No. 95. N 20 20 9
4. Dimensions A, A1 and L are measured with the package seated in
Rev. 0 12/93
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpen-
dicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dam-
bar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
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ever, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No
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17