Sequential Circuits in VHDL: The

Process Statement
▪ In the combinational circuits the results
presented in their outputs depend only on
their current input values
▪ The outputs of a sequential circuit, on the
other hand, depend also on previous values
internally stored.
▪ A sequential circuit must be designed making
use of some sort of memory resources.
▪ Combinational circuits can be built based on
Boolean equations only, while sequential
circuits must employ also storage resources
as latches and flip-flops.
A process defines a sequence of
commands to be performed by
the circuit.

This means that all the

commands listed from line
16–19 are performed in the
defined order, and one after the
other.

A process is cyclic, and it never

ends. However, its list of
commands is performed only
when a change is noticed in one
of its activation signals
The signals activation list of a
process is known as the sensitivity
list. A process
is triggered by new ‘‘events’’
detected on its sensitivity list.

After the last command of a

process has been performed, the
first command in the sequence is
run again, but only after the next
time a change is picked up in one
or more signals of the sensitivity
list (e.g. line 14)

Some VHDL constructions can only

be used inside a process as, for
instance, the IF.. THEN.. ELSE
shown on lines 17–19
Signals cannot be declared
inside a process.

In a process, in case of
several assignments for the
same signal, only the last
assignment will be
performed. In the example, B
will be assigned only on line
18, and C will be assigned
only on line 20.
Describing a D Latch in VHDL

Figure shows a basic storage element, the set-reset

(SR) latch. This simple circuit manages to store
data (a single bit) through the cross-feedback loop
in the pair of cross-coupled NOR gates
Describing a D Latch in VHDL
Describing a D Latch in VHDL

The SR latch is a good option to show how a basic

storage circuit works. However, the ‘‘not allowed’’
input suggests that extra precautions should be taken
during this circuit’s usage. Basically, in most
applications, the circuit around the SR latch should
be designed in order to never allow a ‘1’ value to be
present in both S and R inputs simultaneously.
Describing a D Latch in VHDL

A D latch is built adding two AND gates and an

inverter in front of the SR latch.
With this arrangement, the ‘‘not allowed’’ input
of the SR latch cannot happen.
Describing a D Latch in VHDL
Describing a D Flip-Flop in VHDL
In a D flip-flop, the input data is stored just when
there is a transition from ‘0’ to ‘1’ (or from ‘1’ to ‘0’)
on the C input.

In a D flip-flop, the D value is stored only when the C

input changes from ‘0’ to ‘1’ (a rising edge event).

In other versions of these circuits, the D latch stores

the input data when C = ‘0’ (active low logic level),
and the D flip-flop stores the input data when C
changes from ‘1’ to ‘0’ (a falling edge event).
Describing a D Flip-Flop in VHDL
Describing a D Flip-Flop in VHDL
Describing a D Flip-Flop in VHDL
Describing a D Flip-Flop in VHDL
Describing a D Flip-Flop in VHDL
Describing a D Flip-Flop in VHDL
Describing a D Flip-Flop in VHDL