Mentor英文版教程

AppNote MG579468
A P P N O T E S SM
DxDesigner Tutorial for the Expedition PCB Flow
By: DxDesigner Customer Support

Last Modified: August 15, 2012
Valid Software Versions: EE 7.9.4
Table of Contents
Abstract .......................................................................................................................... 4
Chapter 1: Setting up the Design Data ........................................................................ 5
Exercise 1: Overview............................................................................................................... 5
Prerequisites ............................................................................................................................................................................. 5
Design Data Overview............................................................................................................................................................... 6
Checking For Pre-Existing DxWDIR Folder ............................................................................................................................... 6
Backup Pre-existing DxWDIR Folder ......................................................................................................................................... 7
Copy DxWDIR Tutorial Data to Local Location .......................................................................................................................... 7
Get Design Data from SupportNet ............................................................................................................................................. 7
Exercise 2: Setting the WDIR and DxTutorial Variables .......................................................... 8

Exercise 3: Setting Up DxDataBook ........................................................................................ 9
Exercise 4: Opening a Project ............................................................................................... 11
Exercise 5: Project and User Settings ................................................................................... 12
Project Settings ....................................................................................................................................................................... 12
User Settings .......................................................................................................................................................................... 15
Set Up Units and the Grid ....................................................................................................................................................... 16
Set Up the DxDesigner Navigator............................................................................................................................................ 17
Set Up Default Sheet Size ....................................................................................................................................................... 18
Set Up Rules for Copying ........................................................................................................................................................ 20
Chapter 2: Navigating in DxDesigner......................................................................... 22

Exercise 1: Navigator Tree Pane ........................................................................................... 22
August 15, 2012 Page 1 of 207

Copyright © 2012 Mentor Graphics Corporation
Trademarks that appear in Mentor Graphics product publications that are not owned by Mentor Graphics are trademarks
of their respective owners.
DxDesigner Tutorial for the Expedition Enterprise Flow
Exercise 2: Zooming.............................................................................................................. 26
Exercise 3: Help System ....................................................................................................... 27
Exercise 4: Window Tabs Feature ......................................................................................... 27
Exercise 5: Thumbnail Viewer ............................................................................................... 31
Exercise 6: Find/Replace Function ........................................................................................ 35
Exercise 7: Properties Pane and ICT Viewer ......................................................................... 40
Chapter 3: DxDesigner - Selecting and Verifying Parts with DxDataBook ............. 52
Exercise 1: Configure DxDataBook ...................................................................................... 52
Exercise 2: DxDataBook Libraries ........................................................................................ 56
Exercise 3: Component Selection with DxDataBook.............................................................. 57
Chapter 4: DxDesigner – Schematic Manipulation ................................................... 71
Exercise 1: Creating a New Schematic ................................................................................. 71
Exercise 2: Adding a Sheet Border........................................................................................ 73
Exercise 3: Adding Components ........................................................................................... 74
Exercise 4: Adding Power and Ground Connections. ............................................................ 79
Exercise 5: Moving Components ........................................................................................... 81
Exercise 6: Connecting the Components with Nets ............................................................... 82
Connecting by Abutment ......................................................................................................................................................... 82
Creating Nets Using the Right Mouse Button .......................................................................................................................... 83

Creating Nets using Net Mode ................................................................................................................................................ 85
Exercise 7: Naming Nets ....................................................................................................... 86

Adding Names using the Navigator ......................................................................................................................................... 90
Exercise 8: Modifying Properties ........................................................................................... 91

Property Visibility..................................................................................................................................................................... 91
Modifying Property Values ...................................................................................................................................................... 92
Adding New Properties............................................................................................................................................................ 93
Exercise 9: Working with Busses........................................................................................... 94

Exercise 10: Copying Symbols .............................................................................................. 97
Exercise 11: Renaming Properties ...................................................................................... 100
Exercise 12: Completing the Channel Circuits ..................................................................... 101
Exercise 13: Using Arrays ................................................................................................... 102
Chapter 5: DxDesigner – Hierarchical Design......................................................... 108
Exercise 1: Preparing for Hierarchical Design ..................................................................... 108
Exercise 2: Bottom-Up Hierarchical Design ......................................................................... 110

Exercise 3: Using a Hierarchical Block ................................................................................ 117

Exercise 4: Top-Down Hierarchical Design ......................................................................... 120
Chapter 6: Constraint Definition with CES .............................................................. 126
Exercise 1: Navigating CES .............................................................................................. 126
Exercise 2: Assigning Constraints and Understanding Constraint Class Hierarchies ......... 131
Exercise 3: Creating Constraint Classes ........................................................................... 133
Exercise 4: Net Classes and Schemes .............................................................................. 140
Chapter 7: Preparing a Schematic for PCB Design ................................................ 145
Exercise 1: DxDesigner Diagnostics................................................................................... 145
Exercise 2: Hierarchical Verification with DxDataBook ....................................................... 149
Exercise 3: Design Rule Checks with Tools > Verify .......................................................... 155
Exercise 4: Packager ......................................................................................................... 160
Exercise 5: Expedition PCB................................................................................................ 163
Exercise 6: eExp View........................................................................................................ 177
Chapter 8: Documenting DxDesigner Schematics ................................................. 182
Exercise 1: Cross Referencing ............................................................................................ 182
Cross Reference Settings ..................................................................................................................................................... 182
Exercise 2: DxPDF ............................................................................................................. 195

Exercise 3: Partlister .......................................................................................................... 200
Exercise 4: Archiving Projects ............................................................................................ 205

Abstract
This AppNote is a tutorial for the EE 7.9.4 release of DxDesigner. The primary focus is on
schematic capture with DxDesigner, including DxDataBook. CES, Expedition PCB, and
supporting utilities are also briefly covered by this tutorial. The goal of the tutorial is to
introduce new users to fundamental concepts and techniques to successfully create
schematics using DxDesigner. You should allow for approximately 12 hours to complete
this tutorial.
A video showing updates to the user interface for EE 7.9.4 release can be seen here:
Video: DxDesigner EE7.9.4 Release Highlights (10 min).
For instructor-led training on DxDesigner and other Mentor Graphics products, please
consider attending Mentor Graphics training classes from Mentor Graphics Education
Services department.
Additional AppNotes, TechNotes, movies, and documentation can be found on SupportNet.

Chapter 1: Setting up the Design Data

Welcome to the DxDesigner Tutorial for the Expedition Enterprise Flow! This tutorial walks
a person through the basic flow through the DxDesigner toolset in the Expedition PCB flow
using a moderately complex circuit.
Over the course of this tutorial, you will learn the following:
 Navigating in a DxDesigner schematic
 Selecting and verifying parts using DxDataBook
 Creating schematics with DxDesigner
 Creating hierarchical schematics with DxDesigner
 Using CES to add constraints to your board
 Forward annotating your schematic for Expedition PCB
 Using utilities to document your DxDesigner schematic
As a primer for this tutorial, the following short video will follow the creation of a simple
design in DxDesigner: Video: Small Amplifier Design Lab (13 min). This video is part of a
larger video series that contains content that is beyond this scope of this tutorial. Also this
video series was made for the DxDesigner 7.9.2 release, but is still applicable for the 7.9.4
release. The full series of videos can be found here: DxDesigner for University Video
Series (1hr 15min) .
Exercise 1: Overview
The tutorial assumes no prior knowledge of the tools, just a familiarity with schematic
capture and layout environments. The tutorial is organized in the same way that you would
create a real design. You begin by setting up the DxDesigner environment, you proceed to
draw a schematic, run reports, run a simulation and pass the design to Expedition PCB for
layout. The design you create in the early topics will continue to be used as you perform
more advanced tasks.
Prerequisites
 Your Operating system is Windows. This tutorial is currently not supported on UNIX or
Linux.
 Installed DxDesigner (version EE 7.9.4)
 Installed DxDataBook
 Installed CES

 Installed Expedition PCB
Design Data Overview

The DxDesigner tutorial data can be found in a downloadable DxTUT.zip file from
SupportNet. See the following figure for the structure of the .zip file.
Note: Instructions on how to download the files and where to extract them can be found on
page 7-8.
\DxWDIR
\templates
\DxTUTORIAL
\DxConfig \DxTUT_Lib \DxTUT_Proj \DxTUT_Sample
A brief overview of the tutorial and tutorial data located in the DxWDIR folder is as follows:
 DxTUTORIAL - Contains data for this tutorial covering a real-world design example
 DxTUT_Sample - Contains DxTUTORIAL design data in various stages of completion
 DxConfig - Contains ancillary files used in some topics
 DxTUT_Lib - Contains a Central Library
 templates - Template files are located in templates\dxdesigner\expedition
DxTUT_template.prj
Checking For Pre-Existing DxWDIR Folder

You need to check for a pre-existing DxWDIR folder to avoid losing data. If your local WDIR
variable currently points to a folder with the name DxWDIR and location where you want to
place the examples data, you need to back it up before starting, as the examples data will
take precedence over your existing configuration. The DxDesigner tutorial and the tutorial

designs expect your WDIR variable to be set to the DxWDIR folder provided with this
tutorial, after you copy it into to your file system.
Note: If your WDIR is currently set to your working environment location, you should note
the current WDIR setting so you can later restore it to the original value.
To check where your current WDIR variable is pointing, do the following:
1. From your Windows XP system Start menu, choose Control Panel > System >
Advanced (tab) > Environment Variables (button) to access the Environment
Variables dialog.
a. Note: The Windows 7 path is similar at: Start menu > Control Panel > System
(link) > Advanced system settings (link) > Advanced (tab) > Environment
Variables (button).
2. In the System variables section, locate the WDIR item and click the Edit button. The
Edit System Variable dialog appears.
a. If the WDIR variable points to a folder called DxWDIR in the same location where
you want to copy this tutorial DxWDIR folder, you should back up your original
DxWDIR folder as described in the topic “Backup Pre-existing DxWDIR Folder”.
b. Otherwise you can skip to the “Copy DxWDIR Tutorial Data to Local Location”
topic.
3. Cancel the Environment Variables and System Properties dialogs.
Backup Pre-existing DxWDIR Folder

These steps only apply if your local WDIR variable points to an existing folder called
DxWDIR that is located in the same location that you want to install the DxWDIR folder that
comes with the DxExamples:
1. Before running the tutorial, create a backup of your existing configuration by saving
your local DxWDIR folder to a different location.
2. When you have completed the tutorial, replace the tutorial DxWDIR folder with the
backed-up version of your own DWDIR folder if it makes sense to do so.
Copy DxWDIR Tutorial Data to Local Location

You can download the design data from SupportNet. You should copy the DxWDIR folder
to a local writable location, such as your C: drive as described below.
Get Design Data from SupportNet

This section assumes that you are getting the DxWDIR folder from DxWDIR_EE7.9.4.zip
from SupportNet.
1. Download the DxDesigner tutorial data.

2. Unzip the file DxTUT.zip anywhere in your file system. Make sure you have at least
400 MB of free space.
Note: In the resultant directory there is a .\DxWDIR tree. This is where the tutorial
data is located.
Exercise 2: Setting the WDIR and DxTutorial Variables

The WDIR environment variable is used by DxDesigner to locate default templates,
software executables, and project files. The DxTUTORIAL variable is used during the
project setup to specify the location of the Central Library to avoid hard-coding this path in
the project.
1. Change the WDIR environment variable to point to the DxWDIR folder as follows:
a. From your Windows system Start menu, choose Settings > Control Panel >
System > Advanced (tab) > Environment Variables (button) to access the
Environment Variables dialog.
Note: The Windows 7 path is similar at: Start menu > Control Panel >
System (link) > Advanced system settings (link) > Advanced (tab) >
Environment Variables (button)
b. In the System variables section, locate the WDIR item and click the Edit button.
The Edit System Variable dialog appears.
c. Set the WDIR path so {your_path}\DxWDIR is at the front of the path, similar to
that shown below and click OK:

NOTE: This is a good opportunity to make sure that the WDIR variable points to
the correct software installation tree!
2. Create a user variable called DxTUTORIAL to point to the DxTUTORIAL folder as

follows:
a. From the Environment Variables dialog, in the User variables section, click the
New button.
b. In the Edit User Variable dialog, create the DxTUTORIAL variable so that it points
to the {path_to_DxWDIR}\DxTUTORIAL folder, similar to the following example:
c. Click OK.
d. In the Environment Variables dialog, click OK.
e. In the System Properties dialog, click OK.
Exercise 3: Setting Up DxDataBook

Most of the part instantiations for the tutorial design will be performed from an application
called DxDataBook. DxDataBook uses an ODBC (Open DataBase Connectivity)
connection to link to any ODBC compliant database (for example, MS Access, MySQL,
Oracle, etc.). In order to use DxDataBook, a new ODBC DSN (Data Source Name) must be
created to point to the tutorial Access database as follows:
1. Ensure that DxDesigner is closed.

2. If you are using the Windows 7 operating system launch the ODBC Data Source
Administrator program by double-clicking odbcad32.exe at C:\Windows\SysWOW64.

3. If you are using Windows XP open the Start menu and choose Settings > Control
Panel > Administrative Tools > Data Sources (ODBC) to bring up the ODBC Data
Source Administrator.
The SampleLib DSN will

be created for this tutorial.
4. Select the User DSN tab and click the Add… button to add a new User DSN.
5. In the Create New Data Source dialog box, choose the Microsoft Access Driver
(*.mdb) driver and click Finish. The ODBC Microsoft Access Setup dialog appears.
6. In the Data Source Name field, enter SampleLib.
Note: The Data Source Name is case-sensitive, so make sure you follow the text case
as shown above.
7. In the Description field, enter: DxDataBook for Tutorial.
8. In the Database section, click the Select button.

9. In the Select Database dialog, browse to the sdd_demo.mdb database located at
C:\DxWDIR\DxTUTORIAL\DxTUT_Lib\sdd_demo.mdb as shown below.
Note: The above file path assumes you have installed the DxWDIR folder in your C:
drive.
10. Click OK in the open dialog boxes. DxDataBook is now configured for your machine.
Exercise 4: Opening a Project

To build a schematic in DxDesigner, you must first create a project. A project is a directory
of folders and files that store the relevant details of the schematic, log files, part lists, and,
even the PCB layout. DxDesigner must open the project file (.prj) in order to start your
schematic design session.
Projects can be opened using the Dashboard application (Start > All Programs > Mentor
Graphics SDD > Dashboard) or by selecting the project file (.prj) in Windows Explorer. In
the steps below you will use Windows Explorer to open the tutorial project.
1. In Windows Explorer, navigate to ${DxTUTORIAL}\DxTUT_Proj.

2. Right-click DxTutorial.prj and choose Open With > DxDesigner Application. This
will open the tutorial project in DxDesigner.
Note: If DxDesigner is not set as the default application for a .prj file, you can right-
click on the .prj file and choose Properties to specify DxDesigner as the application
that will open .prj files. If you do this, you will be able to simply double-click the project
file to launch DxDesigner.
Exercise 5: Project and User Settings

This section describes settings you can change in DxDesigner and differentiates the
Project Settings that are stored in the project file (.prj file) and the User Settings that are
stored in the DxDesigner.xml file. The former viewdraw.ini file is no longer used to store
settings.
The project file is located in the root directory of the project (in this tutorial,
${DxTUTORIAL}\DxTUT_Proj\DxTutorial.prj). The DxDesigner.xml file is located in the

WDIR folder.
The DxDesigner.xml file can reside in any, some, or all of the directories referenced by the
WDIR environment variable. If a setting appears in two or more of the DxDesigner.xml
files, the setting in the highest level – the leftmost directory as it is displayed by the WDIR
environment variable – will take precedence.
Project Settings
This section provides an overview of the Project settings. No additional project settings are
changed in this section.
The project settings will typically apply to all of the projects and generally should not be
changed by users. Key Project Settings can be set in a pre-defined template that is
selected when the user creates new projects. Templates are also a good way to ensure
that DxDesigner’s settings are consistent among users in a design group.

The Settings dialog page that you open through the Setup > Settings menu in DxDesigner
makes it very easy to understand what belongs to the project settings or to the user
settings as shown below.
In the sections that follow, DO NOT CHANGE settings randomly. Only change the settings
detailed in the instructions below. Changing settings that are not covered in the tutorial
instructions could cause DxDesigner to behave differently and lead to deviations in the
results that you produce.

Project settings are organized into the following sections:
Special Components: Defines the path to the speccomps.ini file containing predefined
symbol names for hierarchical ports based on the pin type (Input, output, bidirectional,
tri-state, open collector, open emitter, analog, power and ground), for on/off-sheet
connectors and for power/ground.
Bus Contents: Defines the path to the busconts.ini file containing predefined bus
names (typically standard buses or in-house buses) which are available to the users in
the editors.
Borders and Zones: Defines the path to the border.ini file containing predefined
symbol names for various border sheet sizes (A0…A4, A…E sheet sizes). Borders can
be automatically inserted while creating a new sheet. These settings are stored in the
borders.ini file. Also defined here are zone settings. For more information, see the
following documents:
o Partitioning a Sheet into Zones in the DxDesigner User’s Guide

o Displaying Sheet Border Zones in the DxDesigner User’s Guide
o Setting Zones to Match an Existing Border Symbol in the DxDesigner User’s Guide
Cross Reference: Defines how the link annotations appear on the schematic. This
method was introduced in EE 7.9.1 and will eventually replace the Tools > Cross
Reference method of creating cross references on links (such as off-sheet and on-
sheet references).
Net Name Delimiter: Useful to manage bus range values such as ADDR(7:0). None,
curly brackets “( )” or square brackets “[ ]” are supported.
DxDataBook: Points to a DxDataBook configuration file (.dbc) which is explained

further in Chapter 3 of this tutorial.
Sheet Numbering: Specifies which sheet numbering scheme is used.
Export HDL: You specify the VHDL or Verilog parameters of a design. This tutorial
does not cover this topic.
You can enter project settings by way of the graphical user interface if needed. In general,
they are pre-defined in a Template accessible from the project Creation dialog page. More
information can be found in the “Creating a Template File” topic in the DxDesigner
Administrator’s Guide. Template files and project files share the same syntax which makes
it easy to create a Template project.

A portion of the template used in this tutorial

(${DxTUTORIAL}\templates\dxdesigner\expedition\Tutorial.prj) is shown as follows:
SECTION DesignInfo
KEY BorderSymbols "${DxTUTORIAL}\DxConfig\borders.ini"
KEY Bus_Contents "${DxTUTORIAL}\DxConfig\busconts.ini"
KEY CentralLibrary "${DxTUTORIAL}\DxTUT_Lib\Master.lmc"
KEY DBCFile "${DxTUTORIAL}\DxTUT_Lib\SampleLib.dbc"
KEY DxD_Version "7.9.2"
KEY FrontEndSnapshot "DxD"
KEY HdlUtilsConfigFile "hdlutils.ini"
KEY NetNameDelimiter "()"
KEY PinComponents "${DxTUTORIAL}\DxConfig\speccomp.ini"
KEY SheetsEditMode "1"
ENDSECTION
You can click on the different items of the Project Settings dialog page to see what the user
interface looks like. You will change a few of these settings in the following sections of this
chapter.
User Settings
User settings are defined from the DxDesigner Setup > Settings menu. User settings are
divided into the following major categories, some of which are further divided into
subcategories. We will only change a few of them in the next sections.
Schematic Editor: The Schematic editor section includes options such as Units, Grid,
and the New Sheets definitions.
Graphical Rules Checker: Options for the setting reporting of graphical rule violations.
Interconnectivity Table: Options for the ICT Viewer and the InterConnectivity Editor
(ICE). ICE is not covered in this tutorial. The ICT Viewer will be described in
Chapter 2.
Navigator: The Project Navigator section controls the format of items displayed in the
Navigator Window.
Display: Controls the color various objects and fonts for the Graphic area of
DxDesigner.
DxDesigner Diagnostics: Controls whether Tools -> DxDesigner Diagnostics is run
when exiting DxDesigner.

Cross Probing: Controls cross probing options between DxDesigner and the chosen
layout system.
Sheet/ICT Backup: Controls behavior of automatic sheet/ICT backups.
Project Backup: Controls project's backups and backup settings.
HDL/FPGA Integration: Control HDL simulation parameters.
Run on Startup: Specify Forms or Scripts that will run when DxDesigner is started.
DxDataBook Data Source: Allows the user to enter a user name and password for a
DxDataBook data source.
Licensing: Controls which licenses you check out.
Advanced: Contains various optional settings for DxDesigner.
In the User Settings section of the tutorial you change a few settings:
 Units
 DxDesigner Navigator
 Default Sheet Size
 Rules for Copying
Set Up Units and the Grid

Set the units to Inches as follows:
1. In DxDesigner, select Setup > Settings > Schematic Editor.

2. Make sure that the Unit is set to ‘inches’.
3. Verify that the Display Grid box is checked and the Grid Spacing is set to 0.1 in. The
default Grid Type is ‘Lined’ as shown in this tutorial, but can also be changed to
‘Dotted’.

4. Verify that the Grid Interval Markings box is checked.

5. If you had to change any setting, click the Apply button. The Settings dialog box does
not close with the Apply button.
We will continue to use this dialog in the next section. Clicking OK closes the dialog.
If your settings are different than the defaults, clicking the Apply (or OK) button writes
those settings in <WDIR>\DxDesigner.xml. Only settings that differ from the default settings
are stored in that file.
From now on, all the dimensions in all the dialogs are expressed in inches.
Set Up the DxDesigner Navigator

DxDesigner’s Navigator can be configured to display net, symbol, and block information in
a variety of formats. In the following steps you will configure the format of Info Tips for
symbols.
1. From the Setup > Settings dialog, select Navigator > Symbols.
2. In the Symbols section of the Settings dialog, click the icon on the right side of
the “Info Tip format” option and select Property: Ref Designator.

3. In the “Info Tip format” dialog, add “>” characters as shown below. This will improve
the readability of the Info Tip.
4. Test the Info Tips displayed in the Navigator by hovering your cursor over a symbol.
The screen shot below shows how Info Tips are displayed.
Set Up Default Sheet Size

DxDesigner has a default sheet size for new schematic sheets. The sheet size is a property
that can be changed on a case by case basis, but in the steps below you will configure the
default sheet size that will be used in your projects.
1. From the Setup > Settings dialog, select Schematic Editor > New Sheets.
2. Set the Default Sheet Size to D.
3. Confirm that the Sheet Orientation is set to Landscape.
4. Enable the “Automatically add border to new schematic sheets” option.

5. Confirm that the “Enable user-configurable border symbols” option is enabled. The
New Sheets dialog should appear as shown below.
6. Click Apply to save the settings.

7. In the Settings dialog, select Project > Borders and Zones.

8. Confirm that the builtin:dsheet.1 border symbol has been configured for D size
sheets with a landscape orientation.
The “Horizontal Zones” and “Vertical Zones” options are for DxDesigner’s cross referencing
via Link symbols. We will leave these alone for now.
Set Up Rules for Copying

DxDesigner can be configured to handle the names of copied nets in either of the following
two ways:
a. Net names can be copied verbatim.
b. Unique net names can be automatically assigned to the copied nets.
There are times when one behavior is more preferred than another, so it is helpful to be
familiar with the “Unique Names on Copy” option.
1. Select Setup > Settings > Advanced.

2. Disable the “Unique names on copy” option.
3. Click OK to save the setting and close the Settings dialog.

4. Close the schematic and DxDesigner if you do not plan to proceed to Chapter 2.
End of Chapter 1

Chapter 2: Navigating in DxDesigner

The DxDesigner environment is used to optimize productivity with powerful and easy to use
features. There are several ways to navigate through a design. This chapter will introduce
you to several of those options. You can determine which you prefer to use.
For design data completed up to this chapter, please go here: Chapter 2 Design Data.
Note: You must first complete Chapter 1, and then copy this design data over the previous
design data, for this design data to work properly.
Exercise 1: Navigator Tree Pane

As with all panes in DxDesigner, the Navigator pane is dockable. It can be undocked and
moved within DxDesigner. The software will also remember heights and widths of any pane
modified during a working session. This is particularly beneficial in a dual monitor
configuration.
The advantage of this window is the ability to view all of the design files and to jump to
various pages or nets quickly and easily.
1. If DxDesigner is not running, open the DxTutorial project by double clicking the
${DxTutorial}\DxTUT_PROJ\DxTutorial.prj file.
2. If a previous project was open then select the Yes button to allow the software to
close the previous documents.

3. Open the Navigator Tree by selecting the icon if it is not already open.
4. Double click the LMB over the name systemdesign and notice the main window
displays the sheet systemdesign.1.

5. Next, select the icons located to the left of the systemdesign schematic, the
“Symbols” icon, and the ARRANDALE_CPU schematic.
Note: The tree should be expanded to look similar to this example.

6. Double click sheet 4 of the ARRANDALE_CPU schematic. The schematic pane will
update to display sheet 4.
7. Note: The schematic sheet tabs located at the bottom display both systemdesign.1
and ARRANDALE_CPU.4.
8. Notice that there are 2 categories that appear in the dialog for each schematic sheet:
Symbols and Nets.
9. Select the item again to expand the Symbols section of the dialog.

10. Select any of the symbol instances listed and notice the software automatically cross
probes to that item.
Note: You may need to zoom out to see the item selected during cross-probing. You
can also double-click a net or symbol in the Navigator and the schematic pane will
center on that net and zoom into it.
Exercise 2: Zooming
DxDesigner offers numerous methods for zooming in on areas of your schematic. Below
you will experiment with some methods. Your mouse can be configured in a way that the
zooming commands associated with the mouse wheel are consistent between both
DxDesigner and Expedition PCB. The steps below will show you a few methods that you
can use to zoom in and out.
1. Using the LMB click on any open area in the working area pane.
2. Press F7 and F8 on your keyboard or use the mouse wheel, if available, to zoom in or
out in DxDesigner. Practice zooming in and out while using these methods.
Note: As you zoom in, you may notice that the capacitors have a red box around
them. The red box indicates that the symbol has been updated in the Central Library
since it was added to the schematic. In Chapter 4 you will resolve the discrepancy
between the schematic and the library, so disregard the red box for now.

3. Click in the schematic editor and press Home key on your keyboard (Zoom to the
Full) to restore the view to the entire Schematic.
Note: The keyboard hot-keys (like Home or the function keys) are sensitive only when
the schematic editor pane is active. If a hot-key does not appear to work, it may be
that another pane (like the Navigator) is active. All you need to do is click in the
schematic editor pane and then execute the hot-key.
4. Press F9 and click and drag the LMB to define the area you wish to zoom in on.
Press the Home key to return to the full view of the schematic sheet.
Note: This same procedure can be done by pressing the z key, then dragging a box
around the area you wish to zoom in on.
Exercise 3: Help System

DxDesigner offers many ways to access Help. Many dialogs have a ‘Help’ button that will
bring you directly to documentation concerning that dialog. The Help menu will allow you to
access and search the entire documentation set for DxDesigner. SupportNet
(supportnet.mentor.com) also provides access to DxDesigner documentation plus
TechNotes, AppNotes, and movies on DxDesigner and all Mentor Graphics tools.
1. Notice the Help menu at the top of DxDesigner. From here you can access
documentation, support, SupportNet and tips. Take a moment to view the resources
available from this menu.
2. View all available shortcuts and system strokes by selecting Help > Show Bindings
and Help > Show Strokes. Close the Bindings window and disable the Show Strokes
mode after you have reviewed them.
Note: Navigational controls can also be configured in Setup > Settings > Schematic
Editor > Strokes, Pan and Zoom.
Exercise 4: Window Tabs Feature

One of the benefits to using DxDesigner is its ability to have several different windows
displayed within the same window pane. This helps to control the flow and access of data
that is available to engineers using the software.
One such benefit available within DxDesigner is the ability to configure several panes in a
tabbed arrangement. This allows you to enable the required dialog simply by selecting the
tab representing the window pane you wish to view.

1. With the Navigator Tree still visible, select the icons for the DxDatabook pane , ICT
Viewer pane , Properties pane , and the Output pane . This will make the
respective panes visible. Your display should look like the one below. If the topology
is in a different order that is okay, the following procedure will be the same.
Note: You should now have 5 different panes opened up in DxDesigner along with the
schematic.
2. To make things more manageable we are going to combine the DxDataBook, ICT
Viewer, and Output panes into a single pane which will be located at the bottom of the
window.

3. Using the mouse LMB, hold and select the title bar for the DxDataBook pane.
4. Drag the selected pane over the Output window.

Note: A placement guide will appear over each window, with additional placement
guides at the edges of the application. Hovering over these boxes will place the
window to the top, bottom, left, or right of the corresponding window. Placing the
curser in the center of the placement guide will combine the two windows.
Note: A blue tint appears on the target pane when the panes are ready to be
combined.

5. Release the LMB to have the DxDataBook and Output panes placed alongside each
other as tabs at the bottom of the Output dialog.
6. Repeat the operation with the ICT Viewer table. The results should look similar to the
Output Pane shown below.
7. Disable the icons , , , and to set the Lab 2 window panes back to the way
it originally was.
Exercise 5: Thumbnail Viewer

DxDesigner’s Thumbnail pane allows you to view graphical thumbnails of schematic
sheets. Thumbnails can be very useful when changing schematic sheets.
1. In the DxDesigner Navigator, double-click the systemdesign board.

2. In DxDesigner, select View > Thumbnails.
3. The Thumbnails pane is opened and it will display a graphical thumbnail of the
systemdesign.1 schematic sheet. The Thumbnails pane will display all schematic
sheets associated with the currently active hierarchical level. Since the systemdesign
hierarchical level is comprised of one sheet, only one sheet is displayed in the
Thumbnails pane.

4. In the schematic pane, right-click the ARRANDALE_CPU and choose Push.
NOTE: When you push into the ARRANDALE_CPU schematic, numerous “Port
creation failed” messages will appear in the Output pane. These occur because there
are no symbols currently defined as hierarchical ports. You will resolve these issues
in Chapter 5. Presently, you can ignore the messages.
5. The Thumbnails pane now displays thumbnails for each of the seven schematic
sheets that comprise the ARRANDALE_CPU.

6. In the Thumbnails pane, double-click the ARRANDALE_CPU.7 thumbnail. This will
open sheet 7 of the ARRANDALE_CPU schematic. Double-click other sheets to
practice opening them with the Thumbnails pane.
7. Close the Thumbnails pane by clicking the small “x” in the top right corner of the
Thumbnails pane.

Exercise 6: Find/Replace Function
The Edit > Find/Replace command launches a flexible dialog that offers numerous ways to
find and select objects in your schematic.
1. In DxDesigner, select Edit > Find/Replace or click the Find/Replace icon.

2. Click the More >> button to open all options.
3. Take time to familiarize yourself with the options available.

4. Use the “Within:” drop-down menu to define which part of the project you would like
to search. In this case select Board: systemdesign (systemdesign).
5. In the “Find what:” cell type C2 and click Find All.

6. Note: The results of the search appear in the find dialog.
7. Notice that a tab on top of the design area for the sheet containing C2 has been
opened.
8. In the Output window, a hyperlink appears that can be used to quickly jump to the
capacitor with reference designator C2.

Note: You will find capacitor C2 on the left side of the schematic sheet.
9. In the “Find and Replace Text” dialog change the “Find what” field to 22uF and click
the Find All button to find all 22uF capacitors across the systemdesign Board.

10. Notice that all parts meeting this criterion are listed in the output window.
11. Select Window > Close All to close all of the schematic pages. Alternatively, you
could click the small x to close individual sheets.

12. “Find and Replace Text” can also be used to find nets. In the dialog, activate the Use
Wildcards” checkbox.
13. Now enter the net name HOST*GOOD in the “Find and Replace Text” dialog to
search across the systemdesign schematic.
14. Select the Find All button to search the entire schematic.
Note: There are six instances of HOST_VTTPWRGOOD across three schematic
sheets.

15. When selecting an instance of the net in the Output dialog, the associated schematic
sheet is opened and that portion of the HOST_VTTPWRGOOD net is selected. This
functionality allows you to check connectivity throughout your design very efficiently.
16. If you look closely at the search results, you will see that DxDesigner found pins, nets,
and components named HOST_VTTPWRGOOD. In the “Look in” section, deselect
everything but Nets and then click Find All.
17. Review the search results and you will see two hyperlinks for the two instances of net
HOST_VTTPWRGOOD on two respective sheets.
18. Close the “Find and Replace Text” dialog.
19. Select Window > Close All to close all open schematic sheets.
Exercise 7: Properties Pane and ICT Viewer

The Properties Pane allows the user to change properties of one or many objects on the
schematic. The ICT Viewer can be used to find elements within your design. These two
panes can be used together to select and edit or add properties on multiple parts in your
schematic.
1. In the Navigator, double-click the systemdesign board.
2. Select the Properties icon or type CTRL-ALT-A as a hotkey executed from the
keyboard.
3. Select the ICT Viewer icon.

4. For this exercise you can close all panes except the Navigator, the schematic editor,
ICT Viewer and Properties panes.
Note: The scope of the ICT Viewer is controlled by the Navigator. So make sure that
you have selected the systemdesign schematic in the Navigator. Otherwise, you will
not be viewing all of the parts in the design.
5. In the ICT Viewer pane, select the Symbol Properties tab on the bottom of the
window.

6. Select all the resistors with a value of “10K” by scrolling to find the Value column in
the ICT Viewer. Click the small arrow in the first row. This will open a list of available
values. You can either select 10K from the list or you can type it into the free text
field.

7. A filter has been applied and now only the 10K resistors are shown.
Note: You can resize the width of any of the columns in the ICT Viewer by positioning
the mouse cursor over the boundary between columns and click and dragging the left
or right when you see the cursor icon appear as a double-ended arrow.
8. In the ICT Viewer, select one of the resistors with a Part Number of “3301-0028 by
selecting the resistor’s ID ($xxxx) from the leftmost column.

9. The property values for that part are shown in the Properties window.
10. Values can be changed by clicking the cell in the Properties window and typing a new
value. Change the resistor’s “Rating” property from 125mW to 250mW in the Value
column of the Properties window.
11. After entering the new value click into another cell to apply the change.
12. Select Edit > Undo or press the u key on your keyboard to restore the original value
of 125mW to the resistor.

13. Select all 10K resistors by clicking the top row in the ICT Viewer and then holding the
Shift key and clicking the bottom row in the ICT Viewer. You may need to use the
scroll bar to view the bottom of the list of resistors in the ICT Viewer. Remember that
the ICT Viewer’s scope is controlled by the Navigator. If you don’t see 23 resistors in
the list, you should check the Navigator and make sure that systemdesign is
selected.

14. After doing this, all resistor properties can be modified simultaneously by editing the
desired property from within the Properties dialog. To practice this, select the
Tolerance property row in the Properties dialog.
15. Change the value to 1% and click Enter on your keyboard.

16. In the Properties dialog enable the visibility of the Package_Type value by clicking the
checkbox in the Value cell such that a check mark is in the checkbox.
17. Inspect one of the resistors in the schematic to confirm that the Package_Type value
is now visible.
18. In the ICT Viewer select all of the 10K resistors and disable the visibility of the
Package_Type value.
19. In the Navigator, select systemdesign.

20. In the schematic pane, right-click on the ARRANDALE_CPU and choose Push.
Note: When you push into the ARRANDALE_CPU schematic, numerous “Port
creation failed” messages will appear in the Output pane. These occur because there
are no symbols currently defined as hierarchical ports. You will resolve these issues
in Chapter 5. Presently, you can ignore the messages.
21. Press the PageDn key on the keyboard until you get to Sheet 3 of the
ARRANDALE_CPU schematic. The active sheet name will show at the bottom edge of
DxDesigner.

22. Using the LMB, click on either of the two large symbols.
23. Note: The ARRANDALE_CPU part is a very large part which makes it impractical to
capture as a single symbol. Therefore, the librarian has “fractured” this part into
multiple symbols. Two of those symbols appear on sheet 3 of the ARRANDALE_CPU
schematic.
Note: Once a symbol is selected, its properties will appear in the Properties editor.

24. The Properties window will update with selections in the schematic or the ICT Viewer.
25. Close the Properties window by selecting the in the upper right hand corner of this
pane.
26. Close the ICT Viewer.

27. Select Window > Close All to close all open schematics.
Note: At no time have you had to save your work in DxDesigner. DxDesigner is
constantly saving your data. As you complete an action – like moving a part – DxDesigner
immediately writes that change into the schematic database.
End of Chapter 2

Chapter 3: DxDesigner - Selecting and

Verifying Parts with DxDataBook
DxDataBook is a component information system that allows companies to benefit from a

centralized component database system. The DxDataBook utility allows customers to
manage their library data more efficiently than ever before. It increases efficiency by
decreasing the number of symbols required to support the parts in their design
environment.
DxDataBook connects to any ODBC compliant database and makes the necessary content
available to aid in the part selection process. When the part is added to the schematic, the
property data is also added so the part is complete when it is released onto the schematic.
DxDataBook also provides component verification checks which ensure the property data
attached to the symbol in the schematic matches the respective property values in the
Centralized ODBC compliant database. This prevents incomplete or inaccurate data from
being passed into the PCB design phase.
Exercise 1: Configure DxDataBook

The system allows for easy searching and selecting of components. It can tie into a
company’s purchasing database so that engineering can make more intelligent part
selections based on lead time, cost, stock availability, etc.

2. Activate the Navigator icon and the DxDataBook icon.
3. In the Navigator, double-click the systemdesign board to open the systemdesign.1

schematic.
4. If the Output pane is open select the Output pane icon to close it.
5. Make sure that DxDataBook is connected to the SampleLib.dbc configuration file.
You can verify this by looking at the bottom left corner of DxDataBook.

6. If SampleLib.dbc is not listed in DxDataBook, then select Setup > Settings >
Project > DxDataBook and set the “DxDataBook configuration” to
${DxTUTORIAL}\DxTUT_Lib\SampleLib.dbc.
DxDataBook relies on some settings stored in your Windows Registry. In the steps below
we’ll inspect the settings of your Windows Registry to ensure that DxDataBook will display
and annotate component properties in a way that is consistent with the instructions in this
tutorial.
7. In the DxDataBook pane, right-click and choose Properties.

8. In the DxDataBook Properties dialog, click the Appearance tab.
9. Confirm that the Display option is set as “DxDesigner Property Names.” Set that
option if it is not already configured on your machine.
10. Enable the “Display numeric values with magnitude” and the “Enable DxDataBook
Window Column Tooltip” options. Click OK to close the DxDataBook Properties
dialog.

Exercise 2: DxDataBook Libraries

The Library drop-down menu contains a list of all available libraries as described in the
database source. These libraries are defined as Tables directly in the Microsoft Access
database that is used for this tutorial. The list and organization of the libraries is configured
by the DxDesigner librarian or tools administrator.
1. Choose Digital_Logic from the Library drop-down menu.
Note: The system now searches the database and lists all the components in this
library.
Note: “Matches” in the lower right side of the DxDataBook grid indicates how many
parts meet the current filter criteria.

Exercise 3: Component Selection with DxDataBook
When using a standard library configuration without DxDataBook, you must take the time to
enter properties for each instance of a part. This can be both time consuming and error
prone. This process also requires the creation of numerous extra schematic symbols. In
this exercise you will see how DxDataBook reduces the need for extra symbols by having
generic symbols populated with property values from a database. You will also see how
easy it is to search for and select specific parts from a large list.
1. From the Library drop-down menu select the Resistor library.

2. Select the “Query Builder” button to start setting the query criteria.
3. With the Query Builder dialog open, click the Condition button.

4. Select the drop-down arrows in each setting in the dialog so it matches the example
below (Package_Type; =; 0402). Select the Add button to set the criterion.
Note: This will place the search criterion into the dialog as shown, so it can be
applied.
5. Select the OK button to activate the search based on the criterion. Note: The
resulting data is based on Packge_Type equaling 0402.

6. Now narrow the search to find resistors with Value=10K and Package_Type=0402.
Launch the Query Builder again and click the AND button.
7. Click the Condition button to enable the drop-down menus in the Query Builder.
8. Select the drop-down arrows in each setting in the dialog so it matches the example
below (Value =; 10K).
9. Select the Add button to set the criterion.

10. Select the OK button to apply the additional search based on the new criterion.
Note: The list of available parts has been reduced to a single part.
11. Using the LMB select the Part 1001-0002. Notice the entire line is highlighted and the
symbol appears in the symbol preview on the right of the DxDataBook pane.
12. Using the LMB, click and drag the symbol in the preview window and place it on the
schematic.

13. Click on the Properties icon or use the modeless command CTRL-ALT-A to open
the Properties window. All the properties are on the symbol. These properties were
added to the generic symbol by the Microsoft Access database when the part was
added to the schematic. The user does not have to worry about making manual
errors in adding the properties.
Note: When symbols are added to a schematic, DxDesigner assigns a unique “Id” to
them. If you compare your schematic to the screenshots below, it is unlikely that the
“Id” properties will match. This is not a problem so you can disregard any
discrepancies between your Id properties and the Id properties shown in the
screenshots below.

14. While in the Properties editor, change the Value property field from 10K to 107K by
entering the new value in the Value column.
Note: You made a unique change to a part so the part number no longer matches the
resistor’s value. This condition could lead to a very expensive problem due to the way
parts are ordered through a company’s purchasing department. Part numbers that do
not match corresponding properties generally lead to overstocks and delays in
schedule. Both are costly and can be avoided if a DxDataBook configuration is in
place. Over the following steps you will look at how DxDataBook can find these
inconsistencies and allow you to resolve them quickly.
15. Drag another resistor from DxDataBook (Part Number = 1001-0002) onto the
schematic sheet so there are two new ones displayed.
16. Change the Libraries: setting from Resistors to Capacitor.
17.

18. Now assume you need a decoupling capacitor, but have not decided on what value of
decoupling capacitor to use. In DxDataBook, select the drop-down menu under the
Catalog_Group column and select CAP_FIXED and press Enter on your keyboard to
execute the query.
19. In DxDataBook, use the Dx_Symbol drop-down menu to select

passive_discrete:capacitor
20. In DxDataBook, use the drop-down menu below the symbol preview to select the
capacitor.2 symbol.

Note: The librarian has created symbols for both vertical and horizontal orientation. It
is good practice to select the properly oriented symbol when you add a part. Doing so
will save you the effort of rotating parts manually. Additionally, the text on your
symbols will be oriented to make it easy to read the schematic.
21. Select any capacitor listed in DxDataBook and click on the “Add new component with
common Properties” icon to add a generic component to the schematic. With the
new part active on your cursor, move both the cursor and the symbol over the working
area and select the LMB to complete the part placement.
22. Right-click after the capacitor has been added to the schematic to return the cursor to
the “Select” mode.

23. Select the capacitor and look at the Properties editor. You will notice the capacitor is
missing Value and several other properties. DxDataBook can run a complete
verification to ensure all parts are compliant with the database.
24. DxDataBook has the ability to run verification on a group of selected items, a single
page, or an entire design. For this exercise you will do a verification of the parts we
just placed.
25. Select the Filter icon located on the toolbar. Enable only the “Symbol” check box.

26. Do not close the Selection Filter dialog. It will help to remind you that you need to
restore the ability to select the other object types.
27. While using the LMB drag a select box around the three symbols we just added via
DxDataBook.
28. Restore the Selection Filter to the default settings by enabling the All checkbox and
disabling the Pin checkbox. The selection filter should appear as shown below.
29. Close the Selection Filter by clicking the “x” in the upper right corner of the dialog.

30. Click on the New Live Verification Window icon located in the DxDataBook
dialog.
Note: This button is also used for verifying an entire page if no items are selected
when it is activated.
31. A new window will open showing the three parts color-coded. If we click on any of the
parts, that part is highlighted in the schematic.
Indicates a component has multiple matches. This is the generic

component we added.
Indicates the properties on the schematic match the database and only
one part matches.
Indicates that there is a conflict between the database and the

schematic and no parts match. This is the part where we changed
the Value so it no longer matches the Part Number.
32. First, you will fix the problem with the capacitor which is not correctly specified. Using
the LMB, double-click on the Yellow Circle.
33. On the right hand side a search window opens up with the common properties
automatically applied as filters.

34. Using the LMB, select any part listed in the DxDataBook dialog.
35. Using the LMB select the Annotate Component with all Properties to add the
missing part information. Notice the circle changes from yellow to green and the
Properties Editor now shows the capacitor as a completely defined component.
36. Double-click the row that has the red circle. DxDataBook has detected that the
resistor’s value of “107K” does not exist in DxDataBook’s database.

37. In the right side of DxDataBook’s Verify tab, scroll to the right and notice that the
verify routine has found a conflict. The Value is colored red because it does not match
the database.
Note: You may have to adjust the column widths to make read the property values on
the part.
38. Using the LMB, scroll to the Value property name, click the RMB and select Remove
Condition.

39. The system will search the database and find the part that matches the previously
defined conditions.
Note: The verification routine has found a single part.
40. Using the LMB, click on the 1001-0002 part number.
41. Using the LMB, select the Annotate component with All Properties icon to
change to the new part.
42. We have now corrected the problem of the mismatched properties on the resistor. In
Live Verification mode, DxDataBook automatically re-verifies the parts and will show
that all three parts match the database.
43. Select all three parts you placed using the CTRL + LMB keys.
44. Press the Delete key to delete the three parts you added during this exercise.
45. If you are going to continue on to Chapter 4, you can leave the systemdesign
schematic open. Otherwise, close DxDesigner.
End of Chapter 3

Chapter 4: DxDesigner – Schematic

Manipulation
DxDesigner is a comprehensive schematic entry tool which combines a feature rich
environment with an easy to use GUI. DxDesigner is simple to navigate whether you are
adding parts, connections, busses or text.
Exercise 1: Creating a New Schematic

Note: The schematic shown below will be constructed during the following
exercises.

2. In DxDesigner, click the New icon , or click the down arrow and then Schematic.
3. The schematic will initially be named Schematic1. Right click on the Schematic and
select Rename. Type d2a_converter over the Schematic1 name.
Note: The d2a_converter is now a schematic in the DxTutorial project, but it is not yet
integrated into the systemdesign board. In this lab you will create the d2a_converter
schematic and in Chapter 5 you will integrate this schematic into the systemdesign
board design.

Exercise 2: Adding a Sheet Border

Adding borders into a schematic can be done several ways. The process can be automatic
or manual. You can change borders at any time to reflect a sheet size modification. In the
following steps you will change the size of this new sheet to a C sized sheet.
1. Activate the Properties dialog for the schematic sheet by double-clicking the LMB in
any blank area of the schematic.
2. Change the Drawing Size to “C” by selecting the drop-down in the Properties window.
3. RMB and pick Insert Border from the pop-up menu. The pre-defined C sheet border
will replace the D sheet border.
Note: When adding a border using this method, DxDesigner will insert the symbol for
the current sheet size as defined in Setup > Settings > Project > Borders and
Zones. This menu also stores the definitions for automatic border insertion whose
mapping(s) should be embedded in your company’s template project.

4. If needed, press F8 a few times to Zoom Out or hit the Home button to change the
view so it centers on the format.
Exercise 3: Adding Components

1. If DxDataBook is not open, invoke the DxDataBook dialog by clicking the icon.
2. In the Search tab of DxDataBook, select the Capacitor library.

3. In the Value column of DxDataBook, type the value of 6.8pF and press Enter.
Note: The library contains a single 6.8pF capacitor.
4. In DxDataBook, select the row corresponding to the 6.8pF capacitor.

5. Drag and drop the 6.8pF capacitor from the DxDataBook symbol preview pane onto
the schematic.

6. Zoom in on the capacitor by entering a capital Z on the keyboard.
The hot-key Z is a helpful command that will zoom in on whatever objects are selected
in the schematic pane. Make sure that you are aware of the state of Caps Lock
because some commands are case-sensitive.
Note: There is red box outlining the capacitor. This is how DxDesigner alerts you that
symbols have been changed in the library. If you saw this in one of your designs it
would be wise to contact your librarian to find out how the symbol was changed. In this
case, default values for some symbol properties have been added to the symbol. This
has no impact on the integrity of the schematic, but DxDesigner will flag any change to
a symbol file with a red box. In the following steps you will execute a command that
will accept the symbol changes and clear the red box.

7. Select Tools > Update Symbols. The Update Symbols command will inspect your
project and identify all symbols that have been updated in the Central Library since
the time they were placed in the schematic. The “Component definition update” dialog
allows you to select which symbols you would like to update.
8. With the capacitor.1 checkbox selected, click OK in the “Component definition update”
dialog to update the symbol. When the update process concludes, the red box will
disappear.
9. In DxDataBook, right-click and choose Remove All Conditions to clear the current
query.
10. In DxDataBook, search the Capacitor library for a capacitor with a Value of 100nF and
a Tolerance of 20%. Add it to the schematic.
11. Switch the DxDataBook library to the AD_DA library. Here you will find only one part,
the da_8bit.1 symbol.
12. Before you add the da_8bit.1 symbol to the schematic, select the pin numbers for the
part from the “Slot” drop-down menu.
Note: If you add a part from DxDataBook without selecting a slot, it will have no pin
numbers. This is not necessarily a problem because the Packager will add any pin
numbers that are missing prior to opening the design in Expedition PCB. However,
most schematic designers want to have the pin numbers on their parts when they are
added to the schematic, so it is good practice to select the Slot option when you are
adding symbols to your schematic.
13. Drag and drop the da_8bit.1 symbol onto the schematic.
14. Arrange the three components as shown in the screenshot below.
15. Close the DxDataBook dialog.

Exercise 4: Adding Power and Ground Connections.

1. Open the Settings dialog using Setup > Settings.
2. Navigate to Project > Special Components. Then, select Power from the drop-
down menu and click the New icon.
3. The “Power Symbol” dialog will open and allow you to browse the libraries for a power
symbol. Select the pwr.1 symbol from the builtin library. Click OK.
4. Follow the same process but this time select Ground in the Special Components
dialog. Then, from the builtin library select gnd.1 and select OK.

5. Select the OK button to exit the “Settings” dialog.
Note: Now, in your toolbar for DxDesigner the Special Components icon will
display the pwr.1 and gnd.1 symbols.
6. Click on the Special Components icon and select the builtin:pwr.1.
7. A power pin will be attached to your cursor. Select the LMB to place the power symbol
in the working area. When you have placed it click RMB to exit the power pin mode.
Note: When you add a pin using this method, DxDesigner enters a mode where a pin
is added each time you click the LMB. You can exit that mode by clicking the RMB or
by pressing the Esc key.
8. Follow the same steps to add a Ground symbol to the schematic.

Exercise 5: Moving Components

To move components:
A. Click and hold the LMB down while the cursor is over the part you wish to move.
Drag the cursor to the desired location.
B. Release the LMB to drop the part.
1. Arrange the components as seen in the figure below.
Note: You can select multiple components simultaneously by holding down the CTRL
key while selecting all desired parts with the LMB.
When you have selected all of the intended parts release both the CTRL key and the
LMB.
Click any of the selected parts with the LMB and drag the parts to a new location.
Release the LMB to place the parts.
2. Use the method described above to move all of the parts to the center of the sheet.
3. When you have moved the components, click in vacant area of the schematic to
deselect all of the components.

Exercise 6: Connecting the Components with Nets

There are a few ways to add nets to components. This section will experiment with a few
different options.
Connecting by Abutment
1. Click the Zoom Area icon and draw a frame around the symbols you added. This
will cause DxDesigner to zoom in around those parts.
2. Select the power pin (pwr.1).
3. Select and hold the LMB and drag the first power pin to the point where the power pin
touches the end of pin 13 on the da_8bit.1 symbol. A purple star will appear letting
you know that a connection is going to be made when the power pin is placed at that
location.
Note: It is important that the ends of the two pins share the same grid location. If the
pins overlap each other, they will not be joined.
4. Place the power pin by releasing the LMB.

5. Select the power pin again and drag it away from the IC. The pins are automatically
connected as we drag the power pin away from the IC symbol. Release the LMB to
place the power pin approximately 10 grid points above the IC.
Note: If your connection does not look like the screenshot above, repeat steps 3
through 5 above.
6. Use the Abutment method to connect the ground pin to pin 6 of the IC component.
Creating Nets Using the Right Mouse Button

DxDesigner can create nets if you right-click the mouse while the cursor is near the end of
a pin or a dangling net.
1. Position the mouse cursor above pin 16 of the IC, but make sure that the cursor is not
touching or on top of the pin.

2. Click the RMB and move the cursor. A net will be connected between the mouse
cursor and pin 16.
Note: If the Strokes feature is enabled, you may end up issuing a stroke command
instead of drawing a net. The key to ensuring that you draw a net (rather than issue a
stroke command) is to make sure that:
a. The mouse cursor is not on the pin, but near the end of the pin.
b. The mouse cursor is stationary when you click the RMB.
3. Move the mouse cursor upward three or four grid points. The net will follow the
mouse without your having to hold a mouse button.
4. Click the RMB and move the cursor to the left. This will allow you to create a bend in
the net.
Note: You could have simply moved the cursor to the left and the net would turn to the
left. Clicking the RMB to turn the net has the advantage of precisely determining
where the net bend occurs.
5. Position the cursor on the net between pin 13 and the power pin and click the LMB to
complete the connection. The net should appear as shown below.

6. Use the same method to connect the ground pin to pins 6 and 2 of the IC.
Creating Nets using Net Mode

1. Select the Net icon (or type n using the keyboard) to put the software in “Add Net”
mode. This mode suspends all other LMB functions in the schematic editor window.
Below you will use the “Add Net” mode to add a net to pin 14 on the IC.
2. Position the cursor at pin 14.
3. Click and hold the LMB and move the mouse cursor to the right. This will create a net.
4. Release the LMB to terminate the net.

5. Follow the process outlined in steps outlined above to add straight nets to pins 1, 5,
and 15 on the IC.
6. Click the RMB to exit the net mode. Alternatively, you can press the ESC key on the
keyboard or select the Select icon to exit net mode.
Exercise 7: Naming Nets

1. Double-click the net connected to pin 14 of the IC. This will open the Properties dialog
and display the properties associated with the net.

2. Enter A as the value for the Name property.
3. In the schematic editor, select only the name (A) and move it away from the net and
release LMB. Notice that a dashed line indicates the net to which the Name belongs.
1. Move the net name back to its original position on top of the net.
2. Select the net and move it. Note that the net name moves along with the net.
3. Return the net to its original position. You can do this either manually or by selecting
Edit > Undo or by pressing CTRL + Z.
4. In the Properties dialog click the checkbox next to the Name value. This will disable
the visibility of the Name.

5. With net A selected, note that the lower left corner of the schematic window reports
the name and ID of the net.
Note: The “Id” of your net may differ from that shown in the screenshot above.
6. Select the net connected to pin 15 and name it A.

7. In the Properties dialog, change the “Name Inverted” property to True by clicking the
LMB in the Value cell of the “Name Inverted” property. Note that this changes the
“Name” property to ~A and the name in the schematic editor is displayed with an
inversion bar.
8. In the Properties dialog disable the visibility for this net name.

Adding Names using the Navigator
1. Click the net that is attached to pin 5 of the IC.
2. Notice that the net ID will be highlighted in the Navigator.
Note: Remember that the net IDs in your schematic may differ from those shown in
the screenshots. Such differences are not a problem.
3. In the Navigator, position the cursor over the net’s ID in the Navigator and use the
RMB menu to select Rename. Rename the net CLK and click Enter. DxDesigner will
display the text case that you use. Use uppercase letters for your net names in this
tutorial.
4. Select the net in the schematic pane and use the Properties dialog to disable the
visibility of CLK.
5. Use the method described above in steps 1 through 3 to add the name V_REF to the
net connected to pin 1 of the IC.
6. Disable the visibility of V_REF.

Exercise 8: Modifying Properties
Property Visibility
1. If not already open, activate the Properties editor by selecting the Properties icon
or by entering the modeless command CTRL-ALT-A.
2. Using the LMB, select the IC.
Note: The Properties for that component are displayed in the Property editor
3. To make a property type visible you can check the box next to the desired property.
Check the box next to Package_Type. Notice Package_Type is now shown below
the symbol.

4. Make only the value visible by checking the box next to 16SO4 and unchecking the
box next to Package_Type.
Modifying Property Values

1. Select the Power pin symbol.
2. In the Properties dialog, set the Global Signal Name property to 5V.
3. Make sure that the Global Signal Name value is visible.
Note: The “Global Signal Name” property will propagate its value to be the name of
any net that connects to this pin. The ground pin symbol also has a “Global Signal
Name” property; however, it will not be edited here because it has the desired value,
“GND”, already.

Adding New Properties

1. Multiple select the IC and the two capacitors by first selecting one component and
then CTRL+LMB on each of the other two components.
2. The Properties dialog displays the properties for the three components. If any of the
properties among the selected objects have differing values the property value is
listed as <Multiple Values>.
3. In the Properties dialog, select the bottommost cell in the “Property” column.
4. A menu will appear with a list of properties that can be added to these components.
Select Cluster from the list. This will add the Cluster property to each of the
components.

5. While all three components are still selected, set the Value of Cluster to
DA_Converter.
Exercise 9: Working with Busses

1. Invoke the Bus mode by clicking the Bus icon .
2. Draw a vertical bus to the left of the IC symbol.
3. Continue the bus by adding a horizontal segment at the top of the vertical segment.
Tip: Be sure to extend the vertical bus segment so that it is aligned with pin 7 down to
pin 12 of the IC.
4. Exit the Bus mode by pressing Esc on the keyboard.

5. Select the horizontal segment of the bus.
6. In the Properties dialog, name the bus A_CHANNEL[7:0]. This creates a bus
comprised of net names: A_CHANNEL7, A_CHANNEL6, … A_CHANNEL0.
7. Select the bus name in the schematic. This will cause the bus segment to become
deselected and the Properties dialog will display the properties associated with the
bus name (rather than the bus object).
8. Set the Size property to 0.25. DxDesigner will fill in the units automatically.
9. Reposition the bus name so it sits above the horizontal bus segment.

10. Use the RMB to click the vertical bus segment and choose Rip Nets from the popup
menu.
11. Click OK in the Rip Nets dialog and move the resultant nets so they connect to the
pins on the left side of the IC.
12. Click the LMB to complete the connection to the IC pins.
13. If the Net names are too close to the IC or overlap with the IC, select the vertical bus
segment and move it to the left. The net names will follow the bus segment.
Exercise 10: Copying Symbols

DxDesigner offers many ways to copy objects. Below we will practice with two methods:
Copy and Paste and Duplication. The Copy (CTRL+C) and Paste (CTRL+V) commands
work with the operating system’s paste buffer. These commands are particularly helpful
when you intend to copy and paste between different schematic sheets or different
schematic projects. The Duplication method (CTRL+LMB and Drag) is efficient if you
intend to copy objects within a schematic sheet.
1. Hold the CTRL key down and select the power and ground pin symbols. This causes
the two symbols to be selected as a group.
2. Press CTRL+C on the keyboard. Alternatively, you could position your cursor over
one of the selected symbols and click the RMB and choose Copy.
3. Press CTRL+V on the keyboard or click the RMB and choose Paste.
Note: Nothing happens! Unlike a text editor, DxDesigner does not have an active
insertion point. Therefore, you need to click the LMB to complete the Paste
command.
4. Click and hold the LMB and move your cursor toward the capacitor symbols.
5. Release the LMB to place the copied power and ground pins.
6. Position the power and ground pins as shown in the screenshot below.

7. Use your choice of net drawing commands to make the connections shown below.
Review the steps in Exercise 6 of this chapter if needed.
8. Zoom out to see the entire schematic. You can do this by clicking the Fit All icon,
or by pressing the Home button on your keyboard. The schematic should

appear as shown below.

Now, assume it has been decided that the design will have two channels. Therefore,
you will copy this circuit and rename the nets and bus to account for the second
channel.
9. To give you more room on this page, change the sheet size back to a D sheet.
Double-click a blank area of the schematic to view the schematic properties in the
Properties dialog.
10. Change the Drawing Size to D. Notice that the C size sheet border remains.
11. Click the RMB and choose Insert Border. As seen earlier, this will replace the
current border with the pre-defined border for the now D size sheet.
12. Select the entire circuitry and then click and drag the circuitry upward to make room
for the second channel circuit.
13. With all circuitry still selected, press and hold the CTRL key then position the cursor
on the IC and press and hold the LMB (while you are still holding the CTRL key).
14. Move the mouse cursor downward and a duplicate copy will appear attached to your
cursor. Position the new circuit below the original circuit.

Exercise 11: Renaming Properties
Recall in Chapter 1 that we disabled the “Unique names on copy”. Since we disabled that
mode, at this point there are two copies of the Channel A circuit, including duplicate net
names. In the steps below you will rename the net names to make a new channel that will
be called Channel B.
1. Select the horizontal bus segment of the lower circuit.
2. In the Properties dialog, rename the bus B_CHANNEL[7:0]. Notice that the net
names that attach to the bus are automatically changed.
3. Use the same method to change the names of A and ~A to B and ~B, respectively.
The remaining net names do not need to be changed.
4. Disable the visibility of net names B and ~B.
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Exercise 12: Completing the Channel Circuits
1. Use the net drawing techniques you have learned to make the final connections
shown below. This involves joining the V_REF and CLK nets. Move nets and net
names as needed to give the schematic an orderly appearance.
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Exercise 13: Using Arrays
The Array feature can be used to add components and to add net labels. It can also be
used to add multiple objects. To practice using DxDesigner’s Array feature, you will create
an array of capacitors on a different sheet of the systemdesign schematic. The circuit that
you will create is shown below.
1. Open the ddr2_interface schematic by double-clicking its yellow icon in the Blocks
tree of the DxDesigner Navigator.
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2. Open DxDataBook by clicking its icon .

3. In the Search tab of DxDataBook, select the Capacitor library.
4. Type 10nF in the Value column and press Enter to execute the query. A single
capacitor appears in the list below.
5. Select the row associated with part number 3101-0032.

6. Click the N icon to the left of the symbol preview pane.
The N icon will cause net stubs to appear on each pin of any part added from
DxDataBook. If you subsequently click the L icon, net names will automatically appear
on the net stubs. In this case, you only need to have the net stubs, not the names, so
you will not use the L icon at this time.
7. Click and drag the capacitor from the preview pane onto the schematic. Note that net
stubs are added to the capacitor.
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8. Position the capacitor toward the top right portion of the schematic sheet.
9. Add horizontal net segments to the top and bottom net segments attached to the
capacitor. Make sure that the two segments are of equal length.
10. Select the capacitor and all of the net segments that are attached to it.
11. Select the Array button to begin the arraying process.
12. Fill in the dialog as seen below: Rows = 4, Columns = 4. Click OK.
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13. Sixteen capacitors arranged in a 4 by 4 array are attached to your cursor. Move your
mouse cursor such that there is no gap between columns and there is a reasonable
gap between rows (0.1 in. to 0.3 in.).
14. When you have the capacitors in the desired position, click the LMB to place them.
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15. Delete the capacitor on the bottom right of the array and delete the lower net stub on
each of the rows.
16. Add a power pin symbol and a ground pin symbol to the schematic.
17. Double-click the power pin symbol and set the Global Signal Name to 3V3.
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18. Add the net segments shown below to connect the power and ground pins to the
capacitors.
19. Select Window > Close All.

20. Close DxDesigner unless you intend to continue on to Chapter 5.
Note: Remember, at no time have you had to save your work in DxDesigner.
DxDesigner is constantly saving each time you complete a task.
End of Chapter 4
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Chapter 5: DxDesigner – Hierarchical

Design
A hierarchical design methodology can greatly enhance a design flow by both partitioning a
design in a logical way and by taking advantage of schematic reuse. Hierarchical
schematics are also better suited for collaborative or team design approaches. DxDesigner
has numerous features that both support and simplify hierarchical design methodologies.
In this chapter you will learn some of these features and methods.
Exercise 1: Preparing for Hierarchical Design

Hierarchical ports are required in schematics to identify which nets will drive or be driven by
nets from a higher level schematic. Therefore, whether using bottom-up or top-down
hierarchical design methods, port symbols must be available to schematic designers so
that they can add them to the appropriate nets and busses.
In this exercise you will configure your project to use input, output, and bi-directional
hierarchical ports. Normally, the pointers to hierarchical port symbols should be pre-
configured by your tools administrator or librarian and stored in the speccomps.ini file.
However, for the purpose of this exercise, you will manually define these settings for your
project.
2. In the DxDesigner Navigator, double-click the d2a_converter block that you created
in Chapter 4.
3. Select Setup > Settings > Project > Special Components.
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4. With Port IN as the component type, click the New (Insert) icon .
5. In the Port IN dialog, unfold the builtin library and select the hier_in.1 symbol.
6. Click Apply to add the hier_in.1 port symbol to the Special Components list.
7. Change the port type to Port OUT and follow the same process to add hier_out.1 to
the Port OUT category.
8. Change the port type to Port BI and follow the same process to add hier_bi.1 to the
Port BI category. Click OK to exit the Settings dialog.
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9. This completes the port definitions that you will need for this tutorial. Click on the
Special Components icon to confirm that the three hierarchical pins are now
available in the menu.
Exercise 2: Bottom-Up Hierarchical Design

Bottom-up hierarchical design involves first creating a schematic and then creating a
hierarchical symbol that represents that schematic. Bottom-up design tends to be a good
method for users who are new to hierarchical design since it starts with the familiar task of
creating a schematic.
In this exercise you will return to the d2a_converter schematic to build it into a hierarchical
structure. Simply put, the process of creating a bottom-up hierarchy involves the following
steps:
a. Create a schematic
b. Add port symbols to nets/ busses that traverse to the higher level
c. Generate the hierarchical symbol
In Chapter 4 you created the d2a_converter schematic, so in this exercise you will continue
the effort by adding hierarchical ports to the schematic’s nets and busses.
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1. In the d2a_converter schematic, multiple select the CLK, A_CHANNEL[7:0], and
B_CHANNEL[7:0] bus/net segments shown below.
Note: Remember that you can select multiple objects by holding down the CTRL key
and selecting two or more objects.
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2. Click the Special Components icon and select the IN: builtin:hier_in.1 symbol from
the list.
Note: The net and bus names are added to the hierarchical port.
3. Select the output nets A, ~A, B, and ~B.
4. Use the Special Components icon and select the IN: builtin:hier_out.1 symbol from
the list.
5. Select the V_REF net.
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6. Use the Special Components icon and select the BI: builtin:hier_bi.1 symbol from
the list.
7. Position the names on the hierarchal pins as you would like to see them. The
d2a_converter schematic should now appear as shown below.
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8. Choose Tools > Generate Block Symbol.
9. In the Generate Symbol dialog, click the Advanced button.

10. In the Advanced Options dialog set Pin spacing and Pin length to 0.200 and click
OK to return to the Generate Symbol dialog.
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11. Click OK in the Generate Symbol dialog. The Symbol Editor will be launched to allow
you to inspect and, if needed, change the symbol. Notice that the nets that had
hierarchical ports are all represented on the symbol.
Note: The exact positioning of the pins on your symbol may differ from the screenshot
above. In the steps below, you will modify the position of the symbol pins.
12. Use the Pins dialog to set the V_REF pin’s side to “Top”.
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13. Position the V_REF pin centered on the top of the symbol.
14. Rotate the “V_REF” name so it can be read horizontally by selecting the pin name and
clicking the Rotate 90 icon .
15. The symbol should appear as shown below. Make modifications as needed to match
the symbol below.
Note: If you move a pin, the pin’s name will follow it.
16. Update the symbol outline by choosing Symbol > Update Symbol Outline.
17. When you have completed the symbol edits, choose File > Save All and exit the
Symbol Editor.
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Exercise 3: Using a Hierarchical Block

Now that you have created a hierarchical block for the d2a_converter, you will find symbol
in the project’s Local Symbols and you will be able to add this block in other schematics
within the project. Each time you add the symbol, the underlying schematic will also be
added.
1. Launch DxDataBook.
2. In the Navigator, double-click the systemdesign schematic under the Boards tree.
3. In DxDataBook, select the CL View and the Symbol View tab.
4. If needed, expand the width of the Symbol column so you can read the names of the
symbols.
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5. Expand the [local symbols] partition and select the d2a_converter.1 symbol.
6. Drag and drop the symbol from the preview pane into the systemdesign schematic,
placing it in the location shown below.
7. Connect all of the nets and busses in that part of the schematic to the d2a_converter
symbol.
8. In the schematic, click the RMB on the new symbol and choose Push from the menu.
This will open the underlying d2a_converter schematic that you created.
9. Click the systemdesign tab at the top of the schematic editor to return to the top level
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of the design.
10. Double-click the d2a_converter symbol to invoke the Properties dialog.
11. In the Name property, enter D2A_CONVERTER in the value.
Note: Now that you have added the d2a_converter block to the systemdesign board,
the DxDesigner Navigator displays d2a_converter as a branch under the
systemdesign board. If you look in the Blocks tree in the Navigator you will also see
the d2a_converter there. These two schematics are the same. A change in one will
be reflected in both. The primary difference between a schematic in the Block tree
versus the Boards tree is that the Boards schematic is treated as a schematic that will
be sent to Expedition PCB. Blocks, on the other hand, are treated like an element in a
library. In essence, the Blocks tree can be thought of as a local library for the project.
One practical difference between Blocks and Boards is that there are several
commands in the Tools menu that can only be run on Boards. For example, Packager
and Cross Reference operate only on Boards, not Blocks.
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Exercise 4: Top-Down Hierarchical Design
Hierarchical blocks can also be created using a top-down method. In the top-down method
a block symbol is created first and the underlying schematic is created later. The top-down
methodology is helpful to designers who prefer to partition a design into functional blocks
prior to creating the detailed circuitry. In this exercise a top-level block will be created.
The Block feature creates a symbol that resides within the project. Such symbols are
called “local symbols.” Blocks are initially concentric rectangles where the outer boundary is
sensitive to nets and busses. When a net or bus terminates at the boundary of a block, a
pin is automatically added to the block. The block pins adopt the name of the nets and
busses. When a block is completely defined and there is no need to add further pins it
should be “frozen” in order to suspend the dynamic behavior where pins are automatically
added. If there is a need to add pins at a later time a block can be unfrozen.
The instructions below demonstrate the process of creating a hierarchical block using top-
down hierarchical design.
1. In DxDesigner click the Block icon.

2. In the schematic pane LMB and drag to draw a box in the top right corner of the
systemdesign schematic near the ARRANDALE_CPU block.
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3. The Add Block dialog appears. Enter DDR3_SDRAM as the “Block name” and click
OK to close the dialog.
4. Select all of the nets and busses that are between the ARRANDALE_CPU and
DDR3_SDRAM blocks.
Note: You could use Setup > Settings > Advanced to enable the “Area Select by
Overlap” option. This would allow you to select the nets by drawing a box that
overlaps the nets rather than completely encompassing them.
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5. Drag the selected nets and busses to the boundary of the DDR3_SDRAM block. The
nets will connect by abutment and pins will appear on the DDR3_SDRAM block
symbol.
The DDR3_SDRAM symbol is now complete. The steps that follow will finalize the
symbol and begin the creation of the underlying schematic.
6. Click and drag the right side of the DDR3_SDRAM symbol to adjust the width of the
symbol. Make sure that the net names fit within the symbol boundary.
Note: If the block symbol is too short or too long you can also adjust the height by
clicking and dragging the top or bottom boundary.
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7. Right-click on the DDR3_SDRAM symbol and choose Freeze.
Note: When a block is in the “freeze” state, the symbol will not automatically create
pins and the symbol will not be resizable. If new pins need to be added, the symbol
can be unfrozen by right-clicking it and choosing Unfreeze.
Note: When a block symbol is not in the “freeze” state you should avoid copying it.
Otherwise you run the risk of renaming the block’s pin names.
8. Right-click on the DDR3_SDRAM block symbol and choose Edit Local Symbol.
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9. In the Symbol Editor, select the outer rectangle of the symbol and delete it.
Note: The outer rectangle serves to indicate where you can connect nets and busses
while the block is in the unfrozen state. Now that the block has been frozen, you can
delete the outer rectangle so the block will appear like an ordinary symbol.
10. File > Save All and exit the Symbol Editor.
Note: When you return to the systemdesign schematic you will see that the outer box
has been removed.
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11. Right-click on the DDR3_SDRAM block symbol and choose Push.
Note: The net segments attached to hierarchical input ports are automatically
instantiated in the DDR3_SDRAM schematic. The port symbols establish the linking
between the DDR3_SDRAM symbol and its schematic.
At this point you would build the detailed circuitry for the DDR3_SDRAM section of the
systemdesign board. However, we stop here and move on to other features of
DxDesigner.
12. In DxDesigner, select Window > Close All.
13. If you do not intend to continue on to Chapter 6, close DxDesigner.
End of Chapter 5
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Chapter 6: Constraint Definition with CES

In the DxDesigner Expedition Enterprise (EE) flow, CES is the constraint editing and
management tool. CES stores actual physical parameters from Expedition PCB and signal
integrity tools such that these values can be compared against constraint settings entered
by designers. The constraint information can consist of component and trace clearances,
routing constraints, and high speed signaling constraints. CES allows constraints to be
assigned to each layer of the PCB stackup. Differential pair rules, routing schemes, and
component and class rules can also be defined and managed within CES.
Classes of constraints can be created to establish standardized collections of routing

constraints. Classes can also be constructed in a hierarchical manner. In this editor,
constraint modifications are as easy as changing properties.
CES and DxDesigner cross probe between each other. Constraint passing is immediate
since CES, DxDesigner, and Expedition PCB all share a common database.
Exercise 1: Navigating CES

1. If DxDesigner is not running, launch it by double-clicking the
${DxTutorial}\DxTUT_Proj\DxTutorial.prj file.
2. Open the systemdesign schematic by double-clicking it under the Boards tree in the
Navigator.
3. Launch CES by selecting Tools > Constraint Editing System or by clicking the CES
icon .
4. Take a moment to read the CES Tip of the Day and then close it.
Note: CES arranges design data into multiple spreadsheet tabs which include Trace &
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Via Properties, Clearances, Nets, and Parts. Other spreadsheets can be manually
created or will appear as you interact with CES.
5. Click on each of the spreadsheet tabs and take a few moments to explore the contents
of each tab. Use the scrollbars to navigate horizontally and vertically within the
spreadsheet.
Scrollbars
Spreadsheet
Tabs
Since CES allows you to define a broad set of constraints it is sometimes helpful to
use Display Groups to filter the spreadsheet columns to the subset which you intend
to edit.
Below you will learn how to use display groups.
Display Group drop-down menu
In particular, the Nets spreadsheet has over 70 columns, so display groups can
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greatly simplify the effort of defining constraints.

6. In the Nets spreadsheet, select the Display Group drop-down menu and select Net
Properties.
7. Use the horizontal scrollbar and notice that there are less than 25 columns associated
with the Net Properties display group.
8. Set the Display Group to Delays and Lengths.
9. Use the horizontal scrollbar and notice that there are less than 20 columns associated
with the Net Properties display group.
10. Set the Display Group back to All.
Since DxDesigner and CES are accessing the same database, DxDesigner can cross
probe to CES. Thus, if you select a net or component in DxDesigner, that object will
also be selected in CES.
11. In CES, enable cross probing by clicking the icon. When cross probing is
enabled the Output window will report “Cross probing server started (Port: 1).”
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12. In DxDesigner, select the bus named A_A_CHANNEL[7:0].
13. Look at the CES window to see that the A_A_CHANNEL nets are selected.
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14. In CES, expand the Constraint Classes tree in the Navigator and click the (All)
object.
By default, all nets belong to the (All) collection. Since this design is a work-in-
progress, several Constraint Classes have already been defined. A Constraint Class
is a collection of nets that will share a common set of constraints. CES supports a
variety of constructs that allow you to organize and manage these constraints. The
constructs are:
Scheme – A “rule area”. This is an area on the PCB where a set of clearances and other
physical rules will be applied. In CES you set up the rules, but the actual area where
the rules are applied is defined in Expedition PCB.
Net Class -- A collection of nets that will have the same physical constraints, such as
trace width, impedance, and clearance rules.
Constraint Class – A collection of nets that will have the same electrical constraints such
as time of flight, overshoot, and net topology.
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Exercise 2: Assigning Constraints and Understanding
Constraint Class Hierarchies
1. In the CES Navigator expand the DDR3 constraint class.
Notice that there are five other constraint classes under DDR3. This allows you to
create hierarchies of constraints. Thus, a constraint that is assigned to the DDR3
level would apply to all nets assigned to DDR3 and the five underlying constraint
classes. However another constraint could have different values in
DDR3\DDR3_Addr versus DDR3\DDR3_Clk. If you assign a constraint at two or
more levels, CES will prompt you to choose how you want the constraints to
propagate to the nets.
Below you will experiment with the way constraint values can be assigned and
managed in CES.
Note: The “Actual” column under # Vias is reserved to report the actual number of vias
that are found in the routed Expedition PCB design. When these nets are routed, you
will be able to select Data > Actuals > Import > Import Layout Actuals to compare
the constraint limit to the actual number of vias found in the design.
2. In the DDR3 row of the Nets spreadsheet, enter 2 as the Max value for # Vias and
press the Enter key. Notice that the value propagates down to all of the underlying
constraint classes.
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3. Next, enter 1 as an override value for the DDR3_Clk constraint class.
4. Go to Setup > Settings > Display > General, and change the ‘Change Impact Dialog’
radio button to Always prompt user for all values. Now change the top level (DDR3) #
Vias constraint to 3 and press the Enter key.
5. The Multi-Level Propagate dialog will appear allowing you to determine how to
handle the propagation of this new value to the lower level constraint classes. In the
dialog, read the description of each of the options. Choose Keep Overrides.
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6. Experiment with this feature by assigning another value at the top level (DDR3) and
choosing different propagation options.
7. When you have tried each of the propagation options, Type 3 in # Vias of the DDR3
constraint class and Discard Overrides.
Exercise 3: Creating Constraint Classes

In this exercise you will create a new hierarchy of constraint classes, assign nets to these
classes and specify values for the associated constraints.
1. In the CES Navigator, click the RMB on the Constraint Classes tree and choose
New Constraint Class.
2. A default name based on your computer’s login name is given to the new constraint
class. Type in a new name of AA_BB_Channel.
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3. Click the RMB on the AA_BB_Channel constraint class and choose New. This creates
a constraint class under AA_BB_Channel, again with a default name.
4. Type A_A_Channel as the name for this new constraint class.
5. Repeat steps 3 and 4 to create two more constraint classes under AA_BB_Channel.
Name them A_B_Channel and Clk. The constraint classes should appear as shown
below.
6. Click the RMB on Clk and choose Assign Nets.

7. In the “Assign Nets to Constraint Class” dialog, type A_CLK in the search cell and
press the search button.
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8. In the Nets in source constraint class pane, select A_CLK and press the > button to
move it to the Nets in target constraint class pane. Select OK to exit the dialog.
9. Click the RMB on A_A_Channel and choose Assign Nets.

10. In the “Assign Nets to Constraint Class” dialog, type A_A_* in the search cell and
press the search button.
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11. Press the > button to move the A_A_Channel nets to the “Nets in target constraint
class” pane.
12. Repeat the procedure once more to add the A_B_Channel nets to the A_B_Channel
constraint class.
13. In the CES Navigator, select the AA_BB_Channel constraint class and review the
Nets spreadsheet to ensure that you have the nets associated with the proper
constraint classes.
14. Click any “-“ icons under the A_A_Channel Constraint Class to show only the electrical
nets in the CES spreadsheet.
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15. The nets should appear under the constraint classes as shown below.
16. In AA_BB_Channel row of the Nets spreadsheet, set the # Vias Max to 3. Remember
that you will need to press the Enter key to assign the constraint value.
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17. Also in the AA_BB_Channel row of the Nets spreadsheet, set the External and
Internal Max Restricted Layer Length to 200.
18. In the Clk row change the External and Internal Max Restricted Layer Length to 100.
Notice that the Multi-Level Propagate dialog did not appear. This is because the Clk
constraint class is the lowest level, so there are no additional levels for constraint
value propagation. In other words, constraint values do not propagate upward in a
hierarchy.
19. In the Nets spreadsheet scroll over to the right until you see the Type constraint under
the Length or TOF Delay heading.
Note: If you can’t find the spreadsheet columns that you need to edit, first check to
make sure you have the proper spreadsheet tab active. If you still don’t see the
columns you need, make sure that the Display Group is set to All.
With the Type set to “Length” all of the other constraints under the Length or TOF
Delay heading will be interpreted as physical lengths (0.001 in., since we are using
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English units in this tutorial).

20. If you don’t see the Match constraint, scroll further to the right until you see the Match
column.
21. In the Match cells for the A_A_Channel nets, set the value to A_A_Channel. You can
use copy (Ctrl-C) and paste (Ctrl-V) commands to simplify the task.
22. In the Match cells for the A_B_Channel nets, set the value to A_B_Channel.
The Match constraint requires that all members of a given match group have a length
within the specified tolerance as defined by the Tol constraint. In the steps below you
will set values for the match group tolerance.
23. Set the Tol constraint for any of the A_A_Channel nets to 50. Notice that the
tolerance is applied to all other nets that are part of the match group.
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24. Set the Tol constraint for any of the A_B_Channel nets to 50.
Exercise 4: Net Classes and Schemes

In this exercise you will assign the nets found in the AA_BB_Channel constraint class to a
Net Class. Typically, net classes are defined by the PCB designer because the constraints
associated with net classes tend to be associated with manufacturability and other physical
aspects of the board. The process for creating Net Classes and Schemes is the same as
the method you learned for creating Constraint Classes; therefore, we will not create new
constraint classes, but simply assign nets to a Net Class.
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1. In the CES Navigator expand the Net Classes tree. Notice that several net classes
have already been defined for the design.
2. Select the All_Channels net class and inspect the associated constraints in the Trace
& Via Properties spreadsheet.
Notice that the trace widths and differential spacing has been set for the All_Channels
net class for each routing scheme. As mentioned earlier, a scheme is a physical area
on the PCB where a set of rules (constraints) and clearances apply. The PCB
designer will define a polygon and assign it to one of the defined routing schemes.
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The default scheme is called “Master” and the rules associated with “Master” are
applied to all parts of the board not otherwise associated with a defined scheme.
3. In the Trace & Via Properties spreadsheet, expand the All_Channels tree under the
Master scheme.
Note: Further detail is revealed allowing you define constraints for each layer of the
board stackup. A check mark in the Route column indicates that the layer allows
unrestricted routing. Layers without a check mark are subject to the Max Restricted
Layer Length constraint that we defined in the “Nets” spreadsheet earlier in this
chapter.
4. Expand the BGA scheme and the All_Channels net class.
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Note: The top-level trace width (th) is 10 thousandths, yet this value has been
overridden on most of the layers where the constraint is actually 4 thousandths. One
would think that under a BGA, the trace width rules would be equal or smaller than the
default settings, so the value of 10 th seems a bit odd. For now, we’ll trust that there
is a reason for these settings, but if you found such a rule in an actual design, it would
be a good idea to visit the author of the constraint to verify that it is accurate.
So, what do all of these rules mean? Consider an example involving the nets that
belong to the All_Channels Net Class. Anywhere on the board that is not governed by
a defined scheme, the trace widths for the “Master” scheme apply. Thus,
All_Channels nets will have a typical trace width of 4 th. If an All_Channels net enters
a region where the scheme BGA exists, the trace width will depend on the board layer.
If the net is on layer “SIGNAL_1” the typical trace width would also be 4 th. However,
if the net traveled through the BGA area on layer “SIGNAL_10”, the typical trace width
would be 10 th. Once the trace exits the BGA scheme region, the trace width rules
would revert to the constraints defined by “Master” (presuming the trace did not enter
a region controlled by a different scheme).
Now that you have inspected the All_Channels Net Class, you will assign the
A_A_Channel and A_B_Channel nets to it.
5. Activate the Nets spreadsheet.
6. Scroll the view to the left until you view the Net Class column.
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7. At the A_A_Channel row, set the Net Class constraint to All_Channels.
8. The “Multi-Level Propagate” dialog will appear. Click Discard Overrides to propagate
the net class to all of the nets under A_A_Channel.
9. Use the same method to assign All_Channels to the A_B_Channel nets.
10. For now leave the Clk constraint class in the Default net class. Close CES.
End of Chapter 6
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Chapter 7: Preparing a Schematic for PCB

Design
This exercise will walk you through the process of verifying your DxDesigner schematic and
sending it to Expedition PCB.
First you will run the DxDesigner Diagnostics to ensure the integrity of the schematic
database.
The two primary methods for verifying a design are DxDataBook and Tools > Verify. You
will use DxDataBook’s Hierarchical Verification feature to confirm that every part in the
schematic has all of the required properties. Then, Tools > Verify will perform both syntax
and design rule checks.
Finally, you will run the Packager to prepare the schematic data for placement and routing
in Expedition PCB. The Packager will check to confirm that the all symbols have a
corresponding part definition in the Central Library and that all parts have pin numbers and
a unique reference designator. If the schematic fails any of the checks performed by
Packager, errors will be recorded in Partpkg.log in the Logfiles directory of the open project.
The design will not open in Expedition PCB until Packager is able to be run without errors.
Exercise 1: DxDesigner Diagnostics

DxDesigner Diagnostics are a series of tests that can be run on a schematic to determine if
there are any issues with the schematic database. If a problem is found, the diagnostics
can also be used to make corrections to the schematic.
2. In the DxDesigner Navigator, double-click on the systemdesign board to open the
top-level schematic.
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3. Select Tools > DxDesigner Diagnostics.
The Output pane will open a tab named “DxDesigner Diagnostics” and record the
results of each test as it is run. When the diagnostics have completed, a summary will
be provided detailing how many tests were run and how many of them passed. In the
screenshot below, notice that 17 tests passed and one test failed.
4. In the Output pane, review the results of your diagnostics. If you had any errors, scroll
upward to see what diagnostics failed.
If a diagnostic failed, the Output pane would report which diagnostic failed along with
the location of the failure. $1N184
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5. If you had any diagnostic failures, scroll to the bottom of the diagnostics summary and
click the link named Click here to fix all errors.
When the diagnostic fixes are applied, the Output pane will report the results of the
corrections.
Note: If you had to fix any errors, it is a good practice to run the diagnostics a final
time to ensure that all diagnostics have passed. In the DxDesigner Diagnostics tab of
the Output pane, click the RMB and choose Clear to flush your previous diagnostic
reports.
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6. If you ran Diagnostics to fix any errors, right-click in the Output pane and choose
Clear and then select Tools > DxDesigner Diagnostics to ensure that all diagnostics
have passed.
If you want to have DxDesigner Diagnostics run each time you switch projects or close
DxDesigner you can configure DxDesigner to do just that. The steps below will show
you how to configure this feature.
7. In DxDesigner select Setup > Settings > DxDesigner Diagnostics.
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8. OPTIONAL: Enable the Execute DxDesigner Diagnostics on exit option.
Note: It is not required that you enable diagnostics to run on exit, but it might be a
good idea to try using this mode for the balance of this tutorial.
9. Click OK to close the Settings dialog.
Exercise 2: Hierarchical Verification with DxDataBook

Earlier in this tutorial you performed Live Verification with DxDataBook to confirm that a few
parts on a schematic sheet had a matching component in the DxDataBook database. We’ll
follow a similar series of steps to perform Hierarchical Verification which has the ability to
verify all parts in a schematic. One notable difference between Hierarchical and Live
Verification is that Hierarchical Verification will store any component changes into a queue
called the “Pending List”. When you want to apply component changes to your schematic
you will execute an operation that applies all updates in the Pending List. Otherwise, the
Hierarchical Verification and Live Verification processes are very similar.
1. In the DxDesigner Navigator, double-click the systemdesign board to ensure that

DxDataBook will verify the entire systemdesign hierarchy.
2. Close the Output window to make room for DxDataBook.
3. Invoke DxDataBook .
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4. In DxDataBook, invoke a New Hierarchical Verification Window.
5. In DxDataBook, click the green exclamation mark to execute the verification on the
systemdesign schematic.
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During Hierarchical Verification, DxDataBook will evaluate all parts on all sheets and
all levels of a schematic in an attempt to find matching parts in the DxDataBook
database. As you saw earlier in the tutorial, the results will be flagged by a color-
coded circle (red, yellow, green). However, there is result that you have not yet seen:
the question mark (“?”) indicates that a symbol was not found at all in the database.
Typically, this result will occur with “local symbols” – symbols which have been
created within the project and are not part of the DxDataBook library. For example, the
d2a_converter symbol that you created in Chapter 5 will have a status of “Cannot Find
Library.”
In the case of the systemdesign schematic, there are several hierarchical blocks that
are used to partition the design into meaningful sections. These symbols are not part
of the DxDataBook database and are therefore tagged with the “?” code.
6. Inspect the list of these parts that have the “?” code. Notice that most are hierarchical
blocks, yet some are also an FPGA circuit that apparently is not part of the
DxDataBook library.
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7. Scroll downward to review the remaining parts in the design.
Note: You should find that all but four of the other parts are tagged with the green
code which means an exact match was found in the DxDataBook database.
Depending on how you followed the instructions in the earlier chapters, you may have
different results from the hierarchical verification. Clicking on the match indicator
column header will order the matches according to color.
8. Click the RMB on the yellow-coded capacitor and choose Visit by name and select
any of the names from the list that appears.
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9. Inspect the schematic sheet where these capacitors appear.
10. In the DxDataBook pane, double-click the part tagged with the yellow – “Missing
Properties” – code.
11. In the middle pane of DxDataBook you should see only one match in the search list.
Select that row and click the Add Part to Pending List icon.
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12. Click the Update Design icon at the top of the DxDataBook dialog. Note: In the
verification results pane the capacitor is now tagged as OK After Update.
13. Sort the Status column and confirm that all parts now have either “OK” or “Cannot
Find Library” as the status.
Note: You should now have three types of resistors that are failing the verification by
DxDataBook. These failing resistors are the ones on which you changed the
Tolerance during Chapter 2.
14. Double-click the row that corresponds to resistor R44.
15. In the middle pane of DxDataBook, right-click on the Tolerance column and choose
Remove Condition.
Note: A single resistor is now visible in the middle pane.
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17. In the middle pane, select the row corresponding to Part Number 3301-0028 and click
the “Add Part to Pending List” icon.
18. Follow the same process outlined in steps 15 through 17 to add the other two resistor
types to the Pending List.
19. When all three resistor types have the “OK After Update” status, click the Update
Design icon.
20. If you have any other parts tagged with the yellow or red indicator, use the methods
you’ve learned to correct those parts now.
21. Close the DxDataBook pane.
Exercise 3: Design Rule Checks with Tools > Verify

DxDesigner provides an integrated and customizable design rule checker. The Verify utility
will evaluate a wide range of electrical, HDL, and syntactical issues with your schematic.
Given that hardly any two design flows are exactly alike, the tests that Verify can perform
can be customized to your unique tool flow needs. In this exercise you will configure and
execute some design rule checks on the systemdesign schematic.
1. In the DxDesigner Navigator, select the systemdesign board to set the focus of
DxDesigner to the top level of the board.
2. In DxDesigner select Tools > Verify.
3. Note that the banner of the DRC dialog confirms that the scope of the verification is
the systemdesign schematic. Make sure the “Check” option is set to Board.
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4. Click the Rules tab.

5. Click on any one of the tests and notice that a description of the test is provided at the
bottom of the DRC dialog.
6. Scroll down through the list of tests to familiarize yourself with the tests.
The tests that Verify performs are organized into nine groups:
Migration: syntax checks, legal characters, name and property lengths
Connectivity: hierarchical and flat connectivity checks
Electrical: checks for pull-ups/pull-downs, polarity checks
Hierarchy: checks to ensure hierarchical connectivity
Integrity: missing properties, pin number checks
Power&Ground: floating supply pins, legal global signals, implicit /explicit power
Device Specific: ICs, bus transceivers, op amp checks
HDL Checks: Verilog and VHDL keywords, VHDL data type and model availability
Links: tests integrity of link objects in the schematic
Design rule checks can be enabled either as entire groups or as individual checks.
Checkboxes in the Rules tab are used to enable a specific group or test.
The Rules tab also allows you to configure settings/limits for each test along with the
severity of the associated error message.
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7. In the Rules tab, enable the Migration group. This enables each of the individual
tests under Migration Group.
8. Deselect drc-004.
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9. Click OK to execute the tests.

10. Review the DRC output messages.
Note: You will see that 26 drc-002 errors occurred and two drc-006 errors occurred.
The drc-002 errors are caused by net name characters that Verify considers illegal.
The drc-006 errors are caused by two symbols having a property named RB Layer
Map which exceeds the 80 character limit on property values.
You will first focus on correcting the drc-002 errors. If you look at the net names that
failed drc-002 you might guess that this check is failing on the “$” and “~” characters.
If you add these characters to the parameters for drc-002 you should be able to clear
this error.
Note: Editing parameters for Verify really should be the job of a tools administrator
and/or a librarian. Schematic designers ought to avoid making changes to the rules
for Verify. If a test failed and you felt that it may be an erroneous result, you should
discuss it with your tools administrator.
11. In the DRC tab of the Output pane, right-click and choose Clear.
12. Select Tools > Verify to launch the DRC dialog and activate the “Rules” tab.
13. Inspect the “Values” cell associated with drc-002.
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14. Change the “Values” for drc-002 to read as follows: ^([a-zA-Z_0-9+-. ~$]*)$
Note: This format makes the “$” and the “~” characters acceptable to drc-002
regardless of where in the string these characters appear.
15. Click OK to run the design rule checks again.
Note: Now only the two drc-006 errors occur. This test checks the length of property
values and will issue an error if a property’s value exceeds a limit that is defined in the
Rules tab.
16. In the DRC tab of the Output pane, RMB > Clear.
17. Open the DRC dialog (Tools > Verify).
18. Change the value for drc-006 to 255.
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19. Click OK to execute the tests with the new settings. The tests should complete with 0
errors.
Exercise 4: Packager
The Packager will prepare the schematic database for the place and route phases that will
be completed in Expedition PCB. Packager will assign reference designators and pin
numbers where needed. For each part in the design, Packager will make a local part
database. This process ensures that each part in the schematic is properly represented in
the Central Library. If there are duplicate reference designators or parts missing in the
Central Library, Packager will issue error messages. If you receive any error messages,
they must be resolved prior to your being able to open the design in Expedition PCB.
In this exercise you will run Packager on the systemdesign schematic.
1. In DxDesigner select Tools > Package.

Note: Any Errors, Warnings, or Notes that occur are recorded in the Partpkg.log file in
the \logfiles folder of the project. It is a good practice to review the Partpkg.log file after
running the Packager.
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2. Configure the settings as shown below and click OK to execute the Packager on the
systemdesign board.
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3. Packager messages will be recorded in the Packager tab of the Output pane. If the
packaging was successful, the Output pane will report the message shown below.
For normal operation, the options shown here should be sufficient for packaging your
designs. The Packaging Options can be configured such that the Packager will
remove all pre-existing reference designators and assign new ones. This is an
operation that you must be careful to use only when it is appropriate.
Similarly, the PDB Extraction Options can be configured to control the operation where
part data is fetched from the Central Library and stored locally in the project. If your
Central Library has changed, you may need to use one of the options that would
delete and rebuild the local library.
Note: Caution must be used when selecting “Repackage All Symbols” from the
Operation drop-down in the Packaging Options section of the Packaging Dialog as this
option will remove all pre-existing reference designators and assign new ones.
More details on these options are provided in the DxDesigner documentation as well
as in Mentor Graphics’ DxDesigner courses.
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Exercise 5: Expedition PCB
During this exercise you will open the systemdesign board in Expedition PCB and explore
some of the basic features of Expedition PCB. You will import your design into Expedition
PCB, place some parts, renumber reference designators, and back annotate your changes
to the schematic. The Following video will give you a brief overview of some of those
techniques. Video: Create a PCB with Expedition Enterprise (5 min).
In Chapter 4 you added the “Cluster” property to the components in the d2a_converter
schematic. The “Cluster” property enables the PCB designer to identify and tightly group
components sharing this property in Expedition. This exercise will demonstrate the
advantage of using the “Cluster” Property.
1. In DxDesigner, select Tools > Expedition PCB or click the Expedition PCB icon .
Where this is the first time schematic data is being passed forward to Expedition
layout you need to select a layout Template using the Select Template drop-down in
the “DxDesigner To Expedition PCB” dialog to choose the desired Template as shown
below.
PCB templates can be thought of as “seed” boards. They can be as simple as a bare
board outline or they can be boards that are partially placed and routed. The “test”
template, as you will see, is partially placed and routed.
Note: The “PCB directory” setting may differ from the screenshot if you installed the
tutorial data in a location other than “c:\”.
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2. Use the “Select template” drop-down menu to select the systemdesign template.
3. Accept the default PCB directory setting and click OK. Note: The DX2EXP dialog will
inform you that the PCB directory does not exist.
4. Click OK to the warning about the target design having 12 metallic layers.
5. Click OK to create the new directory for the PCB design.
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6. Note: When Expedition PCB is invoked, you may need to bring the Expedition layout
window to the foreground on your screen. After doing so, you will see a dialog
requesting confirmation that you wish to forward annotate DxDesigner data to
Expedition.
7. Forward Annotating to Expedition PCB reads the schematic data and imports any
changes that were made to the schematic since the last time you forward annotated
data to Expedition.
8. When Expedition PCB invokes, click Yes to Forward Annotate the design.
9. The template board will appear along with the Project Integration dialog. The Project
Integration dialog allows you to control how unused parts and traces are handled if
symbols and nets have been removed from the schematic. Additionally, Forward
Annotation will cause new symbols and nets to be added to the PCB database.
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10. Set the “Library extraction options” to “Delete local data; then rebuild all local library
data”. This will ensure that all part details are up to date with the Central Library.
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11. In the Project Integration dialog, click the amber button named “Forward Annotation
Required, connectivity changed”.
12. When the Forward Annotation is complete, notice that the pending schematic CES
changes were also updated in the PCB database and all status indicators are now
green.
13. Close the Project Integration dialog.

Note: In Chapter 4 you created the d2a_interface schematic. At that time you added
the Cluster property to each of the parts. In the following steps you will use the Cluster
property for placing these parts.
14. In Expedition PCB, select Place > Place Parts and Cells.
15. If the “Reusable Block License Requirement” dialog appears, click OK
Note: This board has a pair of reusable blocks. In DxDesigner, an advanced license is
required to place reusable blocks. In this exercise, you will not interact with the
reusable blocks so it will not matter whether or not you own that license.
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16. In the “Place Parts and Cells” dialog, make sure the “Unplaced” and “Placed” options
are checked and the other “Include” options are unchecked.
17. Use the Criterion drop-down menu to choose Cluster.

Note: The DA_Converter cluster that you created appears in the list of cluster names.
Note that the # column specifies how many parts are in the cluster. There are six parts
because when you created a copy of the D2A circuit, the Cluster property was also
copied.
18. Select the DA_Converter cluster name.
19. Click the single downward pointing arrow to load the DA_Converter cluster for
placement.
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20. Use the Action drop-down menu to select Place and ensure that “Method” is set to
“Sequence”.
Note: When you click Apply, the parts in this cluster attach to your cursor in sequence
for placement in Expedition.
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21. In the list of Active Parts, select RefDes IC1.
22. Use the “Active angle” drop-down menu to change the option to 90 degrees.
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23. Click Apply.

24. The “Place Parts and Cells” dialog will temporarily disappear and the focus of the
mouse cursor will move to the Expedition PCB window.
Note: You can roll the mouse wheel to zoom in and out of the board view.
25. Position IC1 on the left side of the board and press the LMB to place the cell in the
location shown below.
IC1
Note: When you placed IC1, the list of Active parts displays a “P” – meaning “placed”
– next to the RefDes column.
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26. Repeat the process to add IC2 to the right of IC1.
IC2
27. In the “Place Parts and Cells” dialog, change the “Active Layer” setting to Bottom.
28. Select C52 and click Apply and place it underneath IC1.
29. Select C54 and click Apply and place it also below IC1.
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30. Use the same process to place C53 and C55 beneath IC2.
31. The DA_Converter parts should appear as shown below.
32. Close the “Place Parts and Cells” dialog.

33. In Expedition PCB, select ECO > Renumber Ref Des.
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34. In the “Process list”, assign IC1 a new Ref Des of IC100.
35. Assign IC2 a new Ref Des of IC200.
36. Click Apply to change the Ref Des properties.

37. In the graphic area of the “Renumber Reference Designators” dialog, pause the
mouse cursor over each of the DA_Converter ICs to see that the Ref Designators
have been changed.
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38. Close the “Renumber Reference Designators” dialog.

39. In Expedition PCB, select Setup > Project Integration.
Note: The Project Integration dialog now indicates that back annotation is required. At
this time, the new “Ref Designator” values in Expedition have not yet been updated in
DxDesigner.
40. In the Project Integration dialog click the “Additional Options” button.
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41. Enable all of the check boxes in the Additional Options dialog.
Note: The “Create eExp View during Back Annotation” option will create the files
necessary for viewing the PCB layout while you are working in DxDesigner.
42. Click the amber button labeled “Back Annotation Required”.
43. When the Back Annotation indicator becomes green, close the Project Integration
dialog.
44. Close Expedition PCB.
45. In DxDesigner, select the d2a_converter in the schematic and push into it.
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46. Inspect the “Ref Designator” properties on the ICs to ensure they are now IC100 and
IC200.
Exercise 6: eExp View

The eExp View feature in DxDesigner allows you to view the Expedition PCB layout within
the DxDesigner window. The DxDesigner editor and the eExp View window will cross
probe. The eExp View relies on a CCZ file of the PCB layout which is generated by
Expedition PCB.
CAMCAD CC / CCZ files are the ASCII XML intelligent hierarchical files becoming a
standard in the EDA realm. The CC file structure allows for archiving and neutralizing data
from all industry popular Vector Graphics formats, Intelligent PCB Layout formats, and
EDIF Schematic 200 & 300 formats, giving engineers unprecedented access to all the
information in a single ASCII XML format. CCZ files are compressed CC files, using
standard PKZip/Winzip compression.
The advantage of using DxDesigner’s eExp View is that a schematic designer does not
have to consume an Expedition PCB license to view the PCB layout.
Note: The CCZ file is a snapshot of the Expedition PCB layout. Therefore, if a change is
made in Expedition PCB, the changes to the layout will not be seen by eExp View until
back annotation has been performed.
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1. In DxDesigner, select View > eExp View.
Note: The eExp View pane will appear at the bottom of the DxDesigner window.
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2. In the eExp View pane, roll the mouse wheel forward to zoom in on the DA_Converter
parts that you placed on the board.
3. In the eExp View pane, click on IC100.
Note: Selections made in the eExp View pane cross probe to the schematic editor.
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4. In the DxDesigner schematic editor, select IC200.
Note: Selections made in the schematic editor will cross probe to the eExp View pane.
5. In the eExp View pane, right-click and choose Show/Hide Toolbar.
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6. Take some time to experiment and become familiar with the toolbar icons in eExp
View.
7. In DxDesigner, select Window > Close All.
8. If you do not intend to continue on to Chapter 8, close DxDesigner.
End of Chapter 7
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Chapter 8: Documenting DxDesigner

Schematics
DxDesigner has several utilities that support the documentation of a schematic including
Cross Reference, DxPDF, Partlister and Archiver. Cross Reference adds properties to the
schematic that make it easy to trace a net through the schematic. DxPDF produces an
intelligent PDF document from the schematic that has several features that would be
helpful to colleagues and vendors who do not have access to DxDesigner. The Partlister
can create both part lists and other reports that list any of the properties on your schematic
symbols. Lastly, Archiver saves a copy of all of the relevant project files to a location of
your choice.
In this chapter you will learn how to use each of the above utilities and you will become
familiar with their optional configurations.
Exercise 1: Cross Referencing

The Cross Reference utility annotates properties to on-sheet and off-sheet pins as well as
to hierarchical blocks in order to help designers trace nets throughout the schematic.
Cross reference properties are especially helpful to designers who are working with a
printed copy of the schematic.
In this exercise you will annotate the systemdesign schematic with cross reference
information. Nets that have Link symbols will be cross referenced. Additionally,
hierarchical blocks will be annotated with a SHEET property that report which schematic
sheets reside below the block.
Cross Reference Settings

Cross Reference requires that all schematic sheets are closed prior to running the cross
referencing operation. This is because Cross Reference annotates a schematic in two
phases: the “record” phase and the “place” phase. During the “record” phase, Cross
Reference traverses the schematic to determine what cross references will be written.
During the “place” phase, Cross Reference writes the annotations to the components in the
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schematic. Therefore, Cross Reference has to ensure that no changes occur in the
schematic between the record and place phases.
All settings for Cross Reference are contained in scout.ini file. The scout.ini file is an ASCII
text file that is copied into the project directory when Cross Reference is run or the settings
are modified. In the steps below, you will modify the settings for Cross Reference using a
dialog, but it is worthwhile to understand that these settings could also be configured using
a text editor.
2. If any schematics are open, close all schematic sheets by selecting Window > Close
All.
3. Select Tools > Cross Reference to launch the Cross Reference dialog.
Note: The “Top Level Block” is set to systemdesign. Cross Reference is one of the
utilities that only operate on Boards and not the Blocks section. If you selected the
drop-down menu, you would only see the Boards that are associated with this project.
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4. In the Introduction page of the Cross Reference dialog, select “Modify Cross
Reference Settings” and click Next.
Note: If you had already run Cross Reference on your schematic, it would be
important to FIRST use the “Remove Cross References Using Existing Settings”
option before you make any changes to your Cross Reference settings. If you failed
to remove pre-existing cross references, you may find that you have old cross
references cluttering your schematic.
5. Click Next again to display the “Cross References Options” page.
“record”
command
“place”
comman
August 15, 2012 Page 184 of 207

Note: The cross reference property will be named XREF. The Format Entry option is
configured such that the XREF property is written in the format of a page number
followed by a vertical and horizontal zone name (e.g., 2-C5).
The several pin symbols shown are pre-configured to be cross referenced. Each pin
symbol has two entries. The entry without the Annotation options will create a “record”
command in the scout.ini file. The entry with the Annotation options will create a
“place” command in the scout.ini. If you add a new pin symbol to the scout.ini file it is
vital that you create both “record” and “place” commands.
The hier_in.1 pin has been left out of the scout.ini file. In the following steps you will
add the required two rows in order to have Scout cross reference the hier_in.1 pin
symbols.
6. Right click anywhere in the Record and Place Options area and choose New Row.
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8. In the new row, configure a “record” command by entering the following options:
a. Block: Any
b. Selection Type: Symbol Name
c. Selection Qualifier: hier_in.1
d. Right click in the Options area again and choose New Row.
e. In the new row, configure a “place” command by entering the following options:
i. Block: Any
ii. Selection Type: Symbol Name
iii. Selection Qualifier: hier_in.1
iv. Annotation Point X: -0.30
v. Annotation Point Y: -0.10
vi. Text Origin: Middle Right
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9. Change all cells under the “Block Type” column to Any.
Note: The Block Type allows you to specify that Scout must find a symbol that
matches both the name in the scout.ini file and the specified block type (where the
Block Type can be Composite, Module, Primitive, Annotate or Pin). The Any option
eliminates this added level of filtering, making it easier for Scout to annotate the
symbols that you intend to be annotated.
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10. Click Next.
Note: The Direct Reference Options page configures cross reference properties that
can be added to hierarchical components. In this case, “directref0” is configured to put
a property named SHEET onto any hierarchical (composite) symbol. The format of
the SHEET property will be the range of page numbers that are below the hierarchical
block.
11. Click Next to advance to the Sheet Options dialog.
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12. On the Sheet Options dialog, the names for the horizontal and vertical zones are
incorrect. For the dsheet.1 symbol that you are using, the horizontal zones are
numbers and the vertical zones are letters. Use the cut/paste commands to swap the
zone names so they appear as shown below.
13. Change the Zones Order Horizontal to Right To Left.
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14. Change the Zones Order Vertical to Bottom To Top.
Note: The settings for the sheet are being configured globally. Thus, any sheet border
in your library would use these settings. The librarian who creates the sheet borders
should be consistent in the way the zones are named.
Note: The D-size sheet border you are using is divided into 8 horizontal zones and 4
vertical zones. Therefore, the vertical and horizontal distances between zones need
to be adjusted.
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15. Change the “Distance Between Zones” to 4.25 and 5.75, X and Y zone sizes,
respectively. The zone distances should appear as shown below.
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16. Click Next and then Finish to save the changes to the scout.ini file in your project
directory. Below is an excerpt of the scout.ini file showing the edits you made to the
sheet options.
Note: In the scout.ini file the pipe ( | ) character is a comment character. All text to the
right of the pipe character is ignored by Scout.
17. Select Tools > Cross Reference again.
Note: Remember that all schematic sheets need to be closed when you run Scout.
18. Select the “Generate Cross References Using Existing Settings” option and click
Finish to execute the cross referencing operation.
Note: When Cross Reference has completed, the Output pane will report: “Finished
scout.exe”.
19. Open the systemdesign schematic.
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20. Double-click the ARRANDALE_CPU symbol to inspect the properties.
Note: The SHEET property should be a range of 7 sheets. Depending on how you
created your schematic, you may find that the exact SHEET numbers differ from the
screenshots below. The key thing for this exercise is that there are 7 sheets recorded
by the SHEET property on the ARRANDALE_CPU block. The symbol now has a
SHEET property with a value of 11-17.
21. Push into the d2a_converter block.
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22. Zoom in on the CLK input pin and make note of the new XREF property.
Note: Here again, the sheet numbers may differ from the examples shown in the
screenshots. The key point is that the cross referencing is correct regardless of the
sheet numbers that Scout assigned.
23. Return to the systemdesign schematic and click on the CHANNEL_OUT block. Notice
that the SHEET property on this block matches the XREF you saw on the CLK signal.
August 15, 2012 Page 194 of 207

24. Push into the CHANNEL_OUT block and find the CLK signal pin.
Note: XREF properties can be moved manually, but the best approach would be to
configure both your pin symbols and the scout.ini file such that the XREF property is
created in a location that makes it easy to read.
25. Zoom out to confirm that the zone coordinates that you saw in the d2a_converter
schematic are accurate.
Note: The zone coordinates are based on the position of the pin to which the XREF is
attached. So the zones referenced in your schematic may differ from the screenshots
shown above.
26. If you find the Output pane reporting any “Duplicate IDs” errors (Error 1296), run
Tools > DxDesigner Diagnostics and click the “Fix all errors” link.
Exercise 2: DxPDF
The DxPDF utility allows you to communicate effectively through an advanced PDF
document which can be opened and viewed using the free Adobe Reader. By generating
an intelligent PDF file, you can send a single file to anyone, anywhere in the world, and
provide them with the ability to perform a complete design review using Adobe Reader.
The PDF file created by DxPDF not only contains the graphical data of the main schematic,
but it also contains hierarchical data.
The PDF file can also include net and part information with symbol names and a complete
list of property names and values assigned to those symbols. This functionality allows you
to easily locate nets or parts using advanced search features. These advanced features
include net name hyperlinks that allow you to easily trace a net throughout the schematic.
Attributes can be reviewed by placing the cursor over a part, clicking the left mouse button
and selecting the pop-up with the list of attributes for the part.
August 15, 2012 Page 195 of 207

1. Select File > Export > PDF…
2. In the Range section of the DxPDF dialog, select Block and choose systemdesign
from the drop-down list.
Note: The Project range option will export all boards and all blocks to the PDF file. If
you choose this option, the PDF file will have duplicate sheets because some sheets
appear under both the Project tree and the Blocks tree. Typically, you will want to
choose the Block option so you can export only the board to the PDF file.
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3. In the Options section of the DxPDF dialog, enable only the “Start PDF Reader After
Generation” option.
4. Click OK to execute the PDF file generation. The PDF file will open and appear as
shown below.
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The PDF file is stored in the project directory (the same location where you find the
.prj file).
The Bookmarks pane on the left lists each of the sheets in the schematic. The
bookmarks are arranged in a tree according to the hierarchical structure of the
schematic.
5. In the Bookmarks pane, click on the ARRANDALE_CPU Sheet 1 bookmark. Notice
the viewing pane displays the sheet that you selected.
6. Click in the graphical pane of the PDF document.
7. Use the Page Down key to move to the other sheets in the ARRANDALE_CPU
schematic.
Note: Clicking in the graphical pane of the PDF file puts the focus of the Page
Up/Page Down keys on the individual sheets.
8. Close the PDF file.
9. In DxDesigner, Launch DxPDF again by choosing File > Export > PDF.
10. Again, select the systemdesign block.
11. Enable the “Add popup menu on components” and “Visible Component/Net
Hyperlinks” options.
12. Click OK to generate a new PDF file.
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13. In the viewing pane of the PDF file, click on the ARRANDALE_CPU block and select
Push Schematic.
14. In sheet 1 of the ARRANDALE_CPU, click some of the components and choose
Properties.
Note: A popup window appears which displays the properties of the selected part. In
this way, the DxPDF output behaves like a view-only version of DxDesigner.
15. In Adobe Reader, select Edit > Find and enter 6.8pF in the search field. Press Enter
to execute the search. Adobe Reader will navigate to the first 6.8pF capacitor that if
finds.
August 15, 2012 Page 199 of 207

16. In Adobe Reader, click the Find Next button to search for the other 6.8pF capacitor in
the schematic.
17. Close Adobe Reader.
Exercise 3: Partlister
The Partlister generates reports that tabulate symbol properties. This is typically used for
Bill of Materials (BOM) reports, but depending on the properties on your symbols, you can
use Partlister to generate a wide range of helpful reports.
1. Select Tools > Partlister.
The “Configuration file” listed in this dialog is where all of the part list settings will be
stored. Your design environment could have several different .ipl files to allow you to
produce a variety of reports: BOMs, cost reports, component height reports, etc. The
partlister is limited only to the properties on the instantiated components on your
schematic.
2. Confirm that the Scope is set to Board and that the “Output format” is set to “Text
File.”
August 15, 2012 Page 200 of 207

3. Click the Columns tab.
The Columns tab lists the columns that will appear in the part list. Additionally, this tab
provides controls for configuring the format of each of the columns. Below you will add
a new column to the report.
4. Above the list of properties, click the New icon .
August 15, 2012 Page 201 of 207

5. Rename the new column to Value.
6. Configure the settings for the Value property as shown below.
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7. Click OK to generate the part list. Below is an excerpt of the report that will be
generated.
Some designers prefer not to have the reference designators compressed as shown
above. Thus, where you see “R76-R78” on line 20, it may be preferable to see
“R76,R77,R78”. Below you will re-configure the Ref Designator column to list each
reference designator.
8. Close the part list file.
9. Open the Partlister (Tools > Partlister) and activate the Columns tab.
August 15, 2012 Page 203 of 207

10. In the list of Columns, select “Ref Designator” and set the Display Mode to “Full.”
11. Click OK to generate a new part list. You will now see that row 4 has many reference
designators listed explicitly.
12. After you have reviewed the report, close it.

August 15, 2012 Page 204 of 207
Exercise 4: Archiving Projects

DxArchiver is a utility that will store your project in a directory of your choice. Additionally,
DxArchiver can create a PDF file of your schematic and/or compress the archive.
1. Select Tools > Archiver to launch DxArchiver.

2. Ensure the “Target directory” is set to ..\ARCH
3. Ensure the “Compress using zip format” option is enabled.
4. Click Next > to proceed to the next page of DxArchiver.

The Additional Files page allows you to add non-project files and folders to be
included in the archive. In this exercise we will not add any additional files.
5. Click Finish to create the archive of your project.
August 15, 2012 Page 205 of 207

6. Close DxArchiver upon completion.
7. Use a file browser to navigate to the \DxWDIR\DxTUTORIAL\ARCH directory and

inspect the archive that was created. A .zip file and a manifest.xml file will reside in the
archive directory.
Note: The zip file name contains a time stamp, so the exact name of your zipped
archive will differ from the one shown in the screenshot above.
8. Close DxDesigner.
End of Chapter 8
August 15, 2012 Page 206 of 207
Congratulations! You have completed the

DxDesigner Tutorial!
August 15, 2012 Page 207 of 207

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AppNote MG579468

DxDesigner Tutorial for the Expedition PCB Flow

By: DxDesigner Customer Support

Exercise 2: Setting the WDIR and DxTutorial Variables .......................................................... 8

Set Up Rules for Copying ........................................................................................................................................................ 20

Chapter 2: Navigating in DxDesigner......................................................................... 22

August 15, 2012 Page 1 of 207

Creating Nets Using the Right Mouse Button .......................................................................................................................... 83

Exercise 7: Naming Nets ....................................................................................................... 86

Exercise 8: Modifying Properties ........................................................................................... 91

Exercise 9: Working with Busses........................................................................................... 94

August 15, 2012 Page 2 of 207

Exercise 3: Using a Hierarchical Block ................................................................................ 117

Exercise 2: DxPDF ............................................................................................................. 195

August 15, 2012 Page 3 of 207

Additional AppNotes, TechNotes, movies, and documentation can be found on SupportNet.

August 15, 2012 Page 4 of 207

Chapter 1: Setting up the Design Data

August 15, 2012 Page 5 of 207

 Installed Expedition PCB

Design Data Overview

\DxConfig \DxTUT_Lib \DxTUT_Proj \DxTUT_Sample

Checking For Pre-Existing DxWDIR Folder

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To check where your current WDIR variable is pointing, do the following:

Backup Pre-existing DxWDIR Folder

Copy DxWDIR Tutorial Data to Local Location

Get Design Data from SupportNet

August 15, 2012 Page 7 of 207

1. Download the DxDesigner tutorial data.

Exercise 2: Setting the WDIR and DxTutorial Variables

August 15, 2012 Page 8 of 207

2. Create a user variable called DxTUTORIAL to point to the DxTUTORIAL folder as

Exercise 3: Setting Up DxDataBook

1. Ensure that DxDesigner is closed.

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The SampleLib DSN will

August 15, 2012 Page 10 of 207

Exercise 4: Opening a Project

1. In Windows Explorer, navigate to ${DxTUTORIAL}\DxTUT_Proj.

August 15, 2012 Page 11 of 207

Exercise 5: Project and User Settings

${DxTUTORIAL}\DxTUT_Proj\DxTutorial.prj). The DxDesigner.xml file is located in the

August 15, 2012 Page 12 of 207

August 15, 2012 Page 13 of 207

o Partitioning a Sheet into Zones in the DxDesigner User’s Guide

DxDataBook: Points to a DxDataBook configuration file (.dbc) which is explained

Sheet Numbering: Specifies which sheet numbering scheme is used.

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A portion of the template used in this tutorial

August 15, 2012 Page 15 of 207

Set Up Units and the Grid

1. In DxDesigner, select Setup > Settings > Schematic Editor.

August 15, 2012 Page 16 of 207

4. Verify that the Grid Interval Markings box is checked.

Set Up the DxDesigner Navigator

August 15, 2012 Page 17 of 207

Set Up Default Sheet Size

August 15, 2012 Page 18 of 207

6. Click Apply to save the settings.

August 15, 2012 Page 19 of 207

Set Up Rules for Copying

a. Net names can be copied verbatim.

b. Unique net names can be automatically assigned to the copied nets.