=========================================================================

* HDL Synthesis *
=========================================================================
Synthesizing Unit <alu_4bit>.
Related source file is "D:/14/alu/alu_4bit.vhd".
Found 4-bit 8-to-1 multiplexer for signal <result>.
Found 4-bit subtractor for signal <result$addsub0000>.
Found 4-bit comparator greater for signal <result$cmp_gt0000> created at line
54.
Found 4-bit xor2 for signal <result$xor0000> created at line 69.
Found 5-bit adder for signal <temp$add0000> created at line 50.
Summary:
inferred 2 Adder/Subtractor(s).
inferred 1 Comparator(s).
inferred 4 Multiplexer(s).
Unit <alu_4bit> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic
operations in this design can share the same physical resources for reduced device
utilization. For improved clock frequency you may try to disable resource sharing.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 2
4-bit subtractor : 1
5-bit adder : 1
# Comparators : 1
4-bit comparator greater : 1
# Multiplexers : 1
4-bit 8-to-1 multiplexer : 1
# Xors : 1
4-bit xor2 : 1

Advanced HDL Synthesis *

=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 2
4-bit subtractor : 1
5-bit adder : 1
# Comparators : 1
4-bit comparator greater : 1
# Multiplexers : 1
4-bit 8-to-1 multiplexer : 1
# Xors : 1
4-bit xor2 : 1

=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s400pq208-5
Number of Slices: 16 out of 3584 0%
Number of 4 input LUTs: 31 out of 7168 0%
Number of IOs: 16
Number of bonded IOBs: 16 out of 141 11%