With effect from academic year 2013-2014

12EI252CV

STRUCTURED DIGITAL SYSTEM DESIGN

Instruction : 3 Periods/Week Sessional Marks : 25
Tutorial : 1 Period/Week End Examination : 75 Marks
Credits :3 Duration : 3 Hours

UNIT-I
Introduction, Concepts of digital design, the logic operators,
Hardware Aspects related to asserted and not-asserted
conditions, Mechanical switches for signal sources, Concept
of inverter, General Implementation procedures, Arithmetic
circuits, comparators, multiplexers, Code converters.

UNIT-II
Wired logic, Practical aspects of Wired logic and Bus-oriented
Structures, Tristate Bus Systems, Practical aspects related
to Combinational Logic Design, Fan-in Fan-out, Propagation
Delay.

UNIT-III
Introduction Sequential Machine Design, The need for
sequential Circuits, Basic Architectural Distinctions between
Sequential machines, Fundamentals of Sequential Machine
operation, clock and Oscillators, The design of a Clocked
Flip-Flop, Flip-Flop conversion from one type to another,
Practical clocking Aspects Concerning Flip-Flops, Timing and
Triggering Considerations, Clock Skew. .

UNIT-IV
Introduction Sequential Analysis and Design, The State
Diagram, Analysis of Synchronous Sequential Circuits, A
Synchronous Analysis Process, Approaches to the Design of
Synchronous Sequential Finite State machines, Design steps
For Traditional Synchronous sequential circuits, State
Reduction, Minimizing the next door Decoders with JK or T
Flip-Flop, Output Decoder Design.

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 With effect from academic year 2013-2014

UNIT-V
Counters, Design of Single Mode Counters, Design of
Specialized Multi-mode Counters, Ripple Counters, Shift
Register, Shift Registers and Memory.

UNIT-VI
Introduction Multi-Input System controller design, System
Controllers, Controller Design Phases and System
Documentation, Defining the purpose and Role of the system,
.Defininq the Basic Operational Characteristic of the system,
The contro.lling Systems and the controlled system, Timing
and Frequency considerations, FUnctional Partition detailed
. Flow Diagram Development,System Controller 'state
Specification(MDS diagram Generation).

··-UNIT.;.vn
Synchronizing -two Syste.ms and choosing Controller
.: Architecture. The State Assignment, The next state decoder,
Next State Decoder Maps, The output decoder, Clock
. Frequency Determination, Power Supply requirements, Control
and Display,' Concepts relatedto the use of tonditional
Outputs.
. ~.. .','.

, UNIT~VIII
.Introduction, Using MSI decoder in System Controllers, Using
'MSLMultiplexers in System Controllers, System Controllers
wtth more Complexity Indirect Addressed Multiplexers
'~cortfijgurati6n, Read Only Memories~ ROM's, PROM's and
.Applications, Using a PROMfor Random Logic, Proqrarnrned
l:.;og.ic9\rrays, Applications of PLA's'and FPLA's.· , '.-

.( ~'..
. '':. 8;. ,'.(
~.
:. "
j;'

1. _::. ~:"n':f:'~£Jineering Approach to Digital Design, William~I

.Fletcher, Prentice Hall of India Pvt. Ltd. rst Edition, 1997.
2:.:\.·~'~-li'{Jndamentalsof digital logic with verilog design Stephen
~. BrO-~Q)!'- Tata McGraw Hill Publications, 2nd Editiof1, 2007 .
',',',: . .

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 With effect from academic year 201a-:-2~j.4
REFERENCES:
.'" "' ••. I·r •

1. Digital'Systems Testing & Testable Design - Hi'roo'

Abramovlu, Melvin A. Breuer and Arthur D.' Friedman - JaTc6'
Book~\:,Wjley, 1994. ("
I 2. Switching & Finite Automata Theory Z.Kohavi, Prentice Hall
, of India Pvt. Ltd, 2nd Edition, 2008.
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