Full Duplex UART

XC3Sxx D-Board

APPLIED DIGITAL MICROSYSTEMS PVT LTD

D-216, ANSA INDUSTRIAL ESTATE, SAKI VIHAR ROAD,
ANDHERI EAST, MUMBAI 400 072.
Tel: (91-22-)28520817, 56924483/4
Email: admltd@mtnl.net.in
 RS232 UART Implementation
TKBase is a VLSI/µP design laboratory training board aimed at enabling
engineering students to learn complete µP to VLSI technology from startup single
chip microcontroller to a complex embedded FPGA platform.

The TKB2S daughter board and an ADM’s LG320/LGLite form a complete

integrated SOC - embedded design environment. It is built for real time
engineering inside a programmable physical hardware design space. You'll be
able to probe, analyze and debug your circuit just like an actual prototype. And
because the implementation is performed on a low cost Xilinx FPGA, you can
update your design quickly and many times over without incurring cost or time
penalties.

Introduction – RS232 Serial Protocol

This application note illustrates the use of VHDL in the design and verification of
a digital UART (Universal Asynchronous Receiver & Transmitter).

The UART consists of two independent HDL modules. One module implements
the transmitter, while the other module implements the receiver. UART
communication is very cheap with single wire for each direction (plus ground
wire). It is asynchronous because no clock signal is transmitted.

UART Transmitter

1. Convert from parallel to serial.

2. Add start and stop delineators (bits).
3. Add parity bit

The diagram above shows the expected waveform from the UART when using
the common 8N1 format. 8N1 signifies 8 Data bits, No Parity and 1 Stop Bit. The
RS-232 line, when idle is in the Mark State (Logic 1). A transmission starts with a
start bit which is (Logic 0). Then each bit is sent down the line, one at a time. The
LSB (Least Significant Bit) is sent first. The stop bit marks the end of
transmission. Receiver checks to make sure it is ‘1’. The stop bit separates one
word from the start bit of the next word.
Each bit has fixed time duration determined by the transmission rate. Example: a
9600 bps (bits per second) UART will have a 1/9600 s or about 104.16 µs bit
width.

The data sent using this method, is said to be framed. That is the data is framed
between a Start and Stop Bit. Should the Stop Bit be received as Logic 0, then a
framing error will occur. This is common, when both sides are communicating at
different speeds.

The above diagram is only relevant for the signal immediately at the UART. RS-
232 logic levels uses +3 to +25 volts to signify a "Space" (Logic 0) and -3 to -25
volts for a "Mark" (logic 1). Any voltage in between these regions (ie between +3
and -3 Volts) is undefined. Therefore this signal is put through a "RS-232 Level
Converter". TKBASE has on board MAX-232 device. It includes a Charge Pump,
which generates +10V and -10V from a single 5v supply.

UART Receiver

1. Convert from serial to parallel.

2. Remove start and stop delineators (bits).
3. Check and remove parity bit

On an oscilloscope, an RS232 waveform looks inverted from the actual data

values transmitted.
VHDL UART Entity

Let us start the design by first describing the entity for the TKBASE board. The
inputs to the design being the 100KHz clock, the transmit and the receive pins.
To make our design easy for trouble shooting using a logic analyzer, we would
be using the Header1 and Header3 to make the presentation meaningful.

Receiver ready

The first thing we have to do is to ensure that we are not in middle of a reception.
The easiest way to do this is to check for idle state, which means that the serin
input pin has to stay high for a minimum of 10 bit time (icount = 0x6D). The
process P2 which checks for this idle state also flags the rin (ready input) flag.
Timing the Receiver

Once the receiver is out of idle state, this means that it has received the start bit.
We have to immediately start the internal timer to extract data from the pulse
stream. To ensure that we are able to present the information correctly we also
create marker pulses. This marker pulses identifies the exact position in
timescale where we sample the data. This marker and the data values can be
captured on the logic analyzer for easy verification.

Extracting serial information

Once the idclk markers are in place, we can use idclk itself to sample the data
and using shift logic convert serial data to parallel data. Please note that we
receive the LSB first and we are able to extract the 8 bit idata successfully.
The transmit module

The easy way to check if we have received the character correctly is to either
push the data on Header3 or view it on the LED’s. The other method is to
implement transmitter and transmit the data back to the PC immediately.

We will do both the job , so that we can also view the received data on both
TKBASE as well as HyperTerminal.

We now are aware that the receive timing and transmit timing pulses (bit time)
are the same. Hence the next module gets ready for data transmission.

The process P5 flags that the transmitter is ready by setting rout bit. We now
start a new counter ocount to time transmits frames. Please note that we are
now using odclk at the beginning of the bit time, instead of mid position used in
idclk.
Conclusion:

The complete cycle for receiving and transmitting a byte of serial data takes about 1mSec
and a single bit time of 100µSec, and hence best seen using a real time Logic analyzer
like LG320/LGLite. These inbuilt VHDL hardware triggers bits (rin, rout) allow you to
isolate the particular bus traffic you’re interested in, and enables you to instantly see the
content of every message transmitted over the serial bus in your acquisition.

While there are many benefits in transitioning from parallel to serial buses in embedded
systems design, there are also a number of challenges the design engineer faces. With
traditional test and measurement tools like scope’s, it’s much more difficult to trigger on
the event you’re looking for, it can be nearly impossible to tell what information is
present by just looking at the analog signal and it’s an extremely time consuming and
error prone process to have to manually decode a long period of bus activity to diagnose
problems. The LG320/LGLite changes everything. With its powerful trigger, clocking,
and search capabilities today’s design engineers can solve embedded system design
issues with exceptional confidence and efficiency.