CAD for VLSI Design - I

Lecture 20
V. Kamakoti and Shankar Balachandran
 Overview of this Lecture
• Why should we write efficient HDL
code?
• Verilog code to be synthesizable
– efficiently synthesizable
• A HDL specialist
– Circuit runs in back of the mind while
coding
 HDL Vs C
• First assignment
– C program in Verilog :-)
• The challenge for a professor
– Brain has to think concurrently
– Brain is sequential
– The conversion is the challenge
• Understand the parallelism
– Carry Look Ahead Adder
 Efficiency
• What is a good HDL model?
– Synthesizable?
– Efficiently synthesizable?
– What does it mean?
• Power optimized
• Area optimized
• Timing optimized
– Synthesis Problem is NP-Complete
• Every circuit has its own identity
– Varied application domains
• Tool is not human
 Efficiency
• Means “Write Good HDL code”
• The only human interface
• If bad, nothing could be done
• It is the basis of any successful
optimizations in the future
• “you should see the evolving circuit
behind every line of verilog you add”
– Else - life is hell
 Objective
• reg [2:0] myvar;
• Initial
• begin
• for (myvar = 0; myvar < 8; myvar=myvar+1)
• #5 a = a + b;
• #5 $finish;
• end
• Question: When will simulation end?
– Answer: 45 units
 Objective
• always @(posedge clock or reset)
if (reset) b = 0;
else b = a;

a b

clock

reset
 Objective
• always @(posedge clock or posedge reset)
if (reset) b = 0;
else b = a;

a b

clock

reset
 Objective
• always @(posedge clock)
if (reset) b = 0;
else b = a;
 Objective
• always @(posedge clock)
if (reset) b = 0;
else b = a;

0 1

a
mux b
0

reset
clock
 Objective
• always @(posedge reset or posedge clock or
posedge A)
if (reset) c = 1;
else if (clock) c = 0;
else c = d;
 Objective
• always @(posedge reset or posedge clock or posedge A)
if (reset) c = 1;
else if (clock) c = 0;
else c = d;

reset

D set C

clear
A

clock
 Objective
• always @(posedge A)
if (reset) c = 1;
else if (clock) c = 0;
else c = d;
 Objective
• always @(posedge A)
if (reset) c = 1;
else if (clock) c = 0;
else c = d;

Reset + ~clock*D C

A
 Objective
• always @(A)
• if (E)
B = A + D;
 Objective
• always @(A or D)
• if (E)
B = A + D;
 Objective
• always @(E or A or D)
• if (E)
B = A + D;

What is the circuit - assuming E, A

and D are one bit and B is two bits.
 Objective
• always @(E or A or D)
• if (E)
B = A + D;

D A
B[0]
Full adder Latch

B[1]
E Latch
Questions and Answers

Thank You