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Analysis of GDI Logic for Minimum Energy Optimal

Supply Voltage
Kishore Sanapala1, Sakthivel R2
School of Electronics Engineering
VIT University
Vellore, India,
kishore.technova@gmail.com1; rsakthivel@vit.ac.in2

Abstract— As technology advances towards the deep sub-micron § VGS  VT ·


regime, energy consumption of digital circuits is becoming more I Sub I 0 exp¨
¨
¸
¸
nVth (1)
serious. Supply voltage (VDD) scaling is the effective knob to achieve © ¹
minimum energy consumption. This paper aims at obtaining the
minimum energy optimal VDD for the design of Gate Diffusion Input and I 0 μ 0 C ox W (n  1)Vth 2
L
(GDI) logic circuits. A 10 transistor (10T) GDI based full adder
circuit is designed for analyzing the performance of GDI logic to Where
obtain optimal VDD. Extensive simulations were performed using VT Threshold voltage
different supply voltages ranging from 100mV to 1V using the Vth Thermal voltage ( KT q =26mV)
cadence 45nm CMOS process technology. The simulations have
VGS Gate to Source voltage
shown that the operation of GDI based design at optimal VDD of
0.4V, lead to energy savings of more than 69% in comparison with
n sub threshold slope factor
the strong inversion counterparts. The expressions for energy using W/L Effective channel width to the length ratio
GDI logic have also been presented. μ0 zero bias mobility
Cdepletion depletion capacitance
Keywords— Energy;Full Adder;GDI; Supply Voltage; Coxide oxide capacitance
Gate Diffusion Input (GDI) [6, 7] is one of the popular
I. INTRODUCTION logic approaches for the design of area and energy efficient
In the recent times, minimizing the energy Consumption of digital circuits, where complex digital logic circuitry and
digital circuits is becoming the key point of interest among the many Boolean functions can be realized with minimum
scientific communities. This is because of the shrinking in the transistor count in comparison to the CMOS [8], PTL [9] and
technology node according to Moore’s law [1] and increase in TG [10] logics. But the GDI logic lags in providing the full
the need for energy scavenging systems. Some of the swing output. This reducing swing sometimes results in
applications of these systems include wearable electronics, intermediate output swing (neither logic ‘0’ nor logic ‘1’).
wireless sensor nodes, biomedical devices/networks, smart This intermediate output logic swing problem may lead to
grids and portable electronic devices. Supply voltage scaling short-circuit paths, which increases the energy consumption of
down to 0.5V has been the good approach for minimizing the
the circuit while operating at ultra low voltage regime (less
energy consumption in the digital circuits.
than 0.5V). However, buffers can be used at the output to
The 1st idea to design low power circuits in the weak reduce the effect of low output swings but this, in turn may
inversion region was developed by Dr. Eric Vittoz in the lead to increase the area and switching power. To reduce the
1970’s [2]. This idea made a great impact in the design of energy consumption of the GDI circuits due to intermediate
many micro integrated circuits and systems for applications logic swing issue, there is a need to determine the optimum
such as medical and battery powered electronics. Another supply voltage (VDD) point for minimum energy consumption.
earlier work which derives the minimum supply voltage for
CMOS digital circuit operation was presented in [3]. In [4], This paper presents the performance analysis of Gate
the optimum values of the supply voltage (VDD) and threshold Diffusion Input (GDI) logic with the 1-bit full adder circuit
voltage (VT) to achieve minimum energy in CMOS circuits designed for minimum energy consumption by fixing the
was obtained by examining the energy and performance optimal VDD point. The rest of the paper is organized as
contours from the CMOS characterization circuit. follows. The GDI based full adder circuit with the analysis of
In weak inversion/subthreshold region of operation, the optimum VDD for minimum energy is presented in section II.
channel is not inverted and the flow of current in the channel Some conclusions were made in section III.
is through the diffusion of charge carriers from the source to
the drain. The basic expression which models the subthreshold II. OPTIMAL VDD ANALYSIS
current is given in (1) [5].
This section evaluates the performance metrics: power,
delay, and energy of GDI logic for obtaining optimal VDD

978-1-5386-1716-8/17/$31.00 ©2017 IEEE


point. As the arithmetic operations play a crucial role in most B. Analysis for Minimum Energy Optimal VDD
of the computing applications. One of the fundamental Extensive simulations have been done to obtain the
arithmetic units is 1-bit full adder circuit [11]. Therefore, we optimal VDD point for the designed full adder circuit (figure 1)
have designed a GDI based 1-bit full adder circuit using 45nm at supply voltages ranging from 0 to 1V using cadence 45nm
CMOS process technology to build intuition about optimal CMOS process technology. Since the applications involved
VDD. using the subthreshold/near threshold circuit designs require
very low clocking frequencies, the operating frequency of the
A. Design of GDI based Full Adder Circuit designed 10T GDI full adder circuit is fixed at 20 kHz.
As GDI technique takes the advantage of implementing Figure 2, shows the performance analysis of the GDI based
complex logic gates using only two transistors [6], the GDI full adder circuit. It clearly depicts, that the optimal VDD point
based full adder circuit requires only 10 transistors as shown lies between 0.4V and 0.45V which is clearly indicated with
in figure 1. It consists of three different logic gates: XOR, the blue rounded circle. At the optimal VDD point, the energy
XNOR, and Multiplexor (MUX). Two multiplexors are consumption of the designed full adder circuit is found to be
needed at the output. MUX-1 along with XOR logic is used to 1.5aJ. The power and delay values at the optimum point are
generate the output sum, whereas the MUX-2 along with found to be 8.74pW and 0.175μs respectively. It should be
XNOR logic used to generate the carry output (Cout). Since noted that the energy consumption metric of the adder design
only one MUX is involved in the carry propagation path, the calculated at different supply voltages is the average energy
propagation delay is minimal for this circuit. The sizing of the consumed per switching operation.
transistors is optimized for low energy metric [12]. The layout
design of the full adder circuit is shown in figure 2. It occupies
an area of only 4.2μm2 with optimum transistor sizing.
GDI XOR GDI MUX-1
b

Inverter2 Cin
a
Sum

GDI MUX-2
b Cin
Inverter1

GDI XNOR

Cout

Fig. 1. Design of Full Adder circuit using GDI logic

Fig. 3. Performance analysis of the GDI based full adder circuit. The point
with circle indicates the optimal VDD operation point of the adder.

From figure 3, it can be observed that the energy metric


tends to increase at a higher rate below optimal point (0.4V).
This is due to the exponential increase in the delay with supply
voltage scaling. The simulations have shown that the
operation of GDI based design at optimal VDD, lead to energy
savings of more than 69% in comparison with the strong
inversion counterparts.
Considering the worst case scenario that the GDI logic
output results in the voltage drop of VT, the expressions for
dynamic energy (EDYN), leakage energy (ELeak) and the total
energy (ET) can be modeled as in (2),(3), (4) respectively.
Fig. 2. Layout Design of Full Adder circuit using GDI logic
E DYN Ceff VDD 2
(2)
E Leak I Leak VDD TD [11] Partha B, Bijoy K, Sovan G and Vinay K. Performance Analysis of a
Low-Power High Speed Hybrid 1-bit Full Adder Circuit. IEEE
Transactions on VLSI, 2015, 1-8.
I Leak VDD TD
[12] M. Nabavi, F. Ramezankhani and M. Shams, "Optimum pMOS-to-
nMOS Width Ratio for Efficient Subthreshold CMOS Circuits," IEEE
V  VS
I 0 exp§¨ DD ·V T (3) Transactions on Electron Devices, vol. 63, no. 3, pp. 916-924, 2016.
© nVth ¸¹ DD D

ET E DYN  E Leak

§C V 2  VDD  VS
¨ eff DD I 0 exp( )VDD TD ·¸ (4)
© nVth ¹
The parameters ILeak is the leakage current, TD is the
critical path delay of the circuit and VS is the voltage across
the load capacitance of the GDI gate. In [6], the analytical
solution for VS is illustrated in detail.

III. CONCLUSION
This work has shown the effect of supply voltage scaling
on the energy metric of GDI logic. The obtained power, delay
and energy metrics from the simulations of the GDI based full
adder circuit at different supply voltages ranging from 0 to 1V
gives the intuition about the effect of V DD scaling limits for
45nm CMOS process technology. From the performance
analysis of GDI based adder circuit; the optimal VDD point for
minimum energy is evaluated which leads to energy savings of
more than 69% in comparison with the strong inversion
counterparts. The results of this work are helpful in the design
of area efficient digital logic circuits for computing
applications which require ultra low energy with moderate
performance.

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