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Supply Voltage
Kishore Sanapala1, Sakthivel R2
School of Electronics Engineering
VIT University
Vellore, India,
kishore.technova@gmail.com1; rsakthivel@vit.ac.in2
Inverter2 Cin
a
Sum
GDI MUX-2
b Cin
Inverter1
GDI XNOR
Cout
Fig. 3. Performance analysis of the GDI based full adder circuit. The point
with circle indicates the optimal VDD operation point of the adder.
ET E DYN E Leak
§C V 2 VDD VS
¨ eff DD I 0 exp( )VDD TD ·¸ (4)
© nVth ¹
The parameters ILeak is the leakage current, TD is the
critical path delay of the circuit and VS is the voltage across
the load capacitance of the GDI gate. In [6], the analytical
solution for VS is illustrated in detail.
III. CONCLUSION
This work has shown the effect of supply voltage scaling
on the energy metric of GDI logic. The obtained power, delay
and energy metrics from the simulations of the GDI based full
adder circuit at different supply voltages ranging from 0 to 1V
gives the intuition about the effect of V DD scaling limits for
45nm CMOS process technology. From the performance
analysis of GDI based adder circuit; the optimal VDD point for
minimum energy is evaluated which leads to energy savings of
more than 69% in comparison with the strong inversion
counterparts. The results of this work are helpful in the design
of area efficient digital logic circuits for computing
applications which require ultra low energy with moderate
performance.
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