A LABORATORY MANUAL FOR

DIGITAL LOGIC
AND
EMBEDDED SYSTEMS
 A MANUAL FOR THE
DIGITAL LOGIC LABORATORY
WITH
AN INTRODUCTION TO

EMBEDDED SYSTEMS
USING THE

PROGRAMMABLE DIGITAL LOGIC PROCESSOR

2
 Copyright 2006 - Robot Crafters, LLC

TABLE OF CONTENTS

Preface 4
Introduction 5
Preliminaries 6
Basic Digital Logic
1. Implementing a Boolean Expression 8
2. Using K-Maps to Simplify a Combinational Circuit 10
3. Designing with Decoders 11
4. Designing with Multiplexers 13
5. Building a D-Type Flip-Flop 15
6. A Bit Sequence Recognizer 17
7. A Serial to Parallel Shift Register 20
8. Magnitude Comparator 22
9. Finite State Machine 24
10. Ring Counter 26
Computer Architecture
11. Register Transfers 29
12. Arithmetic Logic Unit 30
13. Memory Unit 33
14. Control Unit - The Fetch/Execute Cycle 35
15. Executing Assembly Language Instructions 37
Embedded Systems Design
16. Introducing the BasicX-24 Microcontroller 39
17. Analog to Digital (A/D) Converter: Light Meter 40
18. Tone Generator: DTMF 42
19. Pulse Width Modulation: Driving a Servo 43
20. Serial Communications - RS232 45
Appendices
Appendix A: The Very Simple Computer (VSC) 47
Appendix B: Electronics Fundamentals 53
Appendix C: PDLP Circuit Diagram 62
Appendic D: PDLP Software 63

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 Preface

This laboratory manual was written to fill a need in the undergraduate computer science curriculum.
While many CS programs are moving away from computer hardware, a greater understanding of
embedded systems and other "appliances" with a computational component.

A natural location for introducing embedded systems in the undergraduate core is the Computer
Architecture and/or Digital Logic course. Specifically we can integrate a study of microcontrollers into the
Digital Logic Laboratory. In the early experiments a microcontroller can be used to generate input signals
for the student circuit and to evaluate student circuit outputs. In later labs microcontrollers can be used as
simple examples of the von Neumann architecture. In advanced laboratory experiments the students can
design and program their own embedded systems applications.

Every effort has been made to limit the complexity and cost of the electronics used in this experiments.
The ICs used are all TTL 7400 series ICs. While considered largely obsolete, these ICs are preferred for
teaching since they provide the same functionality as CMOS ICs but are less expensive and much more
rugged.

The microcontroller selected for the Programmable Digital Logic Processor (PDLP) and for the student
projects is the BasicX-24. This microcontroller is programmable in a version of the Basic programming
language (similar to VB). The BX-24 has an extensive library of supporting functions and sample
software. Finally this microcontroller has 16 I/O pins including 8 built-in analog to digital (ADC)
converters, making it one of the most versatile software programmable microcontrollers available.

4
 Introduction

This laboratory exercise manual is designed to support an undergraduate course in digital logic. The
Programmable Digital Logic Processor (PDLP) can be assembled on a separate breadboard using the
circuit diagram provided in Appendix D and
common TTL ICs. The BasicX-24
microcontroller, its documentation and
Compiler/IDE can be obtained from Net-
Media's online store at www.basicx.com.

If you prefer to use the circuit board

version of the PDLP, you can obtain a bare
circuit board, a kit of parts or a fully
assembled PDLP from Robot Crafters,
LLC at their online store located at
www.robotcrafters.com. This Web site
also provides all PDLP documentation,
including this laboratory manual, as well as
documentation for advanced projects in
digital electronics and embedded systems.

The purpose of the PDLP is to provide

a convenient source of input for up to 8
digit binary values for both
combinational and sequential circuit.
The PDLP can be programmed to
access and evaluate the output of
student circuits. The instructor and the
student can program the PDLP to
support each laboratory exercise with
minimal hardware complexity.

PDLP programs can be written in the

Basic programming language on a
standard PC. These programs are then
compiled and transferred to the PDLP
through a serial cable. For an
introductory digital logic laboratory, the
programs are loaded onto the PDLP by
the lab instructor before each
laboratory exercise.

In later laboratory exercises and/or in

advanced a second course, the
students design hardware circuits and
program the PDLP (BasicX
microcontroller) creating their own
PDLP Breadboard Version
embedded systems applications.

There are five versions of the PDLP software provided to support this course. A brief description of each
is provided below. The complete source codes for these programs are also provided in Appendix D and
in electronic form on the accompanying CD.
PDLP Program Version 01 - Basic Combinational Circuits
PDLP Program Version 02 - Basic Sequential Circuits
PDLP Program Version 03 - Building and Driving Flip Flops
PDLP Program Version 04 - Driving Seven Segment Displays
PDLP Program Version 05 - Testing Advanced Parallel I/O Circuits
5
 Preliminaries

Before attempting any of the projects, the student should become familiar with the tools and components
used in the electronics laboratory. While not particularly dangerous, electrical equipment such as power
supplies and components such as integrated circuits can be easily damaged by improper handling.
Please review the information provided below. Be sure to ask questions.

Breadboards - The breadboard has many clips made of metal that run underneath the board, behind the
holes in the top of the board. The metal strips are laid out as shown below. These clips run under rows
of holes in the top of the board, which makes it easy to connect components together to build circuits.

bottom view top view

To use the breadboard, the wires of components are placed in the holes. The holes are arranged so that
they will hold the components in place and make an electrical connection between two or more wires, so
you must be sure to press the wires into the holes far enough to make a positive contact. When properly
inserted, a wire should be held tightly by the metal clip.

Groups of holes are electrically connected to one of the metal clips running underneath the board.
Each wire clip forms an electrically common point or node. A node is a point in a circuit where two or
more components are connected. Electrical connections between different components are formed by
putting their wires into holes of a common node. On the breadboard, shown above there are many
groups of five holes laid out in rows on either side of a center gap (gutter) running the length of the board.
The long top and bottom row of holes each form a single node and are usually used for power supply and
ground connections. On some boards the underlying long clips run the entire length of the board. On
others they run only halfway (ask your instructor to verify which type of board you have).

Integrated circuits (ICs) are placed on the

breadboard with a row of legs (pins) on each side
of the gutter. For standard DIP (dual inline pin) ICs
the pins are pressed into the rows of holes closest
to the gutter. For wide body DIP ICs one or two
rows of holes must be skipped.

Important: When removing standard ICs from a breadboard, care must be taken to prevent injury to your
fingers and damage to the pins. If you do not have an IC removal tool you should loosen the ICs by
carefully applying pressure sideways until the left-hand or right hand row of pins slip out of the metal clips.
DO NOT ATTEMPT TO PULL THE ICs OUT OF THE BREADBOARD.

With practice you will learn how to rock the ICs to loosen the pins. Wide body ICs are more difficult to
remove. Their pins can be loosened by gently prying one end and then the other with a small screwdriver
placed into the gutter and under each end of the IC.

6
We will be using a number of ICs containing common digital logic gates. The pins on ICs are numbered
as shown. The internal layout of these gate inside the ICs are shown below (you are looking down

through the tops of the IC. The "dimple" on the left side of each corresponds to either an indentation or a
small circle over pin 1. Each IC requires connection to power (Vcc) pin 14 and ground (GND) pin 7.
Warning! - Other ICs may have their power and ground other pins. Be sure to check the datasheet for
each IC BEFORE wiring your circuits.

 The 7404 is called a Hex Inverter, because it contains 6 inverters or NOT gates.
 The 7408 is called a Quad, Two-input AND, because it contains 4 AND gates each with two inputs.
 The 7432 is called a Quad, Two-input OR, because it contains 4 OR gates each with two inputs.

The ICs you will be using in this laboratory may include additional letters in their labels between the 74
and the rest of the ID numbers or placed at the end of the ID number. The 74 means that the IC is a
member of the 7400 or TTL (transistor-transistor logic) family. These ICs are the oldest and require the
most power to operate. They are also the most durable, which is why we are using them in the
laboratory. The 4000 series of ICs are members of the CMOS (capacitive-coupled metal oxide
semiconductor) family of ICs, which use less power but can be more easily damaged by static electricity.
Sometimes the 7400 series IC includes additional letters in the ID number, which have the following
meanings:
L - Low power, very slow
H - High speed
S - Schottky
LS - Low Power Schottky
AS - Advanced Schottky
ALS - Advanced Low Power Schottky
F - Fast (faster than normal Schottky, similar to AS)
HC - High speed CMOS, similar to LS
AC - Advanced CMOS, between S and F
AHC - Adv. High-Speed CMOS, 3 times as fast as HC
FC - Fast CMOS, performance similar to F

When you insert ICs into the breadboard leave 4 or 5

columns of holes between ICs. Choose one of the long
rows at the top as your +5V (Vcc) line and one of the long
rows on the bottom as your ground (GND) line. Connect
each Vcc pin to the +5V line and each GND pin to the
ground line. In order to become familiar with the operation
of these ICs you may want to assemble a simple test circuit
for the gates in each IC by connecting the gate outputs to
the positive (long) lead of the LED and connecting +5V or
ground to the gate inputs to input 1 and 0 respectively to the
gates. Verify the functions of the NOT, OR and AND gates
in this manner.

7
 Digital Logic Lab 01 - Implementing a Boolean Expression

Name ____________________________________________________________________________

In this laboratory experiment you will build a digital circuit that implements a boolean expression, using
simple logic gates.

Background - A boolean expression has a truth-value of either TRUE or FALSE. We can create digital
circuits that correspond to boolean expressions in which a positive (Vcc) voltage represents TRUE and a
zero voltage represents FALSE. This is called positive logic and is the most common representation for
combinational circuits. In a negative logic circuit, Vcc represents FALSE and zero volts represents TRUE.

Step 1: Since you are a successful college student, you undoubtedly developed good study habits when
you were younger. Study rules at your home probably included something like the following:

(1) Bedtime is 10:00 p.m. on school nights.

(2) Homework must be completed before any playing. (school night or not).

Based on these rules we can make the following statement.

Statement: If it's before10:00 p.m. or it's not a school night, and your homework is finished, then you can
play computer games.

Convert this statement into its equivalent boolean expression F(X,Y,Z), where

X = It's a school night.

Y = Homework is finished.
Z = It's before 10:00 p.m.
F(X,Y,Z) = You can play computer games.

F(X,Y,Z) =

Make sure that F( ) returns TRUE only if the homework is finished and it's before 10:00 p.m. when it's a
school night.

Step 2: Sketch the equivalent digital circuit for this Boolean expression.

8
Step 3: Fill in the middle column of the table on the right to show X Y Z F(X,Y,Z) Your Circuit
the intended value of F(X,Y,Z) for each truth-value of the variables
X, Y and Z. 0 0 0

Step 4: Implement your circuit using the simple logic gates, NOT, 0 0 1
AND, and OR. Be sure to connect power and ground to each IC.
0 1 0
Step 5: Connect your circuit input (X, Y and Z) to the bit-pattern 0 1 1
generator of the Programmable Digital Logic Processor (PDLP). Be
sure that the PDLP is programmed for combinational circuits 1 0 0
(Program 01).
1 0 1

Step 6: Cycle through the possible truth values as you complete 1 1 0

the truth table on the right.
1 1 1
Step 7: Verify that your circuit matches the expected output for the
boolean expression.

Questions:

1. How do you enforce precedence (order of execution) of binary

operators in a boolean expression?

_____________________________________________________

_____________________________________________________

2. How do you enforce precedence of (order of execution) of logic

gates in a digital circuit?

_____________________________________________________

_____________________________________________________

3. Sketch equivalent circuits for these two boolean expressions.

a. G(X,Y,Z) = X . (Y + Z)

b. H(X,Y,Z) = X .Y + Z

4. DeMorgan's Theorem states that (X.Y)' = X' + Y'. Explain why this theorem is important to the design
of digital circuits.

____________________________________________________________________________________

____________________________________________________________________________________

9
____________________________________________________________________________________

10
 Digital Logic Lab 02 - Using Karnaugh Maps to Simplify Circuits

Name ____________________________________________________________________________

In this laboratory experiment you will simplify a boolean expression using a Karnaugh Map and build a
minimal digital circuit that implements it.

Step 1: Determine how many logic gates would be needed to directly implement the following boolean
expression as a digital circuit:

F(A,B,C) = ABC’ + AB’ + A’BC + ABC + A’B’C’

# of AND gates = _____, # of OR gates = _____, # of NOT gates = _____, Total = _____.

Step 2: Complete the middle column of the truth table below, for this expression.

Step 3: Use a Karnaugh Map to simplify this expression:

BC
A
Step 4: Write the simplified version of the expression for 00 01 11 10
the boolean expression F(A,B,C) below:
0

F(A,B,C) = 1

Step 5: Sketch the corresponding digital circuit for this simplified boolean expression.

A B C A B C F(A,B,C) Your Circuit

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0
Step 6: Implement your simplified digital circuit and test it 1 1 1
using the PDLP to generate all possible inputs for A, B and C.
Complete the right-hand column of the truth table for the
output of your circuit.

Question 1 - Did your circuit match the original expression for all input bit patterns? ____________

Question 2 - How many logic gates are required to implement this boolean expression?

# of AND gates = _____, # of OR gates = _____, # of NOT gates = _____, Total = _____.
Question 3 - How many three-variable boolean expressions with unique outputs are possible? _______

Question 4 - Can there be more than one minimal boolean exp. for the same function? __________.

11
 Digital Logic Lab 03 - Designing with Decoders

Name ______________________________________________________________________________

In this laboratory experiment you will build a single-bit, full-adder using a 74138 decoder and a 7420 dual
4-input NAND gate integrated circuit. The 74138 has an active-low output so you will be using negative
logic in your circuit design.

Background - The 74138 is a 3-to-8 decoder in which one of 8

output lines (O0..O7) is set low (L) as determined by the input select
lines (A0,A1,A2) where A0 is the least-significant bit (LSB) of these
three select lines.

The truth table below shows the response for each possible line
74138
select bit-pattern. Note that for the chip to operate, the pins labeled
E1 and E2 must be grounded and the pin labeled E 3 must be set to
Vcc.

The X values in this table represent "don't care" states for the IC
inputs. The L and H values represent Low and High outputs. It is up
to the user to determine the truth-value to be associated with these
values.

Bi Ai Cin S Cout

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

12
Note that all outputs are High except for the output selected by the input bit pattern. For the input bit
pattern the H corresponds to 1 and L to 0.

Step 1: Complete the truth table on the right for a single-bit full adder. Show the outputs of the sum (S)
and the carry-out (Cout) for each of the eight settings of the input A, B and C in (carry-in).

Bi Ai Cin

Full Adder

Cout Si
Step 2: Design a positive-logic (normal) full-adder circuit. That is,
assume that the 3-to-8 decoder is an active high device. Sketch and
label your circuit below.

A0 0
A1 1
A2 1-to-8 2
Decoder 3
4
(active high) 5
6
7

Step 3: As stated earlier the 74138 provides an active low output

(negative logic). This means that the selected output line is low while the
other seven output lines are high (Vcc). For this reason we cannot use
OR gates to accumulate the selected outputs for the sum (S) and carry
out (Cout) functions. We could pass each output through a NOT gate to
convert the 74138 to active high, but this would require eight inverters (or
two 7404 ICs). Instead we will replace the OR gates with NAND gates.
Note that NAND gates have a low output only if all inputs are high, therefore they can be used to convert
the negative logic output of the 74138 back to positive logic. Replace the OR gates in your circuit with 4-
input NAND gates provided in the 7420.

Step 4: Implement your circuit using NAND gates rather than OR gates and test it using the PDLP to
verify its proper operation. You should test both the sum (S) and the carry out (C out) for all combinations
of A, B and Cin. Debug your circuit if necessary before continuing.

Step 5: Get with three other students (if available) and join your circuit with other completed full adders in
the lab to make a 4-bit adder circuit as shown below.
B3 A3 Cin B2 A2 Cin B1 A1 Cin B0 A0 Cin
set to 0

Full Adder Full Adder Full Adder Full Adder

Cout S3 Cout S2 Cout S1 Cout S0

13
Step 6: Test the circuit by adding the following 4-bit binary values. (Negative numbers are given in two's
complement notation. Verify results by converting sums back to their base-10 equivalent values.
binary decimal

3 + 2 = 5 0011 + 0010 =

5 + 4 = 9 0101 + 0100 =

7 - 3 = 4 0111 + 1101 =

3 - 5 = -2 0011 + 1011 =

14
 Digital Logic Lab 04 - Designing with Multiplexers

Name ____________________________________________________________________________

In this laboratory experiment you will use an multiplexer to implement a combinational circuit. The IC
chosen for the experiment is the 74151 (an 8-to-1 multiplexer). Using this IC we will design, implement
and verify a 2-bit equality tester.

Background - A complete description of the 74151A integrated circuit is provided in the datasheet
(Appendix C). The information for this IC that is essential to this laboratory is copied below:

74151

Important: You will be designing a 2-bit equality tester using this 8-to-1 multiplexer. The following notes
should be carefully reviewed before beginning your design work.
 Pin 7 (strobe) must be connected to ground (0 volts) in order to enable this chip.
 This circuit has a 4 line input divided into two, 2-bit binary values.
 When the two 2-bit values are equal the circuit should light an LED, otherwise the LED
should remain off.
 The 74151A has three data select lines A, B, and C (pins 11, 10 and 9 respectively)
binary values applied to these three lines will select one of the eight data input lines to be passed
to the output(s).
 The Y output is a positive representation of the selected data line while W is a negated
representation of this value.

15
Step 1: Complete the truth table on the right for the 2-bit equality

Data Line Function

tester. The circuit is to compare the magnitudes of two 2-bit binary

Expected Output
values P (p1p0) and Q (q1q0). The expected output is 1 P=Q and 0

Actual Output
otherwise.

Step 2: The Data Select pins of the 74151 select one of the 8 Data
Input lines to be presented to the Output pin. We assign the Data P Q
Select Lines in the following manner C->p1, B->p0, and A->q1. The p1 p0 q1 q0
value for q0 depends on which of the 8 Data Input lines have been
selected. Determine the wiring for each of the eight data lines to 0 0 0 0
implement the equality tester. 0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
A
B 0 1 0 1
C
0 1 1 0
D0 0 1 1 1
D1
74151 OUT
1 0 0 0
D2
D3
1 0 0 1
D4 1 0 1 0
D5 1 0 1 1
D6
D7
1 1 0 0
STROBE
1 1 0 1
1 1 1 0
1 1 1 1

Example: When p1 p0 and q1 are 0 0 and 0 respectively, the expected output will be 1 for q 0=0 and 0 for
q0=1. (This is because we are building an equality tester which should output a 1 when P = Q.) In this
case we want the opposite of q0 presented to the output therefore we would connect the line representing
q0 to pin 4 of the 74151 through an inverter.

Step 3: Implement your circuit on a breadboard using the 74151 and an inverter (7404). Provide the
output LED on your breadboard.

Step 4: Connect your circuit to an appropriate input data source (4 bit binary values 0000 through 1111).

Step 5: Step through all possible input patterns and record your circuits Actual Output in the table above.

Step 6: Verify the operation of your circuit. Describe any unexpected results or problems encountered
during this experiment.

Comments: _________________________________________________________________________

___________________________________________________________________________________

___________________________________________________________________________________

___________________________________________________________________________________

___________________________________________________________________________________

___________________________________________________________________________________

16
 Digital Logic Lab 05 - Building a D-Type Flip-Flop

Name ____________________________________________________________________________

In this laboratory experiment you will build flip-flops. This project introduces sequential circuits and is the
first circuit for which the output is a function of both the current input and the previous inputs. First we will
build an S-R flip-flop and then modify it to make a D-type flip-flop.

Background - The definition of a sequential circuit is one in

which the output depends on both the input and the current
state of the circuit. The flip-flop is the first sequential circuit we
have seen and is the basis for all sequential circuits we will
study.

The typical representation of an S-R flip-flop uses a pair of

NOR gates. In this laboratory we will use a pair of NAND
gates to build a different version of the S-R flip-flop and then
use additional NAND gates to synchronize the flip-flop's
operation to a clock signal.
7400 - Quad 2-Input NAND
Finally we will construct a D-type flip-flop, which has a single
input. The D-Type flip-flop represents a single bit memory cell.
A B P Q
Step 1: Build the circuit below. Connect outputs P and Q to LEDs.
0 0
A
P
0 1

0 0
Q
B
1 0
Step 2: Use the PDLP to generate input signals for A and B. Complete
the truth table on the right.
0 0
Step 3: Modify your circuit as shown below.
0 1
S
P t=0 t=0 t=1
R S P Q P Q
Clk

Q 1 1
R

Step 4: Use the PDLP to generate Input and Clock signals to 0 1

evaluate this circuit. Complete the excitation table on the right. t=0 is
before clock pulse and t=1 is after the clock pulse.
1 1
Question 1: Do the values of R and S have the same meaning as
they do for a normal S-R flip-flop constructed from NOR gates?
Explain. __________
1 0
____________________________________________________

____________________________________________________ 1 1
Question 2: Which row in the excitation table distinguishes this circuit
from a combinational circuit? Explain.
____________________________________________________________________________________

17
____________________________________________________________________________________

Question 3: The clock signal synchronizes this flip-flop, which means that it prevents a change in the P
and Q values while the values of S and R are being changed. During which part of the clock pulse will
this circuit change (positive going or negative going)?

___________________________

Step 5 - Modify your circuit as shown below to create a D-type flip-flop.

t=0 t=0 t=1
Input
Input P Q P Q
P

0 0 1

Clk Q
0 1 0

1 0 1
Step 6 - Use the PDLP to generate input and clock signals to
evaluate this circuit. complete the excitation table on the right.
1 1 0
Note that the NAND gate connected from the input line to the lower
input NAND gate is being used as an inverter (inputs tied together).

Question 4: Describe the difference in input/output between the standard D-type flip-flop and the NAND-
only flip-flop.

____________________________________________________________________________________

Question 5: During which part of the clock pulse does the input get passed to the output of your flip-flop.

____________________________________________________________________________________

Question 6: Which output of this flip-flop corresponds to the Q output of the standard D-type flip-flop?

____________________________________________________________________________________

Comments: __________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________

18
 Digital Logic Lab 06 - A Bit Sequence Recognizer

Name ____________________________________________________________________________

In this laboratory exercise you will design and implement a sequential circuit that recognizes a particular
bit pattern presented to your circuit as a sequence of bits.

Background - Consider a circuit that can be presented a sequence of binary values (0's and 1's) and
output a 1 when it has received a particular bit sequence. We will refer to this type of circuit as a bit-
stream recognizer.

Output
Sequential
Input
: Circuit

Clock

In general, a sequential circuit is one whose output depends on both its input and its current state. The
state of a sequential circuit is a function of its previous inputs. In contrast, a combinational circuit has an
output that is strictly a function of its current input. So, a sequential circuit is different from a
combinational circuit in the sense that it has a memory.

We can vary the input value(s) to a sequential circuit but we need a way to indicate that a new input is
ready to be read by the circuit. This is called synchronizing the input with the state transitions inside the
sequential circuit. We can synchronize a sequential circuit by using a special input called the clock.
When we are ready for the sequential circuit to read the input we cycle the clock input (from low to high or
from high to low). In our example we will assume that the clock signal is normally low (ground) and will be
momentarily pulsed high (V+) when we want the sequential circuit to read the new input and update its
internal state.

The bit-stream recognizer circuit of this experiment will have a single input line, a clock line and an output
line. You will design a sequential circuit to recognize the bit sequence 1101 (read left to right in order of
presentation). The timing diagram below shows the bit stream 1101 on the input line (red) repeated three
times. Shortly after each bit is presented, the clock is cycled (blue) once. The circuit outputs a zero (0)
value until the fourth bit of sequence is presented and the clock pulse goes high.

1 1 0 1 1 1 0 1 1 1 0 1
input

clock

output

We note that the circuit does not accept overlapping bit streams. That is, the last 1 of the sequence
cannot also be the first 1 of the next sequence. You will design a sequential circuit to recognize the bit
stream 1101 without overlap using D-type flip-flops.

19
Step 1 - Draw a state transition diagram for this bit-stream recognizer using a minimum number of states.
Be sure to account for the non-overlapping of the bit-stream.

Step 2 - Label the states of the diagram above appropriately to represent the output values of the flip-
flops that will be used to build this circuit and then convert the state transition diagram into a state
transition table. Be sure to include a column for the sequential output function.

Step 3 - Extend the table above by including the excitations (necessary inputs) to produce the desired
outputs for D-type flip-flops for each state transition.

Step 4 - Use K-maps to minimize boolean expressions for each flip-flop input and the output function.

Step 5 - Sketch the sequential circuit that is suggested by your state transition table and boolean
expressions.

20
Step 6 - Implement your circuit using D-type flip-flops (you may use the 7474 Dual D-Type Flip-Flop, the
74174 Hex D-Type Flip Flop with Master Reset, or then 74273 Octal D-Type Flip-Flop).

Step 7 - Use the PDLP (Program 05) to create test bit patterns to present to your circuit for evaluation.
Make sure your circuit recognizes the bit pattern 1101 embedded inside any other bit stream. Verify that
your circuit does not recognize overlapping bit streams. For example, test your circuit against the string
11011010. It should output 00010000.

Question 1 - Did you use a flip-flop with a resetting capability? __________ If NO, discuss the problems
of getting the circuit into the proper start state. If YES, discuss the importance of labeling the states such
that the start state is labeled 00.

____________________________________________________________________________________

Question 2 - How did you synchronize your circuit's output? ___________________________________

____________________________________________________________________________________

Question 3 - Did you have to invert the clock pulse (i.e. were your D-type flip-flops edge triggered
negative or positive?) Discuss.
____________________________________________________________________________________

____________________________________________________________________________________

Question 4 - Sketch the state transition diagram for a bit-stream recognizer for the bit pattern 1101 with
overlap.

Question 5 - How would you need to change your circuit to recognize 1101 with overlap?

____________________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________

21
 Digital Logic Lab 07 - Serial to Parallel Shift Register

Name ____________________________________________________________________________

In this laboratory experiment you will design and build a sequential circuit that accepts a serial data and
outputs a data byte in parallel. This output is used to drive a seven-segment display.

Background - Almost all data that is transmitted over significant distances is converted to serial data
streams and transmitted one bit at a time. In this experiment the PDLP will be used to generate serial
data to drive a 7-segment display. The data will be captured in an 8-bit shift register built from a 74273
octal d-type flip-flop as shown below. The output of the flip-flops will be connected to the seven segments
and decimal point of the display.

"The 74F273 has eight edge-triggered D-type flip-flops with

individual D inputs and Q outputs. The common buffered Clock (CP)
and Master Reset (MR) inputs load and reset (clear) all flip-flops
simultaneously. The register is fully edge-triggered. The state of each
D input, one setup time before the LOW-to-HIGH clock transition, is
transferred to the corresponding flip-flop’s Q output. All outputs will
be forced LOW independently of Clock or Data inputs by a LOW
voltage level on the MR input. The device is useful for applications
where the true output only is required and the Clock and Master
Reset are common to all storage elements."*

The pinout of the MAN 3910A Seven-Segment Display is shown below. Note
1 14
that there are missing pins on this device, but the numbering is based on a
2 13
standard 14-pin DIP IC.
3
1. Cathode A 8. Cathode D 11
2. Cathode F 9. Cathode D.P. 10
3. Common Anode 10. Cathode C 6 9
4. No Pin 11. Cathode G 7 8
5. No Pin 12. No Pin MAN 3910A
6. No Connection 13. Cathode B
7. Cathode E 14. Common Anode

Step 1: Assemble the circuit shown below using the 74273 and MAN3910A seven-segment display.
Connect a 1K ohm resistor between the common anode and +V. Be sure to connect MR to +V on the to
prevent a reset (or lockup) of the flip-flops.
a

f b
g

e c
dp
d

dp g f e d c b a

serial input D Q D Q D Q D Q D Q D Q D Q D Q

clock

Be sure
that the PDLP is loaded with Program 04. This version of the software generates the bit sequences
*
Fairchild Semiconductor Datasheet - Octal D-Type Flip Flop, Copyright 2000, Fairchild Semiconductor Corporation
DS009511, www.fairchildsemi.com, April 1988, Revised September 2000.

22
needed to drive the chosen seven-segment display with wired as shown in the circuit above. Any
variation in either the display type or wiring of the seven segments will result in an unreadable display.

Step 2: Use Mode A to test and debug this circuit.

Question 1: Did your circuit operate correctly on the first try? __________ If "NO" describe the problem
and how you corrected it.

____________________________________________________________________________________

____________________________________________________________________________________

Step 3: Verify each hexadecimal digit 0 thru F in mode b of the PDLP.

Question 2: Seven segment displays are typically used to display base 10 digits, only. There are a
number of IC's available for driving seven segment displays. Why might you want to build your own
seven-segment display driver circuit?

____________________________________________________________________________________

____________________________________________________________________________________

Step 4: Demonstrate your circuit to the to the lab instructor using Mode C.

Passed _________________________

Review the PDLP software used in this laboratory experiment, as you answer the following questions:

Question 3: Why does the display flicker between each displayed digit?

____________________________________________________________________________________

____________________________________________________________________________________

Question 4: What is the purpose of the D( ) array in the subroutine Seven_Seg_Serial( )?

____________________________________________________________________________________

____________________________________________________________________________________

Question 5: The PDLP user can push 1's and 0's into the serial input of this laboratory circuit. What is the
result of pushing the sequence 10101010 (entered from left to right)? That is, describe the display.

____________________________________________________________________________________

____________________________________________________________________________________

Question 6: What bit-string should be pushed into the serial input to produce a capital "H" on the display?

__ __ __ __ __ __ __ __

Comments: __________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________

23
 Digital Logic Lab 08 - Sequential Magnitude Comparator

In this laboratory experiment you will build a magnitude comparator for two four-bit binary values entered
sequentially. This circuit will use a serial to parallel shift register to read and hold the two values.

Background - Sometimes the classic sequential circuit design methodology (see Lab 06) is not the
preferred approach to design. In this laboratory you are to design and build a circuit that will read in 8 bits
and then output a truth value for one of the three magnitude comparison operators (<, = , or > ). If you
were to attempt to design such a circuit by sketching a state transition diagram you would find that you
needed to consider 28 possible bit patterns.

Instead we will separate the task of reading the two 4-bit binary values from the task of comparing their
magnitudes.

<

Combinational =
Circuit

>

Input Sequential
Circuit

Clock

Following the reading of the bit pattern, the sequential circuit outputs will present all eight bits in parallel to
the combinational circuit. In this experiment you may choose to implement less than (<), equals (=), or
greater than (<), (however, we strongly recommend =).

Step 1 - Choose one o the three magnitude comparison functions and design the combinational circuit
that will output a high value (true) when this function is true and a low value otherwise. Sketch this circuit
below.

24
Step 2 - Use an Octal D-type flip-flop (74273) to design a series to parallel shift register (see Lab 07).
Sketch this portion of the circuit below.

Step 3 - Combine the two circuits from Steps 1 and 2 and implement them.

Step 4 - Use the PDLP to present bit patterns to your circuit using Program 04. You may wish to wire the
eight input flip-flops of the PDLP (right-hand side of the board) in order to verify that your series to parallel
shift register is reading the correct values. List the test patterns you choose for testing and indicate the
result of your magnitude comparator in the table below.

Question 1 - Why do you think we recommended that you implement equals (=) rather than less-than (<)
or greater-than (>)?
____________________________________________________________________

____________________________________________________________________________________

Question 2 - Assuming you had a circuit for adding and subtracting binary values, how might you use this
circuit to implement a magnitude comparator? You may want to make a sketch to support your answer.

____________________________________________________________________________________

____________________________________________________________________________________

25
 Digital Logic Lab 09 - Finite State Machine

Name ____________________________________________________________________________

In this laboratory experiment you will design and implement a finite state machine that recognizes binary
encoded values that are multiples of three.

Background - Binary encoded values are composed of 1's and 0's with the rightmost digit representing 1,
the next digit to the left representing 2, the next representing 4 and so on.

25 24 23 22 21 20
32 16 8 4 2 1
0 1 1 0 0 0 = 2410
The value encoded in such a binary string has intrinsic properties that are not a function of the base of the
number. For example, a numeric value that is divisible by 4 (i.e. evenly divisible without a remainder) will
be divisible by 4 whether its represented in base 10, base 2, base 8, base 16 or any other base.

2410 divided by 410 = 610

110002 divided by 1002 = 1102
308 divided by 48 = 68
1816 divided by 416 = 616

Sometimes it is easy to tell if a particular base-2 number is divisible by some value. Any power of 2 is
straightforward since we only have to look at the least significant digits of the binary value. Any binary
number ending in a zero (0) is divisible by two. It is divisible by four if the last two digits are zero (i.e.
divisible by 2 twice).

Other values are not so easy, which brings us to the challenge of this experiment. You are to design and
implement a finite state machine that recognizes (i.e. accepts) any binary encoded value that is evenly
divisible by 3. A few examples of binary numbers that are divisible by three are:

11 110011 1001
110 110011011 100001
1100 100101001 10000001
1001 111100110 1000000001
10101 1010110101 100010001
1111 1111111111 1001001001

After staring at these for a while you should begin to detect some patterns. In particular pairs of ones
separated by an even number of zero's (e.g. 11, 1001, 100001...) and triplets of 1's separated by an odd
number of zero's (10101, 100010001,...). You should also note that a binary number can be decomposed
by extracting such sequences from the number without affecting whether the resulting number is divisible
by 3. For example, the value 1010111 is divisible by three because both 11 and 1010100 are divisible by
3. Try decomposing the value 1111001 to show that this string is not divisible by 3. You can remove any
sub string that is divisible by three without affecting the resulting value, so

1111001 --> 1100001 --> 0000001 or 1111001 --> 11001 --> 10000

neither sequence of decompositions results in a binary encoded value that is divisible by 3.

26
Step 1 - Sketch the state transition diagram of a finite state machine (FSM) that accepts binary encoded
values that are divisible by 3 without remainder. (Hint: This FSM can be defined with 3 states.) Make the
start state an accept state. (For this experiment, we will let the empty string be equivalent to zero.)

Step 2 - Design a sequential circuit to implement your FSM. You may use any applicable IC's. Use the
space provided below to show your excitation table and to minimize your circuit's boolean expressions.

Step 3 - Evaluate your circuit with binary encoded values. You should be able to use the PDLP Program
04 for this experiment. List some of the values and the results below.

___________________ ____ ___________________ ____

___________________ ____ ___________________ ____

___________________ ____ ___________________ ____

___________________ ____ ___________________ ____

___________________ ____ ___________________ ____

Discuss any issues you encountered during this experiment:

____________________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________
27
 Digital Logic Lab 10 - Ring Counter

Name ____________________________________________________________________________

In this laboratory experiment you will build a sequential circuit called a ring counter.

Background - A counter is a sequential circuit that does not have an input other than the clock signal.
The counter "counts" the clock pulses and generates one or more output patterns that are submultiples of
the clock signal. The phase of the output can vary according to the application. One of the most
common application is the generation of the control signals for register transfers of a computer. See
Appendix A - The Very Simple Computer (VSC).

A ring counter is a type of counter that repeats its output pattern as it continues to receive input clock
pulses. A state transition diagram such as the one shown below can be used to represent a ring counter.

start
000

111 001

110 010

101 011

100

The output can be set to high or low for each of the states. To make a divide-by-eight counter we could
set the output to 1 for state 001 and 0 for all the other states. This would produce an output of
100000001000000010000000... We could also let the output be 1 for the first four states and 0 for the
next four to produce 111100001111000011110000... We could also create any other repeating pattern of
eight bits 101001101010011010100110...

We would need a minimum of three flip-flops to implement an eight-state (i.e. 2 3 states) ring counter. In
this experiment you will learn that, while the labeling of states is somewhat arbitrary, it can affect the
complexity of the resulting circuit.

28
Step 1 - Complete the state transition table below for the ring counter shown above using D-type flip-
flops. Include the excitations for the inputs of the three flip-flops needed to produce the transitions.

0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0

Step 2 - Minimize the boolean expressions for the three flip-flop inputs.

Step 3 - Rework the state transition table using the diagram on the right. This ring counter is the same as
the one above except for the order of the state labels.

start
000
0 0 0 0 0 1
100 001
0 0 1 0 1 1
0 1 0 1 1 0
0 1 1 0 1 0
1 0 0 0 0 0 101 011

1 0 1 1 0 0
1 1 0 1 1 1
111 010
1 1 1 1 0 1
Step 4 - Minimize the excitation functions for the 110
flip-flops and compare them with those for the
previous version of the ring counter.

Step 5 - Choose the version of the ring counter with the simplest excitation functions and sketch the
circuit for it below.

29
Step 6 - Implement this circuit and use the PDLP (Program 04) to provide the clock signal. You can also
use the input LEDs of the PDLP to display to outputs of the flip-flops.

Step 7 - Verify that the sequence of state labels matches the sequence of the version of the ring counter
that you implemented.

Question 1 - Which version of the ring count did you choose? ________________________________

Question 2 - Why do you think that the complexities of the two versions are different?

__________________________________________________________________________________

__________________________________________________________________________________

Question 3 - How would you implement the output functions discussed in the background section of this
laboratory?
___________________________________________________________________________

__________________________________________________________________________________

Question 4 - Design and implement a combinational circuit that represents the output function 10100110.

Question 5 - How might a 3-to-8 decoder be used to generate the output functions of an eight-state ring
counter? Hint: See Appendix A.

___________________________________________________________________________________

___________________________________________________________________________________

___________________________________________________________________________________

30
 Digital Logic Lab 11 - Register Transfers

Name ____________________________________________________________________________

In this laboratory experiment you will build a simple data register using D-type flip-flops and tri-state
gates. You will use this register to read and write bit patterns.

Background - A register is a sequence of memory cells connected to a bus (parallel lines of

communication) in a manner that permits both reading and writing on the same lines.

The memory cells are just D-type flip-flops with their outputs
connected to tri-state gates. A tri-state gate is like an
electronic switch, which passes its input to its output when it
is enabled, but generates a high-impedance output (i.e. not
connection) when it is disabled.

The 74244 is an IC that contains eight tri-state gates in

parallel. These are controlled by write enable lines connected
to groups of four gates. These enable lines are active low
and can be banked together.

The 74273 IC is an Octal D-type Flip-Flop with a common

clock line. These two ICs can be combined to create a one-
byte data register as shown on the right.

When the Write Enable line is inactive the outputs of the flip-
flops are blocked from the Bus. A bit-pattern can be
presented to the Bus and the Read Enable line can be
activated. This will load a bit pattern from the bus into the flip-
flops.

When the Write Enable line is active the bit-pattern stored in

the flip-flops is loaded onto the Bus. In this state another register connected to the Bus can Read this bit
pattern. So long as only one data register is writing to the Bus at any one time data can be safely
transferred from one register to another.

Project - Build an eight-bit data register and use the PDLP (Program 01) to present data patterns to your
register. You can use DIP switches or direct wiring to control the Read and Write Enable lines.

Question 1 - Why might it be a good idea to delay the Read Enable signal slightly compared with the
Write enable signal during a registers transfer?

____________________________________________________________________________________

____________________________________________________________________________________

Question 2 - Considering the reduced complexity of a serial transfer compared to a parallel transfer of
data between registers, why do you think that parallel data transfers are preferred in a CPU?

____________________________________________________________________________________

____________________________________________________________________________________

Question 3 - Why is serial data transfer preferred between computers over the Internet?

____________________________________________________________________________________

31
 Digital Logic Lab 12 - Arithmetic Logic Unit

Name ____________________________________________________________________________

In this laboratory experiment you will test a 4-bit ALU to verify and demonstrate its logical and arithmetic
operations. You will also learn the concept of a dual in which each logical function in positive logic has a
corresponding but different function (its dual) in negative logic.

Background - The IC for this experiment is the 74181. The pinout for
this chip is shown below. Note that the A and B inputs and the F
outputs are negative logic. The pins labeled S0 thru S3 are control
lines used to select the function to be performed.

"The 74F181 is a 4-bit high-speed parallel Arithmetic Logic Unit (ALU).

Controlled by the four Function Select inputs (S0–S3) and the Mode
Control input (M), it can perform all the 16 possible logic operations or
16 different arithmetic operations on Active HIGH or Active LOW
operands. The Function Table lists these operations. When the Mode
Control input (M) is HIGH, all internal carries are inhibited and the
device performs logic operations on the individual bits as listed. When
the Mode Control input is LOW, the carries are enabled and the device
performs arithmetic operations on the two 4-bit words.

The A = B output from the device goes HIGH when all four F outputs
are HIGH and can be used to indicate logic equivalence over four bits
when the unit is in the Subtract mode. The A = B output is open
collector and can be wired AND with other A = B outputs to give a comparison for more than four bits. The
A = B signal can also be used with the Cn+4 signal to indicate A > B and A < B."*

The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry
adds a one to each operation. Thus, select code LHHL generates A minus B minus 1 (2s complement
notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is
actually performed by complementary addition (1s complement), a carry out means borrow; thus a carry
is generated when there is no underflow and no carry is generated when there is underflow. As indicated,
this device can be used with either active LOW inputs producing active LOW outputs or with active HIGH
inputs producing active HIGH outputs. For either case the table lists the operations that are performed to
the operands labeled inside the logic symbol.

*
Fairchild Semiconductor Datasheet - 4-Bit Arithmetic Logic Unit, Copyright 1999, Fairchild Semiconductor
Corporation DS009511, www.fairchildsemi.com, April 1988, Revised September 1999.
32
Step 1: Be sure that the PDLP is loaded with Program 05. In this configuration the PDLP has 3 modes.
In Mode A you can run through all 256 possible patterns for an 8-bit value. You will be using these 8 lines
to specify the binary values for the two 4-bit inputs to the ALU. In Mode B you can directly generate any
8-bit pattern across the PDLP output lines. Mode C cycles through the 256 bit patterns automatically.
Review these modes before you design your ALU test circuit.
+5
Step 2: Design a test circuit using the PDLP to be able to test
all functions of the 74181. Using your circuit and the PDLP, you
should be able to evaluate both Logical and Arithmetic Modes 1k Ohm
for the ALU. You should use the PDLP output line (left side) to
out
provide the A and B inputs to the ALU. You may use the PDLP
input line (right side) LEDs to display the F output of the ALU or
you may choose to use discrete LED's on the breadboard.

The four select lines (S) should be controlled with DIP switches wired to +5V and Gnd. Make sure your
circuit for the select lines provides both High (V+) and Low (GND) values to S. Both 5 volts and GND can
be presented to a high-impedance input by using a pull-up resistor as shown above. Sketch a block
diagram of your test circuit below.

Step 3 - Test your circuit in Logic Mode for A+B, A.B, and A+B (Choose a representative set of values for
A and B).

Select Lines A B F

A B Operation F
Step 4 -0Test your
0 0 0 ALU 1on1the
1 indicated
1 Afunctions
.B with the values of A and B specified below. Be sure to
set the mode of the ALU to perform the indicated arithmetic operations (plus with and without carry in).
1 0 0 1 1 1 0 0 A+B
1 1 0 0 1 0 1 0 A'+B
1 1 0 0 1 0 1 0 A+B'
1 1 0 0 1 0 1 0 A
0 1 1 1 0 1 1 1 A plus B (no carry in)
0 1 1 1 0 1 1 1 A plus B (plus carry in)
1 1 1 0 0 1 1 1 A minus B
1 1 1 1 1 1 1 1 A plus B (no carry in) 33

0 0 1 1 0 0 0 0 A plus A . B' (no carry in)

Question 1: What is the difference between Co active and Co inactive in arithmetic mode?

____________________________________________________________________________________

____________________________________________________________________________________

Question 2: Given the function A+B in positive logic, what function does it become in negative logic?

__________________

Question 3: Why is carry in and carry out not important when M=H?

____________________________________________________________________________________

____________________________________________________________________________________

Question 4: What happens when the sum of two values exceeds 15 for the arithmetic plus operation?

____________________________________________________________________________________

____________________________________________________________________________________

Question 5: What happens when A minus B produces a negative value (i.e. when B>A)?

____________________________________________________________________________________

____________________________________________________________________________________

Question 6: What do you think the purpose of A . B minus 1 is?

____________________________________________________________________________________

____________________________________________________________________________________

34
 Digital Logic Lab 13 - Memory Unit

Name ____________________________________________________________________________

In this laboratory experiment you will build a Random Access Memory unit for the Very Simple Computer
(VSC) as discussed in Appendix A.

Background - A computer's active memory is called Random Access Memory or RAM. This memory can
be dynamic called DRAM which must be refreshed periodically by scanning to prevent data loss. Static
RAM (SRAM) does not need to be scanned but will hold its data values so long as power is applied to the
memory ICs. SRAM is more expensive than dynamic RAM so it is less frequently used in a standard
computer. We will use SRAM in our experiment because it is easier to control.

Computer memory is often distributed across several ICs so that certain memory blocks on each IC. Also
each word in memory can be distributed across more than one IC. In this experiment we will be building
a 32 word x 8 bit memory using 4 ICs each holding 16 x 4 bits. The 74189 is a 64 bit Random Access
Memory with tri-state outputs. The datasheet provides the following specifications:

"The 74189 is a high-speed 64-bit RAM organized as a 16- word by

4-bit array. Address inputs are buffered to minimize loading and are
fully decoded on-chip. The outputs are 3-STATE and are in the high
impedance state whenever the Chip Select (CS) input is HIGH. The
outputs are active only in the Read mode and the output data is the
complement of the stored data."

This IC has 4 address lines A0 through A3 that give access to one of

16 4-bit words. The data input is provided through pins D0 through D3.
The output is provided through pins O0 through O3 but these values
are inverted with respect to the stored data. This permits the output
to be connected directly to another negative logic circuit without the
need for buffering through OR gates.

Step 1 - Complete the sketch below in which 4 16x4 bit memory ICs are used to construct an 8 x 32 bit
memory unit for the VSC.

A0 D0 D1 D2 D3 A0 D0 D1 D2 D3
A1 A1
A2 A2
A3 A3
CS CS
WE WE
O0 O1 O2 O3 O0 O1 O2 O3

A0 D0 D1 D2 D3 A0 D0 D1 D2 D3
A1 A1
A2 A2
A3 A3
CS CS
WE WE
O0 O1 O2 O3 O0 O1 O2 O3

35
Step 2 - Build an evaluation circuit for a 74189.

Step 3 - Use the PDLP to evaluate the ability to load and store value (4-bit) in the 74189. Load data
values into several memory locations and then read them to verify them. Complete the table below by
indicated the stored and observed values in at least eight different memory locations in the 74189.

Question 1 - Explain how you dealt with the need for a 5 bit address in your circuit for the VSC memory
unit.
____________________________________________________________________________________

____________________________________________________________________________________

Question 2 - How did you deal with the inverted output of the 74189 in your memory unit design?

____________________________________________________________________________________

____________________________________________________________________________________

Question 3 - What feature of the 74189 permits us to connect the output lines to the input lines without
special buffering?

____________________________________________________________________________________

____________________________________________________________________________________

Question 4 - Explain how you converted the IC enable line ~CS and the Read/Write Mode line into a
Read Enable and a Write Enable line as required by the VSC?

____________________________________________________________________________________

____________________________________________________________________________________

Comments___________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________

36
 Digital Logic Lab 14 - Control Unit: The Fetch/Execute Cycle

Name ____________________________________________________________________________

In this laboratory exercise you will design and implement a control unit for the Fetch/Execute Cycle of the
Very Simple Computer. This circuit will generate the read and write enable signals for each of the steps
of the Fetch stage and a single clock cycle for the Execute stage.

Background - For more details on the Very Simple Computer (VSC) read Appendix A. The Fetch/Execute
cycle of a von Neumann architecture computer must perform a number of operations for each instruction
executed. Most of the work is performed during the Fetch stage. This work involves transferring
data/instructions between the various registers of the CPU. The numbered list shown in the figure below
are the register transfers for the VSC.

The program counter (PC) holds the memory address of the next instruction to be executed. The first
step is to load the memory address register (MAR) with this address value. Next the instruction in
memory located at this address (MEM[MAR]) is transferred into the instruction register (IR).

Sometime during the Fetch stage the program counter must be incremented. This is done in register
transfer statement 3 above. The VSC uses direct addressing mode, which means that the memory
address of the data being operating on by the current instruction is contained in the address portion of the
instruction (IR0-4). The 4th register transfer statement moves this address into the MAR in preparation for
reading this data value.

There are two registers (latches) at the input of the arithmetic logic unit (ALU) called LAT1 and LAT2. The
data value referred to by the current instruction is loaded into LAT1 and the value of the accumulator
(ACC) is loaded into LAT2. The ACC holds the value of the previous ALU operation and is often used in
subsequent operations.

Finally the current statement is executed by invoking the EXE en call to the control unit. For more
information on the Execution stage of the Fetch/Execute cycle you may refer to Appendix A and Lab 15.
Once the current instruction has been executed the cycle repeats until interrupted by the HALT
instruction. The control unit of the VSC drives the Fetch/Execute cycle uses a ring counter and a decoder
to generate the various read and write enable signals. The timing diagram on the right above shows the
order of these signals.

37
Step 1 - Sketch a block diagram for the VSC control unit based on a divide-by-eight counter and a 3-to-8
decoder.

Step 2 - Implement the Fetch stage for the Fetch/Execute cycle of the VSC based on your block diagram
using a 74138 3-to-8 decoder. Since the 74138 uses negative logic you will need to invert each enable
line to produce positive logic control signals. Also when combining two outputs of the 74138 you can use
a NAND gate rather than an OR gate.

Step 3 - Connect the output for the following eight enable lines to the input (right-hand side) of the PDLP.

MARRE _______________________
IRRE _______________________
IRWE _______________________
LAT1RE _______________________
LAT2RE _______________________
MEMRE _______________________
MEMWE _______________________
ACCRE _______________________

Step 4 - Use the PDLP (Program 04) to drive your ring counter with clock signals and observe the
corresponding outputs of the 3-to-8 decoder. Use the space above to comment on the validity of your
circuit design.

Question 1 - The read enable and the write enable signals are shown to occur simultaneously. Explain
why this may not be a good idea. (I.e. consider why it may be preferred to let the read enable signal to lag
the write enable signal slightly.)

____________________________________________________________________________________

____________________________________________________________________________________

Question 2 - The PC increment register transfer is performed in the third step of the Fetch stage. Indicate
how early and how late this could be performed.

earliest _________________ latest ____________________

Question 3 - Why is the address of the current instruction transferred into the MAR when some of the
instructions don't use it?
_________________________________________________________________

Question 4 - Why are there so many steps for the Fetch stage and only one step for the Execute stage?

____________________________________________________________________________________

____________________________________________________________________________________

38
 Digital Logic Lab 15 - Executing Assembly Language Instructions

Name ____________________________________________________________________________

In this laboratory experiment you will implement the Execute stage of the Very Simple Computer (VSC)
control unit. This circuit will generate the control signals for the register transfers of the eight instructions
of the VSC.

Background - The Very Simple Computer (VSC) is a rudimentary von Neumann architecture computer
that implements eight instructions. Each of these instructions is implemented using a single register
transfer. Several register transfers are performed during the Fetch stage (see Lab 14) which are the
same for all instructions. As shown below, control unit performs one additional register transfer during the
Execution stage that is specific to the particular instruction being executed.

The VSC uses an 8-bit instruction with a 3-bit opcode and a 5-bit address. The 3-bit opcode defines eight
instructions as shown above. Each instruction that involves the memory unit uses direct addressing so the
address of the data being operated on is in the lower 5-bits of the instruction.

The register transfer expression for each expression is

shown above.

LDA - This instruction loads the accumulator with the value

in LAT1. This simple requires a transfer of the data in LAT1
into ACC without alteration.

STO - Stores the value in ACC into the memory at the

address indicated in the current instruction (i.e. MEM[MAR].)

ADD - Adds the value in MEM[MAR] to the value in ACC and

places the result in ACC.

CMP - Performs a one's complement (i.e. bit wise inverse) of

the value in ACC.

BNN - Branch if not negative change the value in PC to the

address in IR if the value loaded in ACC is not negative.

SHL - Performs a single-bit left shift of the data in ACC.

SHR - Performs an arithmetic right-ship of the data in ACC.

HLT - Stops the Fetch-Execute cycle of the VSC.

As shown on the right above, the control unit for the Execute stage can be implemented using a 3-to-8
decoder. The three bits of the opcode are used as the select lines of the decoder.

39
Step 1 - Build a circuit that represents the Execute stage of the control unit as described above. Use the
74138 3-to-8 decoder for your circuit. You can use LED's for each of the enable lines. Since the 74138 is
negative logic you will need to invert each output line. You will also want to use NAND gates in place of
OR gates and an alternative for the BNN instruction implementation. Sketch your circuit below.

Step 2 - Verify that each register transfer is properly implemented.

LDA _______________________
STO _______________________
ADD _______________________
CMP _______________________
BNN _______________________
SHL _______________________
SHR _______________________
HLT _______________________

Question 1 - How many instructions involve the ACC? __________

Question 2 - How many instructions make use of the address portion of the IR? __________

Question 3 - The VSC uses two's complement arithmetic. How does this affect the implementation of the
branch instruction (BNN - branch if ACC is not negative).

____________________________________________________________________________________

____________________________________________________________________________________

Question 4 - Why do you think that the Halt instruction is implemented by setting the PC to 11111?

____________________________________________________________________________________

____________________________________________________________________________________

Question 5 - How would a programmer of the VSC implement subtraction? That is, which instructions
would be used?

____________________________________________________________________________________

Question 6 - Write a VSC program to implement Booth's multiplication. Use another page or the back of
this sheet.

40
 Digital Logic Lab 16 - Introducing the BasicX-24 Microcontroller

Name ____________________________________________________________________________

In this laboratory experiment you will lean how to program the BasicX-24 microcontroller. This device is
programmed in a version of the Basic programming language. The programs are written on a desktop
computer

Background - We have selected a microprocessor for the PDLP that provides a memory space large
enough to hold significant programs while supporting a large number of I/O control lines. The BasicX-24
includes 32K Bytes of memory for BASIC source code while providing 16 I/O lines. The BasicX-24 also
supports a serial communications port (COM1) with speeds from 2400 baud to 460.8K baud and 300
baud to 19,200 baud on any of its 16 I/O pins (COM3). Eight of the 16 I/O lines include built in analog to
digital (A/D) conversion.

HelloWorld is a simple BasicX program that uses built-in queue and serial port functions to write to the
BasicX Status Window. The program first opens two queues to be used as data buffers for the serial port.
Then it opens the port and attaches the two queues to the port. Finally, it enters a loop in which the string
"Hello, world" is transmitted repeatedly, followed by carriage return/linefeed. A call to the built-in Delay
procedure inserts a one second delay after each string. Follow the steps below as provided by the
Application Note to build and implement your first BX-24 BASIC program:

Step 1 - Start BasicX Program: Start, Programs, BasicX, BasicX Express...

Step 2 - Options menu -- verify that BX-24 is checked.
Step 3 - Download Port -- open the COM port.
Step 4 - Monitor Port -- open the same port as in step (3) above.
Step 5 - Editor button -- press.
Step 6 - The Open - Project File dialog box will pop up. Type HelloWorld as a filename. Program will ask
if you want to create a new file -- hit Yes. This boilerplate code is automatically created in the editor
window:
Sub Main()
End Sub
Step 7 - Project - Chip menu. Verify all boxes in the "IN" columns are checked (this means all input pins
are initialized as input-tristate). Click on OK.
Step 8 - Enter the following code into the Edit Window (or cut and paste):

Sub Main()
Do
Debug.Print "Hello, world"
Call Delay(1.0)
Loop
End Sub
Step 9 - Hit F5 to compile and run. Say "Yes" when compiler asks to save changes.
Step 10 - "Hello, world" will print on screen until stopped by reset button. Debug is necessary.

The output of the BX-24 statement Debug.Print "Hello, world" is sent back to the host PC and will be
displayed in the IDE window. Once you have successfully executed this HelloWorld program, write
another program of your own and test it on the BX-24.

Once you have become familiar with the BX-24 IDE begin reviewing the BX-24 Language Reference
Manual and the System Library to learn the features of the BX-24 BASIC language.

41
 Digital Logic Lab 17 - Analog to Digital (A/D) Converter: Light Meter

Name ____________________________________________________________________________

In this laboratory experiment you will program the PDLP to be a light meter. Your meter will use a photo
resistor as part of a voltage divider to generate analog voltage levels proportional to the amount of light
on the sensor. You will then program the BasicX to convert this voltage level into a two-digit display.

Background - The light meter will use a simple voltage divider network as shown here. The resistance of
the photo resistor changes with changing light level. The resistance drops as the light level increases.
The other resistor of this circuit is a fixed value 10 K ohm resistor. In the circuit shown, if the photo
resistor is at 10 K ohm then the voltage at the mid-point (between the resistors) would be 2.5 volts. We
will connect this point of the circuit to one of the analog to digital input pins of the BX-24 (pin 13 for
example). We will then use the BX-24 to convert this voltage level into a numeric value. The sample
Basic code shown below can be used to perform this conversion.

Option Explicit +5
Public Sub Main()
photoresistor
Dim val As Single
Dim ival as byte out to ADC (pin 13)
Do
Call GetAdc (13,val) 10k Ohm
ival = CByte(100.0*val)
Delay 0.25
Loop

End Sub
The call to Get Adc (13,val) takes the voltage level at pin 13 and converts it into a single-precision floating
point value named val. The next line multiplies this value times 100 and converts it into a Byte sized
integer.
You can use the SerialPort module provided with the BasicX IDE to display this value in a console window
on the desktop computer being used to program your BX-24. Additional information on this process can
be found in the App_Notes of the BX documentation provided with the BX-24 IDE.
You can get access to pin 13 by removing the jumpers and connecting a Breadboard cable to the BX-24
side of the pin header on the PDLP as shown below.

remove jumpers connect cable

pin 13

PDLP Circuit Board Modification

Step 1: Download and Install BasicX IDE from NetMedia Web Page (if not already installed on your
computer). http://www.basicx.com

42
Step 2: Create a New Project. Set the Processor Type to BX-24. Set all Chip pins to IN (tristate).
Step 3: Copy "Hello World" Program from BasicX Documentation (C://Program_Files/BasicX/BX-24
Docs/...) , then compile and test run this program on the PDLP. (Show instructor).
Step 4: Create a New _Project that reads an analog voltage level from pin 13 and displays this value
back to the Desktop console. You will need to download the Serial_Port.bas module and Add it to your
project. You may use the source code below as a guide. (show instructor)

Option Explicit
Public Sub Main()
Dim Tx as string
Dim val As Single
Call OpenSerialPort(1,19200)
Tx = " "
val=0.0
Do
Call GetAdc(13,val)
Call PutL(CLng(1000.0*val))
Call PutLine(Tx)
Loop
End Sub
Step 5: Download a copy of the PDLP_Digits.bas module which contains the low-level functions for
driving the PDLP display.
Step 6: Modify your project to generate a Byte value (00,99) rather than a string value, then split this
value into two digits using integer division (\) and mod functions.
Step 7: Output the two digit values to the seven segment display digits of the PDLP using the Set_Digit( )
function. You can use the left-hand button (with jumper in place) to generate high and low values for
testing. (show instructor)
Step 8: Remove the jumpers, connect a cable to the four BX-24 pins as shown in the preliminary
discussion (actually only one pin will be used in this experiment) and build a voltage divider using the
circuit above as a guide. Be sure that the photo resistor is between pin13 and +5 volt source.
Step 9: Adjust the scaling parameter to make the value being displayed fall between 00 and 90 when the
photo resistor is placed in complete darkness and the brightest available light, respectively.

Question 1. Based on your circuit output values and scaling parameters, what is your estimate of the
range of resistances being generated by the photo resistor?
min ____________ max ____________

Question 2. The photo resistor can be replaced with many other types of sensors that vary resistance as
a function of the level of some measured parameter. Give possible applications for a version of this
device when the photo resistor is replaced with:
a temperature sensor __________________________________________________________________
a fluid level sensor ____________________________________________________________________
a pressure sensor _____________________________________________________________________

Question 3. If the photo resistor and the fixed 10K resistor were interchanged, how would the behavior of
your device be changed?
____________________________________________________________________________________

_____________________________________________________________________________________________

43
 Digital Logic Lab 18 - Tone Generator: DTMF

Name ____________________________________________________________________________

In this laboratory experiment you will design and implement a circuit to generate dual frequency tones
that can be used to dial telephone numbers.

Background - A touch-tone telephone uses a pair of sine waves to represent each number and/or symbol
on the key pad. The frequencies of the tones indicate the row and column of the button being pressed.
As shown below, the there is a low-range frequency and a high-range
frequency. The low range frequencies are 697 Hz, 770 Hz, 852 Hz, 1209 1336 1477
and 941 Hz while the column frequencies are 1209 Hz, 1336 Hz, and
1477 Hz.
697 1
1 2
2 3
3
Once a dial tone has been established these tones can be generated
by pressing the buttons on the key pad or by presenting them to the
phone circuit through the handset mouthpiece. 770 4
4 5
5 6
6

The pair of frequencies (DTMF - dual tone modulation frequency) can

be produced by a built-in function of the BasicX-24 microcontroller. 852 7
7 8
8 9
9
The command freqout( ) can be used to generate a pair of frequencies
as shown in the example code below.
941 #
# 0
0 **
Call FreqOut(Pin, Freq1, Freq2, Duration)

where Pin is the output pin number, Freq 1 and Freq 2 are the frequencies in Hertz and Duration is
duration of the dual tone output in seconds. There is an integer and a floating-point version of this
command. (See System Library for more details.)

Step 1 - Program the BasicX-24 to generate DTMF tones matching each of the buttons of a standard
telephone keypad.

Step 2 - Design a means to enter a sequence of digits into the BasicX-24 on the PDLP.

Step 3 - Load a known telephone number and use a buzzer (or small speaker) to generate audible tones
using your circuit. You can use an LM386 as a general audio amplifier (see the LM386 datasheet for
more information on the audio amp.)

Step 4 - test your DTMF generator by holding the buzzer/speaker output to a telephone mouthpiece as it
generates the tones for a known phone number.

Question 1 - What is the minimum duration for each DTMF tone pair that ensures a successful telephone
call? (You may use the Internet to research this question.)

____________________________________________________________________________________

____________________________________________________________________________________

Question 2 - Why do you think the telephone company chose to use dual frequency tones rather than
single frequency tones to represent the digits of a telephone number?

____________________________________________________________________________________

____________________________________________________________________________________

44
 Digital Logic Lab 19 - Pulse Width Modulation: Driving a Servo

Name ____________________________________________________________________________

In this laboratory exercise you will implement a circuit to drive a standard servo. This circuit can be used
to control a position actuator or drive a hacked servo used as a wheel motor on a desktop robot.

Background - A servo is a device originally designed for remote control (RC) models that converts an
electrical signal into mechanical motion. This motion is used to control steering and throttle settings in RC
model cars and airplanes. The servo is made up of a motor, a gearbox, a variable resistor called a
potentiometer connected to the gearbox and some electronics to drive the motor and sense the value of
the potentiometer.

In order for the servo to operate, a signal must be

applied to the signal wire of the servo input cable. This
signal must be sent repeatedly in order for the servo to
respond appropriately. Typically the servo signal (a
square-ware pulse) is sent to the servo every 5 to 20
milliseconds. These pulses have an amplitude of 4.5 to
5 volts and last for 1 to 2 milliseconds each.

When the pulses are 1.5 milliseconds in duration, the

servo rotates to orient its output shaft in the center
position (angle = 0 deg.). When the pulses are 1.0
milliseconds wide the output shaft rotate to -90 deg
(fully counterclockwise), and when the pulses are 2.0
milliseconds wide the output shaft rotates to +90
degrees (fully clockwise).
We can "hack" servos in be used as drive
motors in small robots. In order to "hack a
server, the potentiometer must be
disconnected from the gearbox so that it does
not rotate as the motor turns the output shaft
(i.e. should not change resistance).

This variable resistor is set near the middle

resistance so that the electronics "thinks" that
the output shaft is near its midpoint of rotation.
Also, the mechanical stops must be removed
so that the output shaft is free to rotate
clockwise or counterclockwise continuously
through multiple rotations. When the pulse
width of the control signal is slightly less than
the pulse width required to center the servo
the output shaft will turn counterclockwise. When the pulse width of the control signal is slightly longer
than the centering pulse width the output shaft will rotate clockwise.

The basicX-24 provides a predefined library function to generate square wave pulses of a specified pulse
width. This command can be used to drive a standard servo. The command is,

pulseout(Pin, PulseWidth, State)

where Pin is the pin number of the basicX-24, PulseWidth is the duration of the pulse in seconds, and the
State is the output level of the pulse. When State=1 the pulse goes high, when State=0 the pulse goes
low.

45
Step 1 - Design a simple test circuit to evaluate the operation of the pulseout( ) command on a standard
servo. This circuit can use the buttons of the PDLP to incrementally increase or decrease the pulse
width.

Step 2 - Use the sample source code below as a template for a PDLP circuit to test the performance of a
hacked servo.

Sub Main()

' test driver for a hacked servo robot

' running servos on I/O pins 11 and 12

dim i as integer

do

for i=0 to 300

Call PulseOut(11, 0.002, 1)
Call Delay(0.02)
next

loop

End Sub

Step 3 - Modify the program from step two to drive the hacked servo near its centering frequency (both >
and < the precise centering frequency).

Question 1 - Why do you think that the servo must be "reminded" of the desired position by resending the
control pulse periodically?

____________________________________________________________________________________

____________________________________________________________________________________

Question 2 - What is the effect of running the hack servo near its centering frequency? _______________

____________________________________________________________________________________

____________________________________________________________________________________

Question 3 - Considering the original application discuss the effects of a much slower response time for a
much faster response time for the servo response.

____________________________________________________________________________________

____________________________________________________________________________________

Question 4 - What is the purpose of the 0.02 second delay in the sample source code above. In other
words, what is the effect of reducing, increasing or removing this delay?

__________________________________________________________________________________

__________________________________________________________________________________

__________________________________________________________________________________

46
 Digital Logic Lab 20 - Serial Communications - RS232

Name ____________________________________________________________________________

In this laboratory experiment you will implement a serial communication interface between the BasicX-24
and your desktop computer.

Background - The RS 232 serial interface is one of the oldest communication protocols defined for
textual communication with a digital computer. The BasicX-24 support serial communication and uses
this interface for downloading compiled programs into the microcontroller.

NetMedia provides software for communication through the serial port as part of their documentation.
The source code serialport.bas is a Basic code module that implements a serial interface with the PC and
can be found in C:\Program Files\BasicX\BX24_Docs\Serial_IO\serialport.bas.

The sample code below can be used with serialport.bas to display values on the PC screen in the BasicX
IDE window. In this example we are reading the value of the ADC pin 13, multiplying the value time 1000
and passing it to the PC through the serial interface.

'----------------------------------------------
Option Explicit
Public Sub Main()

Dim Tx as string
Dim val As Single

Call OpenSerialPort(1,19200)

Tx = " "

Do
Call GetAdc(13,val)
Call PutL(CLng(1000.0*val))
Call PutLine(Tx)
Call Delay(0.1)
Loop

End Sub
'---------------------------------------------

Note that the data in val must be converted to a CLng (character string) before it can be displayed on the
PC screen. The PutLine command forces a carriage return and line feed in the output.

Step 1 - Design a circuit and a BasicX program to read and display an analog value presented to on of
the ADC pins of the BasicX-24 (i.e. pins 13 through 20).

Step 2 - Implement this program on the PDLP and connect it to the PC through the serial port.

Step 3 - Execute this circuit while altering the analog input (the particular application is up to you), and
evaluate the performance of your circuit. Discuss the results in the Comments section provided below:

Comments __________________________________________________________________________

____________________________________________________________________________________

____________________________________________________________________________________

47
 Appendix A
The Very Simple Computer (VSC)

48
 The Very Simple Computer (VSC)

The purpose of the Very Simple Computer (VSC) is to provide a simple description of the von Neumann
architecture and to give the student a designer's perspective on the Central Processing Unit (CPU).
Modeled after a Post-Turing style minimal "complete" language, the VSC provides the simplest possible
computer design in which all computable functions can be represented. It also stands as a point of
departure to discuss the many variations and refinements in modern digital computers.

Features of the VSC include:

8-bit instruction composed of a 3-bit operations code and a 5-bit address.

direct addressing mode
32 word memory unit
direct memory access input/output (I/O) unit
discrete component arithmetic logic unit (ALU)
hardwired control unit
single bus architecture

Obviously the VSC is not a practical computer. Its value is as a conceptual design of a minimal processor
for gaining a better understanding of the organization of computer hardware. In the following section we
will work through all the major design decisions for the VSC instruction set, bus structure, ALU, memory
unit, control unit and I/O unit.

The Instruction Set - The instruction set of the VSC is modeled after a minimal set of instructions that
can be used to build any computable function. Our minimally "complete" language includes the following
eight operations:

Load - load a register with a value from memory

Store - store a value from a register into memory
Add - add a value in memory to the value in a register and put the result in a register
Complement - perform a bit wise (one's) complement of a value in a register
Branch - change the address of the next instruction to be executed based on some condition
Shift Left - shift the bits in a register 1 position to the left with a 0 fill on the least-significant-bit (LSB)
Shift Right - shift the bits in a register 1 position to the right preserving the most-significant-bit (MSB)
Halt - terminate the currently running program and return to I/O mode

We say that these eight operations form a "complete"

language because, with them, we can build any arithmetic
or logical computation. These operations can be
implemented in hardware and encoded with 3 bits in an 8-
bit instruction. This leaves 5 bits to directly address up to
32 words of memory.

VSC Registers - Registers for the VSC include an

instruction register (IR), program counter (PC) to hold the
address of the next instruction to be executed, a memory
address register (MAR), an accumulator (ACC) and two
data registers called latches (LAT1 and LAT2). The eight
operations described above, will be implemented as
transfers of data and instructions between these registers
and memory (MEM) over an 8-bit parallel bus. In hardware
a register is implemented as a set of D-type flip flops and
tri-state gates. The register "reads" or accepts a value by Register Details
clocking the D-type flip-flop and "writes" or outputs a bit
pattern to the bus by enabling the tri-state gates.

49
The functional components of the VSC include an input/output (I/O) unit, an arithmetic/logic unit (ALU),
the memory unit, a control unit and a means mechanism for incrementing the program counter. The block
diagram of the VSC is shown below:

The VSC Bus is an 8-bit parallel

communication path between the registers
and the organization units for both data and
instructions.

The I/O unit can be implemented as a panel of

rocker switches and push buttons to permit the
user to read/write to every byte in the memory
unit, to launch a program and to monitor bus
activity.

The Arithmetic Logic Unit (ALU) implements

the Add, Complement, Shift Left and Shift
Right operations for the VSC. It reads values
from the registers LAT1 and LAT2 and loads
the result of the selected operation into the
Accumulator (ACC).

The Control Unit decodes the operation in the

op-code of the current instruction loaded into
the Instruction Register (IR). It is directly Layout of the Very Simple Computer (VSC)
wired to the ALU, memory unit and other
hardware in the VSC.

The Memory Unit Reads/Writes on the Bus the value in memory at the address specified by the Memory
Address Register (MAR). The address portion of an instruction such as Load or Store is transferred to
the MAR during the Fetch stage of the Fetch/Execute cycle. We review the Fetch/Execute cycle in detail
below.

The Program Counter (PC) holds the memory address of the next instruction to be executed. The value
of the PC is incremented during the Fetch stage but may be changed during the Execute stage of a
Branch instruction.

Register Transfers - Now that we have an overview of the VSC hardware organization we are ready to
implement the instruction set. You may have been told that there is a one-to-one correspondence
between matching language (assembly) instructions and computer hardware operations We are about to
learn that this is not true. While the execution itself can be a single
hardware operation, there are a number of steps that must be completed
(Fetch stage) to prepare for the execution (Execute stage) of each stage.
The good news is, the steps for the Fetch stage are the same for all
instructions. Let's walk through these steps in detail.
Step 1 - At the beginning of the Fetch stage the PC is holding the address
(location in memory) of the next instruction to be executed. Therefore we
need to transfer this address value from the PC to the MAR (memory
address register) in preparation for moving the instruction. Fetch Stage
Step 2 - The instruction in memory at address MAR is transferred into the
IR (instruction register).
Step 3 - Sometime during the Fetch stage we need to increment the PC so we do it now.
Step 4 - Since half of the instructions require memory access we transfer the address portion of the
current instruction into the MAR. (It's easier to do this every time rather than testing to see if its needed).
Step 5 - We transfer the contents of memory at address MAR into a register LAT1.
Step 6 - In anticipation of some ALU instruction we transfer the contents of ACC into LAT2.

50
The arrow in each register transfer expression indicates the direction of the transfer of the data or
instruction. In the next section we see how these transfers are implemented in hardware.

The Timing Circuit - The Fetch/Execute cycle is driven by a timing circuit to generate clock pulses that
activate read enable (RE) and write enable (WE) controls for the registers, the memory unit and the ALU.

We can develop a timing diagram for the fetch/execute cycle by listing the REs and WEs needed to
perform each register transfer. We have included an extra step in our cycle so we can use a standard
divide-by-eight counter to generate the enabling clock pulses. The primary clock pulse generator drives
the divide-by-eight counter. This counter outputs a sequence of values 000 through 111. A decoder (e.g.
a 3-to-8 decoder) can then be used to generate a sequence of enabling pulses as shown below.

Step 7 of this cycle is the execution of the particular register transfer indicated by the op-code of the
current instruction (i.e. the Execute stage). Now we are ready to execute the current instruction. Each of
the eight operations defined as hardware operations can be implemented as register transfers.

The table below shows the chosen 3-bit op-code and the three letter mnemonic for each instruction,
followed by the corresponding register transfer. We note that during the Fetch stage the value in ACC is
transferred to LAT2 and the value in MEM at address MAR is transferred to LAT1. These two operations
are necessary to make it possible to complete some of the instruction register transfers in a single step.

51
 Execute Stage

It is important to note that only one of these instructions will be executed during a Fetch/Execute cycle,
which is determined by the op-code of the instruction in the IR and implemented by the Control Unit.
LDA - Load Accumulator - This instruction is
implemented by activating the read enable line
of the ACC while simultaneously activating the
write enable of LAT1. This is accomplished
within the ALU by a simple unaltered transfer
of the data.
STO - Store Accumulator - This instruction
transfers the value in the ACC into memory at
MEM[MAR].
ADD - Add - The contents of LAT1 and LAT2
are added and the result is placed in the ACC.
CMP - Complement - The value in LAT1 is bit
inversed and passed to the ACC.
BNN - Branch Not Negative - If the most
significant bit of the value in the ACC is a zero
then the address of the IR is loaded into the
PC.
SHL - Shift Left Logical - All the bits of LAT1
are shifted one position higher (to the left) and
a zero is loaded into the LSB. The result is
passed to the ACC.
SHR - Shift Right Arithmetic - All the bits of
LAT1 are shifted one position lower (to the
right) and the value of the old MSB is used as
the new MSB.
HLT - Halt - The instruction that ends the
program.

The Control Unit - The control unit implements the Execute stage of the Fetch/Execute cycle and can be
built from a circuit similar to the one used to implement the Fetch stage. In this case, the control line input
to the 3-to-8 decoder will come from the op-code.

Note: Enable lines in common with those in the fetch circuit

must be connected through OR gates for positive logic or
through NAND gates for negative logic.

52
VSC Assembly - We can define an assembler to write programs for the VSC. This assembler will be
used to help us manually develop machine code (1’s and 0’s) for the VSC. The best way to become
familiar with the VSC assembler is by reviewing a few examples:

Example 1: In our first example we will write a program to

add the values 6 and 3. We will preload these values into
memory labeled X and Y and have the program store the
result in Z.

Note that the assembly language commands are simply the

8 operations we defined for the VSC and their
corresponding op-codes are the 3 high-order bits of each
instruction.

The program is placed in memory with the 1st instruction at

address 0000. Upon completion the VSC should hold the
value 00001001 at memory address 00110.

The program is placed in memory with the first instruction at address 0000. This is called absolute loading
and is the oldest form memory management for programs. Upon completion the VSC should hold the
value 00001001 at memory address 00110.

Lets walk through each line of this program:

1. First the value of X is loaded into the accumulator. This is the value stored in memory (address 0100).

2. The value in ACC is then added to the value at location Y (address 00101) and is held in ACC.

3. The result in ACC is then stored back into MEM (at address 0110).

4. Finally the program stops when HLT is encountered.

Example 2: The next example is a program that

checks an input value X. If X is even then it is divided
by 2 otherwise it is multiplied by 2. The result
replaces X. In this example X=7.

1. Load the value in MEM at X into ACC

2-3. Divide by 2 the Multiply by 2.
4. Store the result in MEM at Y.
5. Load the value in MEM at X into ACC (again).
6. Take the 1's complement of this value
7. Add 1 to make the two's complement
8. Add this value to the value stored at Y
9. If the result is zero (or > 0) branch to label "EVEN"
10. Load the value at X into ACC
11. Multiply this value by 2.
12.

53
 Appendix B
Electronics Fundamentals

54
 Electronics Fundamentals

Direct Current (DC) Basics - The fundamental principles of the movement, restriction and accumulation
of electrons in various materials has been well understood for centuries. However, the development and
refinement of electronic devices and technologies continues. Since we will be using some of these
devices in our digital logic laboratory we will review these principles.

Voltage - The voltage of an electrical power source, V (measured in volts) is the potential for pushing
electrons through a conductor. The voltage of a source can be thought of as an electrical pressure.

Resistance - The resistance to the flow of electrons in a material R (measured in ohms) is the inverse of
conductance (measured in mhos). Generally, metals are good conductors while wood, plastic and rubber
are insulators and other materials such as carbon and metal oxides are poor conductors (also called
resistors). Conductors have low resistance, resistors can have a moderate to high resistance and
insulators have an infinite resistance.

Current - The current, I (measured in amps or amperes) is a measure of the flow of electrons through a
material.

Ohm's Law - The relationship between the resistance R in a

resistor, the voltage, V of an electrical source and the current, I
in a circuit composed of connecting the conductor to the source +
is given by Ohm's Law.
V I R

V  IR -

As indicated by this simple expression we can increase the

current through the resistor by increasing the voltage or by
reducing the resistance.

Power - The battery or other electrical power source expends energy (MKS units of electrical energy are
Joules) to push electrons through a resistor. The power P dissipated by a source V sustaining a current I
in a resistor R (measured in watts or Joules/sec) is given by,
V2
P  IV  I 2 R 
R
An important underlying issue of this expression is the consideration of the maximum power that can be
tolerated by an electrical component. The power generated in an electrical component by the flow of
electrons is dissipated in the form of heat. Commercially produced resistors are rated for a maximum
power dissipation. Typical resistor power
ratings are 1/4 watt, 1/2 watt and 1 watt. Va = V
Higher wattage resistors are produced for
special purposes.

+ R1
Example: Consider a 100 ohm resistor
connected to a 12 volt source in a simple V
circuit. Compute the power generated in Vb = V.R2/(R1+R2)
the resistor. -
2
V
P R2
R
(12) 2
P  1.44 watts Vc = 0
100

Series Circuits - A series circuit is one in which the components are connected end-to-end as shown. The
electrons flowing in this circuit must pass through both resistors so the equivalent resistance of this circuit
is the sum of the two resistors R1 and R2.

Rtot  R1  R2 (series)
55
We can compute the voltage level at any point in this circuit. The voltage V a at any point from the positive
end of the source to the resistor R 1 is equal to the source voltage. There is a voltage drop through this
resistor proportional to the fraction of the total resistance contributed by R 1, so the voltage Vb is given by,

R2
Vb  V
R1  R2

We can test the validity of this expression by varying the values of the resistances R 1 and R2. For
example, as R1 goes to zero the voltage V b goes to V and as R2 goes to zero the voltage V b goes to zero.
This matches our understanding of voltage drops across resistors in a series circuit. We can compute the
power dissipated in each resistor using the current through the circuit and the voltage drop (voltage
difference) between the ends of each resistor.

Example: Assuming that R1=100 ohms, R2=200 ohms and V=6 volts of the series circuit above, compute
the voltage Vb and the power dissipated in each resistor, (P1 for R1 and P2 for R2).

 200   2
Vb  (6)   (6)   4 volts
 100  200   3
Va  Vb  2 22
P1    0.04 watts
R1 100
Vb  Vc  2
42 16
P2   
0.08 watts
R1 200 200
Alternatively, we could compute the power using P  I 2 R and V  IR to find the current I in the
resistors.
V 6
I    0.02 amps
R (100  200)
P1  (0.02) 2 R1  (0.0004)(100)  0.04 watts
P2  (0.0004)(200)  0.08 watts

Parallel Circuits - The components in a parallel circuit are

connected side-by-side as illustrated by the two resistors
in the circuit on the right. The electrons flowing in this
circuit can pass through either R1 or R2 so the total +
resistance to electron flow is less than it would be for
V
either one of the resistors alone. The total resistance of a R1 R2
pair of resistors, R1, R2 connected in parallel is given by, I1 I2
-

1 R1 R2
Rtot  
1 1 R1  R2 (parallel)

R1 R2

The power dissipated by each resistor can be computed using P  V 2 / R where the voltage drop is the
same for each resistor and is equal to the total source voltage. The current in each resistor is inversely
proportional to its resistance and can be determined by Ohm's Law.

Example: Compute the current I 1, I2 in each resistor in a simple parallel circuit as shown above with
R1=100 ohms, R2=500 ohms and V=10 volts.
56
 V 10
I1    0.10 amps
R1 100
V 10
I2    0.02 amps
R2 500

Non-Series/Parallel Circuits - Sometimes a circuit will

contain an arrangement of resistors which cannot be
reduced to combinations of series and parallel
elements. For example, consider the circuit shown
here. Without resistor R3, resistor R2 would be in
series with R4, and resistor R1 would be in series with
R5. Also these two pairs of resistors would be in
parallel with each other. However the presence of R 3
creates a configuration which cannot be considered
either series or parallel.

We cannot use our series/parallel formula to analyze this

circuit. In order to determine the current through the
resistors or the voltage drop across the resistors, we must
make use of Kirchoff's Laws.

In our example let us assume that the source voltage is

10 volts, resistors R1, R2 and R5 are 100 ohms and R3 and
R4 are 200 ohms. In order to analyze this circuit we need
to determine the current through each resistor and/or the
voltage drop across each resistor.

Kirchoff's Current Law - This law states that the total

current entering a node is equal to the total current
leaving the same node.

The figures on the right shows our example circuit with

the node voltages and current in each path labeled. We Kirchoff's Current Law
can use Kirchoff's Current Law to formulate a number of
expressions relating the resistor values and the currents
in the circuit.

Using Kirchoff's Current Law we have

i0 = i1 + i2 (node a)
i2 = i3 + i4 (node b)
i4 + i5 = i0 (node d)

We do not know the actual direction of the current through

R3, however we can simply choose a direction for the
current arbitrarily. Once we have solved for a value for i 3
its sign will tell us if we have chosen the correct direction
for the current in this path of the circuit. We could also
formulate an expression for node c. We will use Kirchoff's
Voltage-Sum Law to formulate the additional expressions Kirchoff's Voltage-Sum Law
needed to solve for the six unknown values i0 through i5.

Kirchoff's Voltage-Sum Law - This law states that the

sum of the voltage drops around any closed loop in a circuit will equal zero.

57
In the right-hand circuit we have defined three closed-loop paths through our circuit. These loops result in
the following expressions in terms of the resistor values, the current through the resistors, and the source
voltage.
i1R1 - i2R2 - i3R3 = 0
i2R2 + i4R4 = -10
i1R1 + i5R5 = -10

Note that we have formulated a set of expressions that include all the essential data defining our circuit.
All resistances and the source voltage are present in at least one of the six expressions formulated using
Kirchoff's Laws. In order to determine the currents we can transform these expressions into a table of
coefficients for a system of linear equations.

i0 i1 i2 i3 i4 i5 =
1 -1 -1 0 0 0 0
0 0 1 -1 -1 0 0
-1 0 0 0 1 1 0
0 0 R2 0 R4 0 -10
0 R1 - R2 - R3 0 0 0
0 R1 0 0 0 R5 -10

Note that the first three rows of our table represent the expressions obtained using Kirchoff's Current Law
while the last three rows represent the expressions obtained using Kirchoff's Voltage-Sum Law. Using
Gauss elimination or some other method for solving systems of linear equations we have,

i0 i1 i2 i3 i4 i5 =
1 0 0 0 0 0 0.08
0 1 0 0 0 0 0.06
0 0 1 0 0 0 0.02
0 0 0 1 0 0 -0.02
0 0 0 0 1 0 0.04
0 0 0 0 0 1 0.04

So,
i0 = 0.08 amps i1 = 0.06 amps
i2 = 0.02 amps i3 = -0.02 amps
i4 = 0.04 amps i5 = 0.04 amps

We can use these current values and the resistance values to determine the voltage drops across each
resistor using Ohm's Law, V=IR. It is important to note that we chose the direction of the current i 3
incorrectly, and as a result, we obtained a negative value for this current, so we need to reverse its
direction. There are a number of excellent solvers for linear systems of equations available online. *

Capacitors - A capacitor is composed of a pair of

conducting plates separated by an insulator.
When a voltage is applied to the leads of a
+
capacitor electrons accumulate on one of the + + + ++ +
+ ++ + +
insulator
plates and a depletion of electrons forms on the conductor (dielectric)
-
other. Since the plates are not in contact the - - - - -- -
electrons cannot continue to flow. The
-
- - -
accumulation of electrons is called a charge.

When a capacitor is charged the power source

can be removed and it will hold its charge until
the leads of the capacitor are connected to some
conductor. The capacity to hold charge (called capacitance, symbol C) is measured in units of Farads.

*
http://www.ubmail.ubalt.edu/~harsham/Business-stat/otherapplets/SysEq.htm
58
 We can use a resistor to slow the rate of charge and
discharge as shown in the simple RC-circuit shown
+ C below.
V
When the switch is closed, the capacitor will begin to
- charge. The voltage drop across the capacitor will
R
asymptotically approach the source voltage. The
amount of charge (measured in volts) on the capacitor
as a function of time is given by,
 
t

VC (t )  V  
1  e
RC 

 
Voltage

where V is the source voltage, R is in ohms, C is in

Farads and t is the time in seconds. The product R .C
is called the RC-time constant and it represents the
time required for the voltage across the capacitor to
increase by ~62.3% of the remaining voltage. Once
RC 2RC 3RC 4RC 5RC charged, a capacitor can be discharged by connecting
Time
it leads to a conductor. In the circuit below a capacitor,
C with an initial charge producing a voltage VC is
connected to a resistor R. When the switch is closed the capacitor will be discharged at a rate
determined by the RC-time constant.
Voltage

+
VC C
-

R
RC 2RC 3RC 4RC 5RC
Time

t

V (t )  VC  e RC

+ C
Example: Compute the voltage drop across the capacitor
and the resistor in the circuit below 3 seconds after the V
switch is closed. C=10F, R=100K, V=10 v The instant the
switch is closed, the voltage drop across the capacitor is -
zero, which means that the voltage drop across the resistor R
is V=10v. As the capacitor charges the voltage drop across
the capacitor increases asymptotically while the voltage drop
across the resistor decreases by a proportional amount. The RC-time constant is equal to (100x10 3)
(100x10-6)=10 seconds, so we can compute the voltage drop across the capacitor after 3 seconds by,
 
t
  
3

VC  V  
 1  e RC   (10) 1  e 10
 
  (10)(1  0.741)  2.59 volts

   

When two capacitors are connected in parallel

the equivalent capacitance is the sum of the
capacitance of each. When they are connected C1
in series the equivalence capacitance is reduced.
C1 C2
C2 59
 1
C series 
C parallel  C1  C 2 1 1

C1 C 2

R4
R1
+
R5
Exercises V

1. Given R1 through R6 = 100 and V=10v, find the -

voltage drop across and current through each resistor in
R2 R3 R6
the circuit on the right.

2. What is the power dissipated by resistor R 3 in this

circuit?

3. In the circuit on the right, the switch is flipped up for

1 second and then back down. Compute the voltage
drop across the capacitor 5 seconds after the switch is
+ 100F
flipped down.
10 v
100K
-
10K
4. Compute the equivalent resistance of the following
resistor networks.

R R R
R R
R R R

R R R

R R R R R

R R R

a. b.
c.

R R R R R

d.

5. Compute the equivalence capacitance of three capacitors C each with

60F capacitance connected in series.

60
6. Solve for the currents and voltage drops across each resistor in the circuit shown below. Vs=10 volts
and R1 through R6 are 100 ohms each.

Diode - A diode is an electronic component that allows electrons to flow in one direction but not in the
other direction.
1N4004
cathode anode anode
cathode

The direction of current is from the anode to the cathode. There are a wide variety of diodes. Normally
diodes are used to redirect or restrict electron flow. A zener diode is used to drop the voltage of a source
to some lower level. A light-emitting diode (LED) as shown below is used as an indicator.

V R

There is a dual red-green LED on the BasicX-24. This type of

LED is made of two separate LEDs of different colors. When applied to a voltage source with a particular
polarity one of the LEDs lights, and when the polarity is reversed the other lights. If alternating current is
applied both LED's light giving an impression of another color (e.g. yellow for a red-green dual LED).

Resistor Color Code

61
 1 The first two bands of the color code represent the first two digits of the resistance value in ohms. The third
band indicates the number of zeros to append to these digits (i.e. the power of 10). For example the color
2 code red, red, yellow represents 220000 ohms or 220K ohms. The color code green, blue, red represents
5600 or 5.6K ohms.
3
Resistors with only three bands have resistances that are accurate to within 20% of the indicated value.
4 If there is a silver fourth band this resistor's value will be within 10% of the indicated value. A gold fourth band
5 represents 5% accuracy. If a resistor has a fifth band this indicates the expected number of values that will
be out of tolerance in terms of 1 in 10color_value. For example a yellow fifth band indicates that 1 in 104 resistors
6 will be out of tolerance.
When a resistor has only three bands the first band is the one closest to the end of the resistor. If the resistor
7 has four or five color bands the presence of a silver or gold fourth band can be used to find the first band.
8

7. Give the resistances for the following color bands:

a. red, red, brown b. yellow, purple, yellowc. brown, black, red

_____________ _______________ ______________

8. Give the color bands for the following resistances:

a. 31K Ohm b. 100 K Ohm c. 5.6 Meg Ohm

_____________ ______________ _______________

_____________ ______________ _______________

_____________ ______________ _______________

9. Choose the proper wattage resister for each of the following conditions. Show your work.

a. 100 Ohm at 12 Volts _______________________________________________

b. 1K Ohm at 120 Volts _______________________________________________

c. 330 Ohm at 5 Volts _______________________________________________

d. 10 Ohm at 120 Volts _______________________________________________

62
 Appendix D
PDLP Circuit Diagram/Software

63
PDLP Circuit Diagram

64
 Appendix D
PDLP Software

65
' Programmable Digital Logic Processor Laboratory
' Laboratory Setup 01
' Copyright 2004 - Robot Crafters LLC
' www.robotcrafters.com
'
' This Setup is suitable for presenting binary data patterns to any
' Combinational Circuit with up to 8 input variables

Option Explicit
Public Sub Main()
Dim i as Byte
Dim mode as Byte
Dim IO_Val as Byte
Dim Num_Vars as Byte
Dim Max_Count as Byte
Num_Vars = 0
IO_Val = 0
Max_Count = 0
mode = 0 'mode 0=A, 1=b, 2=C
StartUp
Hello
Set_Digit 1,1
Set_Digit 2,0
Delay 2.0
Clear_Digit 2
Set_Digit 1,(mode+10)
Set_Out_Byte 0
Do
Select Case Get_Button
Case 0 'no button
Clear_Digit 2
Case 1 'first button
IO_Val = 0
Set_Out_Byte 0
mode = (mode+1) mod 3
Set_Digit 2,(mode+10)
Delay 0.25
Set_Digit 1,(mode+10)
Clear_Digit 2
Case 2 'second button
Select Case mode
Case 0
IO_Val = (IO_Val + 1) Mod (Max_Count + 1)
Set_Out_Byte IO_Val
Delay 0.1
Case 1
Num_Vars = (Num_Vars + 1) Mod 9
Max_Count = CByte(CInt(Pow(2.0,CSng(CInt(Num_Vars))))-1)
Set_Digit 2,Num_Vars
Delay 0.25
Clear_Digit 2
Case 2
IO_Val = 0
Delay 1.0
Set_Out_Byte 0
If Num_Vars>0 Then
For i=0 to Max_Count-1
IO_Val = IO_Val +1
Set_Out_Byte IO_Val
Delay 0.5

66
 If Get_Button>0 then
Exit For
End If
Next
End If
IO_Val = 0
Set_Out_Byte IO_Val
End Select
Case 3 'third button
IO_Val = 0
Set_Out_Byte 0
End Select
Loop
End Sub

67
' Programmable Digital Logic Processor Laboratory
' Laboratory Setup 02
' Copyright 2004 - Robot Crafters LLC
' www.robotcrafters.com
'
' This Setup is suitable for presenting binary data patterns to any
' Sequential Circuit and for evaluating the current state for circuits with
' up to 8 flip flops

Option Explicit
Public Sub Main()
Dim i as Byte
Dim mode as Byte
Dim IO_Val as Byte
Dim Tval as Byte
Dim Lo_Nibble as Byte
Dim Hi_Nibble as Byte
Dim Num_Vars as Byte
Dim Seq_Val as Byte
Dim Seq(0 to 7) as Byte
Dim stp as Byte
Num_Vars = 0
IO_Val = 0
Seq_Val = 0
mode = 0 'mode 0=A, 1=b, 2=C, 3=d, 4=E
stp = 0
Tval = 0
StartUp
Hello
Set_Digit 1,2
Set_Digit 2,0
Delay 2.0
Clear_Digit 2
Set_Digit 1,(mode+10)
Set_Out_Byte 0
Do
Select Case Get_Button
Case 0 'no button
Clear_Digit 2
Case 1 'first button
IO_Val = 0
mode = (mode+1) mod 5
Set_Digit 2,(mode+10)
Delay 0.25
Set_Digit 1,(mode+10)
Clear_Digit 2
stp=0
Select Case mode
Case 0
Set_Out_Byte 0
Clear_Digit 2
Case 1
Set_Digit 2,Num_Vars
Delay 0.5
Case 2
Seq_Val=0
End Select
Case 2 'second button
Select Case mode
Case 0 'A

68
 If Num_Vars>0 Then
PutPin 6,Seq(stp)
Set_Digit 2,stp
PutPin 5,1
Delay 0.25
PutPin 5,0
stp = (stp+1) mod Num_Vars
End If
Delay 0.1
Case 1 'b
Num_Vars = (Num_Vars + 1) Mod 9
Set_Digit 2,Num_Vars
Delay 0.25
Clear_Digit 2
Case 2 'C
If Num_Vars>0 Then
Seq(stp)=0
Set_Digit 2,stp
Set_Out_Byte Seq_Val
stp=(stp+1) mod Num_Vars
If stp=0 Then
Seq_Val=0
End If
End If
Case 3 'd
If Num_Vars>0 Then
Do
PutPin 6,Seq(stp)
Set_Digit 2,stp
PutPin 5,1
Delay 0.1
PutPin 5,0
stp = (stp+1) mod Num_Vars
If Get_Button=3 Then
Exit Do
End If
Delay 0.5
Loop
End If
Case 4
Tval=Get_In_Byte()
Lo_Nibble=Tval mod 16
Hi_Nibble=Tval\16
Set_Digit 1,Lo_Nibble
Set_Digit 2,Hi_Nibble
Delay 1.0
Clear_Digit 1
Clear_Digit 2
End Select
Delay 0.25
Case 3 'third button
Select Case mode
Case 0 'A
stp=0
Seq_Val = 0
Set_Out_Byte 0
Clear_Digit 2
Case 1 'b
For i=0 to 7
Seq(i)=0

69
 Next
Num_Vars=0
Case 2 'C
If Num_Vars>0 Then
Seq(stp)=1
Set_Digit 2,stp
Seq_Val = Seq_Val+CByte(CInt(Pow(2.0,CSng(CInt(stp)))))
Set_Out_Byte Seq_Val
stp=(stp+1) mod Num_Vars
If stp=0 Then
Seq_Val=0
End If
End If
Case 3 'd
Set_Out_Byte 0
stp=0
Clear_Digit 2
Case 4 'E
Set_Out_Byte Tval
End Select
Delay 0.25
End Select
Loop

70
' Programmable Digital Logic Processor Laboratory
' Laboratory Setup 03
' Copyright 2004 - Robot Crafters LLC
' www.robotcrafters.com
'
' This setup is designed to evaluate single and dual input flip-flops
' in both positive logic and negative logic modes

Option Explicit
Public Sub Main()
Dim i as Byte
Dim mode as Byte
Dim IO_Val as Byte
Dim Num_Vars as Byte
Dim Max_Count as Byte
Num_Vars = 2
IO_Val = 0
Max_Count = 3
mode = 0 'mode 0=A, 1=b, 2=C
StartUp
Hello
Set_Digit 1,3
Set_Digit 2,0
Delay 2.0
Clear_Digit 2
Set_Digit 1,(mode+10)
Set_Out_Byte 0
Do
Select Case Get_Button
Case 0 'no button
Clear_Digit 2
Case 1 'first button
IO_Val = 0
Set_Out_Byte 0
mode = (mode+1) mod 3
Set_Digit 2,(mode+10)
Delay 0.25
Set_Digit 1,(mode+10)
Clear_Digit 2
Case 2 'second button
Select Case mode
Case 0
IO_Val = (IO_Val + 1) Mod 2
Set_Out_Byte (IO_Val+1)
Delay 0.2
Set_Out_Byte 3
Case 1
IO_Val = (IO_Val + 1) Mod 2
Set_Out_Byte (IO_Val+1)
Delay 0.2
Set_Out_Byte 0
Case 2
IO_Val = 0
Delay 1.0
Set_Out_Byte 0
If Num_Vars>0 Then
For i=0 to Max_Count-1
IO_Val = IO_Val +1
Set_Out_Byte IO_Val
Delay 0.5

71
 If Get_Button>0 then
Exit For
End If
Next
End If
IO_Val = 0
Set_Out_Byte IO_Val
End Select
Case 3 'third button
IO_Val = 0
Set_Out_Byte 0
End Select
Loop
End Sub

72
' Programmable Digital Logic Processor Laboratory
' Laboratory Setup 04
' Copyright 2004 - Robot Crafters LLC
' www.robotcrafters.com
'
' This Setup is suitable for building and testing seven segment displays

Option Explicit
Public Sub Main()
Dim i as Byte
Dim mode as Byte
Dim IO_Val as Byte
Dim Tval as Byte
Dim Lo_Nibble as Byte
Dim Hi_Nibble as Byte
Dim Num_Vars as Byte
Dim Dig as Byte
Dim Seq_Val as Byte
Dim Seq(0 to 7) as Byte
Dim stp as Byte
Num_Vars = 8
Dig = 0
IO_Val = 0
Seq_Val = 0
mode = 0 'mode 0=A, 1=b, 2=C, 3=d, 4=E
stp = 0
Tval = 0
StartUp
Hello
Set_Digit 1,4
Set_Digit 2,0
Delay 2.0
Clear_Digit 2
Set_Digit 1,(mode+10)
Set_Out_Byte 0
Do
Select Case Get_Button
Case 0 'no button
Clear_Digit 2
Case 1 'first button
IO_Val = 0
mode = (mode+1) mod 3
Set_Digit 2,(mode+10)
Delay 0.25
Set_Digit 1,(mode+10)
Clear_Digit 2
stp=0
Select Case mode
Case 0
Set_Out_Byte 0
Clear_Digit 2
Case 1
Seven_Seg_Serial Dig
Delay 0.5
Case 2
Seq_Val=0
End Select
Case 2 'second button
Select Case mode
Case 0 'A

73
 Serial_One
Case 1 'b
Dig = (Dig + 1) Mod 16
Set_Digit 2,Dig
Delay 0.25
Clear_Digit 2
Case 2 'C
For i=0 to 15
Seven_Seg_Serial i
Delay 0.5
Next
End Select
Delay 0.25
Case 3 'third button
Select Case mode
Case 0 'A
Serial_Zero
Case 1 'b
Seven_Seg_Serial Dig
Delay 0.5
Case 2 'C
Clear_Serial
End Select
Delay 0.25
End Select
Loop
End Sub

74
' Programmable Digital Logic Processor Laboratory
' Laboratory Setup 05
' Copyright 2004 - Robot Crafters LLC
' www.robotcrafters.com
'
' This Setup is suitable for presenting 8-bit data to a circuit in parallel
' and reading and displaying 8-bit data from a circuit in parallel

Option Explicit
Public Sub Main()
Dim i as Byte
Dim mode as Byte
Dim IO_Val as Byte
Dim Num_Vars as Byte
Dim Max_Count as Byte
Dim Dig_Val as Byte
Num_Vars = 8
IO_Val = 0
Max_Count = 255
Dig_Val = 1
mode = 0 'mode 0=A, 1=b, 2=C
StartUp
Hello
Set_Digit 1,5
Set_Digit 2,0
Delay 2.0
Clear_Digit 2
Set_Digit 1,(mode+10)
Set_Out_Byte 0
Do
Select Case Get_Button
Case 0 'no button
Clear_Digit 2
Case 1 'first button (i.e. right hand side)
IO_Val = 0
Set_Out_Byte 0
mode = (mode+1) mod 3
Set_Digit 2,(mode+10)
Delay 0.25
Set_Digit 1,(mode+10)
Clear_Digit 2
Case 2 'second button (i.e. middle button)
Select Case mode
Case 0 'Mode A
IO_Val = (IO_Val + 1) Mod (Max_Count + 1)
Set_Out_Byte IO_Val
Delay 0.1
Case 1 'Mode b
IO_Val = IO_Val*2
IO_Val = IO_Val+1
If IO_Val>255 then
IO_Val=1
End If
Delay 0.15
Set_Out_Byte IO_Val
Case 2 'Mode C
IO_Val = 0
Delay 1.0
Set_Out_Byte 0
If Num_Vars>0 Then

75
 For i=0 to Max_Count-1
IO_Val = IO_Val +1
Set_Out_Byte IO_Val
Delay 0.5
If Get_Button>0 then
Exit For
End If
Next
End If
IO_Val = 0
Set_Out_Byte IO_Val
End Select
Case 3 'third button (i.e. left hand button)
Select Case mode
Case 0 'Mode A
IO_Val = 0
Set_Out_Byte IO_Val
Case 1 'Mode b
IO_Val = IO_Val*2
If IO_Val>255 then
IO_Val=0
End If
Delay 0.15
Set_Out_Byte IO_Val
Case 2 'Mode C
IO_Val = 0
Set_Out_Byte IO_Val
End Select
End Select
Loop
End Sub

76
' PDLP Digits Module Contains the Low Level Functions to drive the I/O

Option Explicit
'-------------------------------------------------------------------
Public Sub Clear_Digit(ByVal N as Byte)
Dim P as Byte
Dim Q as Byte
P=3*N + 14
Q=3*N + 13
Dim i as Integer
PutPin P,1
Delay 0.001
For i=0 to 7
PulseOut Q,0.001,0
Next
End Sub

'-------------------------------------------------------------------
Public Sub Set_Digit(ByVal N as Byte, ByVal V as Byte)
Dim P as Byte
Dim Q as Byte
P=3*N + 14
Q=3*N + 13
Dim D(0 to 7) as Byte
Dim i as Integer
For i=0 to 7
D(i)=0
Next
D(3)=1

Select Case V
Case 0 '0
D(6)=1
Case 1 '1
D(0)=1
D(4)=1
D(5)=1
D(6)=1
D(7)=1
Case 2 '2
D(2)=1
D(7)=1
Case 3 '3
D(5)=1
D(7)=1
Case 4 '4
D(0)=1
D(4)=1
D(5)=1
Case 5 '5
D(1)=1
D(5)=1
Case 6 '6
D(1)=1
Case 7 '7
D(4)=1
D(5)=1
D(6)=1
D(7)=1
Case 8

77
 '8
Case 9 '9
D(5)=1
Case 10 'A
D(4)=1
Case 11 'b
D(0)=1
D(1)=1
Case 12 'C
D(1)=1
D(2)=1
D(6)=1
Case 13 'd
D(0)=1
D(7)=1
Case 14 'E
D(1)=1
D(2)=1
Case 15 'F
D(1)=1
D(2)=1
D(4)=1
Case 16 'top box
D(0)=1
D(1)=1
D(7)=1
Case 17 'bottom box
D(2)=1
D(4)=1
D(5)=1
Case 18 'H
D(0)=1
D(4)=1
Case 19 'L
D(0)=1
D(1)=1
D(2)=1
D(6)=1
End Select
For i=0 to 7
PutPin P,D(i)
Delay 0.0001
PulseOut Q,0.0001,0
Next
End Sub
'-------------------------------------------------------------------
Public Sub StartUp()
Dim i as Integer
Delay 0.001
Clear_Digit 1
Clear_Digit 2
Delay 1.0
For i=0 to 5
Set_Digit 1,16
Set_Digit 2,17
Delay 0.1
Set_Digit 1,17
Set_Digit 2,16
Delay 0.1
Next

78
 Clear_Digit 1
Clear_Digit 2
Delay 1.0
End Sub
'-------------------------------------------------------------------
Public Sub Set_Out_Byte(ByVal N as Byte)
Dim i as Byte
For i=0 to 7
PutPin 5+i,(N Mod 2)
N = N\2
Next
End Sub
'-------------------------------------------------------------------
Public Sub Hello()
Clear_Digit 1
Clear_Digit 2
Set_Digit 1,18
Delay 0.2
Set_Digit 2,18
Set_Digit 1,14
Delay 0.2
Set_Digit 2,14
Set_Digit 1,19
Delay 0.2
Set_Digit 2,19
Delay 0.2
Set_Digit 1,0
Delay 0.2
Set_Digit 2,0
Clear_Digit 1
Delay 0.2
Clear_Digit 2
Delay 0.5
End Sub
'-------------------------------------------------------------------
Public Function Get_Button() As Byte
Dim Rtn_Val as Byte
Rtn_Val = 0
If (GetPin(15) = 1) Then
Rtn_Val = 1
End If
If (GetPin(14) = 1) Then
Rtn_Val = 2
End If
If (GetPin(13) = 1) Then
Rtn_Val = 3
End If
Get_Button = Rtn_Val
End Function
'-------------------------------------------------------------------
Public Function Get_In_Byte() As Byte
Dim i As Byte
Dim del As Single
del = 0.01
Get_In_Byte = 0
PutPin 13,1
Delay del
For i=0 to 7
PutPin 14,1
Delay del

79
 PutPin 14,0
Delay del
Next
PutPin 13,0
PutPin 14,0
Delay del
PutPin 14,1
Delay del
PutPin 14,0
PutPin 13,1
Delay del
For i=0 to 7
Get_In_Byte = (Get_In_Byte*2) + GetPin(18)
PutPin 14,1
Delay del
PutPin 14,0
Delay del
Next
PutPin 13,0
End Function
'-------------------------------------------------------------------
Public Sub Seven_Seg_Serial(ByVal V as Byte)
Dim D(0 to 7) as Byte
Dim i as Integer
For i=0 to 7
D(i)=0
Next
D(7)=1
Select Case V
Case 0 '0
D(6)=1
Case 1 '1
D(0)=1
D(3)=1
D(4)=1
D(5)=1
D(6)=1
Case 2 '2
D(2)=1
D(5)=1
Case 3 '3
D(4)=1
D(5)=1
Case 4 '4
D(0)=1
D(3)=1
D(4)=1
Case 5 '5
D(1)=1
D(4)=1
Case 6 '6
D(1)=1
Case 7 '7
D(3)=1
D(4)=1
D(5)=1
D(6)=1
Case 8
'8
Case 9 '9

80
 D(4)=1
Case 10 'A
D(3)=1
Case 11 'b
D(0)=1
D(1)=1
Case 12 'C
D(1)=1
D(2)=1
D(6)=1
Case 13 'd
D(0)=1
D(5)=1
Case 14 'E
D(1)=1
D(2)=1
Case 15 'F
D(1)=1
D(2)=1
D(3)=1
End Select
For i=0 to 7
PutPin 6,D(i)
Delay 0.0001
PulseOut 5,0.0001,0
Next
End Sub
'-------------------------------------------------------------------
Public Sub Clear_Serial()
Dim i as Byte
PutPin 6,1
For i=0 to 7
Delay 0.0001
PulseOut 5,0.0001,0
Next
PutPin 6,0
PutPin 5,0
End Sub
'-------------------------------------------------------------------
Public Sub Serial_Zero()
PutPin 6,0
Delay 0.0001
PulseOut 5,0.0001,0
End Sub
'-------------------------------------------------------------------
Public Sub Serial_One()
PutPin 6,1
Delay 0.0001
PulseOut 5,0.0001,0
End Sub

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