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in FinFET
Alvin Loke
alvin.loke@ieee.org
Qualcomm Technologies, Inc.
PMOS p+ source
p+ source
n-well n-well
p-substrate p-substrate
NMOS PMOS
Garcia Bardon et al., IMEC [5]
Liu et al., Globalfoundries [6]
NMOS PMOS
-2% +8%
-4% +6%
-6% +4%
-8% +2%
-10% 0%
HK HK
HK-first (bottom only) HK-last (bottom+sides)
Auth et al., Intel [10] Packan et al., Intel [11]
MG very resistive
fins in over fin ΦM1
gate trench gate
PMOS ΦM metal metal fill
fins
NMOS
fins
fins ΦM2
spacer gate Asenov, U Glasgow [12]
Yamaguchi et al., Toshiba [13]
Yang et al., Qualcomm [14]
sacrificial
mandrel spacer
Mask A Mask B
contact spacer
gate well
S/D
Auth et al., Intel [15]
Rashed et al., Globalfoundries [17]
Vref Vbias
OTA CGS
CGD
Vout Vin Vref
Vout
diffusion short
contact together
low-frequency high-frequency
ac current ac current
A B A A B A A B A
• Accumulation-mode varactor C
• Steeper transition for
n+ n+ accumulation
higher KVCO
• Quarter-gap ΦM gate
material for higher VT n-well inversion
p-substrate
VGS
• Metal-Insulator-Metal (MIM) – Extra cost, less common
Chang et al., UC Berkeley [20]
p+ n+ p+
n-well p-well
p-substrate
p+
n-well n-well
p-substrate p-substrate