Low Power Design Methods:

Design Flows and Kits

Shushanik Karapetyan
1st year PhD Student
Synopsys Armenia Educational Department,
State Engineering University of Armenia

Moscow
March 23, 2011

Copyright © 2011 Synopsys, Inc.

Outline

• Low Power Design Flows

• Library requirements for Low Power Design
• Example of 90nm EDK

Copyright © 2011 Synopsys, Inc.

Conventional Design Flow
System and Software Architecture Power Management should be
taken into account at the earliest
design stages
RTL Implementation

Logic simulation

Logic Synthesis Almost every step of design flow

need to be modified for LPD
Timing Analysis

Formal Verification

Physical Synthesis

Signoff

Copyright © 2011 Synopsys, Inc.

Power-Aware Design Flow
System and Software Architecture Choose appropriate
power intent, design styles etc.
RTL Implementation Implement power intent
in appropriate format
Logic simulation
Power aware simulation
and analysis
Logic Synthesis
Automate synthesis
Timing Analysis of LPD techniques

Power-aware verification
Formal Verification
needed to reveal power
Related bugs
Physical Synthesis

Signoff tools must be voltage-

Signoff aware for silicon success

Copyright © 2011 Synopsys, Inc.

LPD Techniques Automation Levels

D Q Leakage
Clock Gating EN
CG
FF Multi-threshold
Clk Delay
Clock Gate Low-Vth Std-Vth High-Vth

Automatically No special treatment needed

OFF
0.9V
Power gating 0.9V Multi Voltage
0.9V 0.9V 0.7V 0.9V

Automatically Specification of power intent (UPF)

Copyright © 2011 Synopsys, Inc.

Unified Power Format (UPF): Necessity

Specification of Interoperable Can be freely used

Language
power intent among EDA tools (open standard)

Hardware
Description
Languages - + +
(Verilog, VHDL, etc.)

Vendor –Specific
Formats + - -

UPF + + +

Copyright © 2011 Synopsys, Inc.

Specifying Power Intent

A 0.9V
Periphery Power Domain
0.9/OFF

OFF

Supply Network

•iso
LS
LS
B C
LS
0.7V/1.2V 0.9V

LS

Operation Scenario
(OFF, 0.9V, 0.7V)
(0.9V, 0.9V, 1.2V) MV with power gating

Copyright © 2011 Synopsys, Inc.

MV with Power Gating Example

VDDA
A 0.9V
VDD
VDDB VDD
0.9/OFF
Control
RR
VDDV
OFF
VSS

•iso
LS
LS

B
VDDA LS C
0.7V/1.2V 0.9V VDD
VDDB LS
VSS VSS

VSS

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UPF: Power Domains

UPF
VDDA
A 0.9V Power Power
VDD
VDDB VDD Domain State
0.9/OFF
A 0.9/OFF
RR VDDV
OFF B 0.7/1.2
VSS
C 0.9

•iso
LS
LS

LS
Control

B
VDDA LS C
0.7V/1.2V 0.9V VDD
VDDB LS
VSS VSS

VSS

Copyright © 2011 Synopsys, Inc.

UPF: Supply Network

UPF
VDDA
A 0.9V Supply Voltage Power
VDD
VDDB VDD Net Level (V) Domain
0.9/OFF
VDD 0.9 C
RR VDDV
OFF VDDA 0.7 B
VSS
VDDB 1.2 B

•iso
LS
LS

LS VDDV Virtual 0.9 A

Control
VSS Common A/B/C
B Ground
VDDA LS C
0.7V/1.2V 0.9V VDD
VDDB LS
VSS VSS

VSS

Copyright © 2011 Synopsys, Inc.

UPF: Periphery

UPF
VDDA
A 0.9V Required Periphery
VDD
VDDB VDD
0.9/OFF Level Shifters between A and B
RR VDDV Level Shifters between B and C
OFF
VSS Isolation between C and A

Retention Cell inside A

•iso
LS
LS

LS
Control Control Block inside A
B
VDDA LS C
0.7V/1.2V 0.9V VDD
VDDB LS
VSS VSS

VSS

Copyright © 2011 Synopsys, Inc.

UPF: State Scenario

UPF
VDDA
A 0.9V A B C Scenario
VDD
VDDB VDD
0.9/OFF 0.9 0.7 0.9 Allowed
RR VDDV 0.9 1.2 0.9 Allowed
OFF
VSS OFF 0.7 0.9 Allowed

OFF 1.2 0.9 Not Allowed

•iso
LS
LS

LS

Control

B
VDDA LS C
0.7V/1.2V 0.9V VDD
VDDB LS
VSS VSS

VSS

Copyright © 2011 Synopsys, Inc.

 Design Flow Modification with UPF
Initial UPF description is
Design Specification modified during design

Initial Power Intent

RTL + Initial UPF •LPD Technique strategy
•Implementation details
Ex. Synopsys
Design Compiler Logic Synthesis

Gate Level + Gate Level •Supply net connections

UPF •Special cells
Ex. Synopsys
IC Compiler
Physical Synthesis

•Modifications to low-power
Gate Level + Physical circuit structures
PG Gate Level UPF

Copyright © 2011 Synopsys, Inc.

Design Compiler Visual UPF
Strategies Visualization
Supply port

PD boundary
Block PD primary
power net
Power Switch

ISO location Retention register

parentwith
backup power
defined

LS strategy Top PD primary

defined in ground net
UPF

Copyright © 2011 Synopsys, Inc.

 IC Compiler UPF Placement

• Placement respects LS cells

voltage area
boundary
• Special Level Shifter
and Isolation Cells
placement
 Special cells ISO cells
placed closer to
VA boundary

Copyright © 2011 Synopsys, Inc.

Library Requirements for LPD

• Special cells
• Special versions of library
• Characterization in additional corners
• Additional views/files/attributes

Copyright © 2011 Synopsys, Inc.

90nm EDK: Digital Standard Cell Library

Digital Standard Cell Library (DSCL)

Aimed at optimizing the main characteristics of designed Ics

Contains 340 cells, cell list compiled based on the requirements for educational
designs

Typical combinational and sequential logic cells for different drive strengths

Typical combinational and sequential Special cells for different styles LPD

Flip-Flops Retention
Inverters/Buffers Logic Gates Isolation Cells Level Shifters
(regular+scan) Flip-Flops
Physical Always-on
Latches Delay Lines Clock gating Power Gating
(Antenna diode) Buffers

Provides the support of IC design with different core voltages to minimize

dynamic and leakage power.

Copyright © 2011 Synopsys, Inc.

Special Cells for LPD: Level Shifter

1.2

LS

LS
LS

LS
LS
0.9 0.7
LS

Level Shifters

Copyright © 2011 Synopsys, Inc.

Level Shifter

VDDL VDDH VDDH VDDL

D Q D Q

VSS VSS

Logic Symbol of Low to High Level Shifter Logic Symbol of High to Low Level Shifter

Low to High Level Shifter Truth Table High to Low Level Shifter Truth Table

D (0.8V) Q (1.2V) D (1.2V) Q (0.8V)

0 0 0 0
1 1 1 1

Copyright © 2011 Synopsys, Inc.

Level Shifter Physical Structure
VDD VDD
L H

VDDH VDDL

VS VS
S S

VDDL VDDH

High-to-Low Low-to-High

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Level Shifter (High to Low) Physical
Design
VDDL

VDDH High
voltage
areas

Low voltage
area
VDDL

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Level Shifter (Low to High) Physical
Design
VDDH
Low voltage
VDDL area

H
High
voltage
areas

VDDH

Copyright © 2011 Synopsys, Inc.

Special Cells for LPD: Isolation Cells
Power Gating

0.9

0.9 OFF/0.7

Isolation Cells

Copyright © 2011 Synopsys, Inc.

Isolation Cells

D D

Q Q

ISO ISO

Logic Symbol of Clamp 0 Logic Symbol of Clamp 1

Isolation Cell (Logic AND) Isolation Cell (Logic OR)

Hold 0 Isolation Cell (Logic AND) Truth Table Hold 1 Isolation Cell (Logic OR) Truth Table
D ISO Q D ISO Q
0 1 0 Bypass 0 0 0 Bypass
1 1 1 mode 1 0 1 mode
X 0 0 X 1 1

Output clamped

Copyright © 2011 Synopsys, Inc.

Isolation Cells: Physical Design

Copyright © 2011 Synopsys, Inc.

Special Cells for LPD: Always-on Buffers
Power Gating

0.7 – 1.08

0.9 OFF/0.7

Always on cells

Copyright © 2011 Synopsys, Inc.

Always-on Buffer

VDDG

INP Z

VDD local
(on/off)
VSS

Logic Symbol of Always Always on

on Non-Inverting Buffer area

Always on Non-Inverting VDD_global

Buffer Truth Table (always-on)
IN VDDG VSS Q
VSS local
(on/off)
0 1 0 0
1 1 0 1

Copyright © 2011 Synopsys, Inc.

Special Cells for LPD: Always-on Isolation cells

Always-on
Isolation Cells

0.7

0.9 OFF/0.7

Copyright © 2011 Synopsys, Inc.

Always on Isolation Cells

VDD VDDG VDD VDDG

D D
Q
Q
ISO
ISO

VSS VSS

Logic Symbol of Clamp 0 Isolation Cell Logic Symbol of Clamp 1 Isolation Cell
(Logic AND),Always On (Logic OR), Always On

Hold 0 Isolation Cell (Logic AND) Truth Table Hold 1 Isolation Cell (Logic OR) Truth Table
D ISO Q D ISO Q
0 1 0 Bypass 0 0 0 Bypass
1 1 1 mode 1 0 1 mode
X 0 0 X 1 1

Output clamped

Copyright © 2011 Synopsys, Inc.

Isolation Cell (always-on) Physical Design

Always on supply

Always on area

Copyright © 2011 Synopsys, Inc.

Special Cells for LPD: Enable level
shifters
Enable level
shifters
• Combination of Level
Shifter and ISO cell
1.08

0.9 OFF/0.7

Copyright © 2011 Synopsys, Inc.

Level Shifters With Active Low Enable

VDDL VDDH VDDH VDDL

ENB ENB
LSUPEN
D Q Q
D

VSS VSS

Symbol of Low to High Level Shifter Symbol of High to Low Level Shifter
Active Low Enable, Clamp 0 Active Low Enable, Clamp 1

D(0.8V) ENB Q(1.2V) D(1.2V) ENB Q(0.8V)

0 1 0 Bypass 0 0 0 Bypass
1 1 1 mode 1 0 1 mode
X 0 0 X 1 1

Output clamped

Copyright © 2011 Synopsys, Inc.

Enable Level Shifter (low-to-high)
Physical design

VDDH Low voltage

area
VDDL

High
voltage
areas

VDDH

Copyright © 2011 Synopsys, Inc.

State Retention Registers

State Retention Registers

RR RR RR

CTR
1.08V/OFF
1.08V/OFF

0.7V sleep
0.9V

• Retention Register - preserve

status while the logic is turned off

Copyright © 2011 Synopsys, Inc.

Retention Register Physical design

Always-on Power pin Always on area, with high-

Vth

Copyright © 2011 Synopsys, Inc.

Power Gates

RR RR RR

CTR
1.08V/OFF
1.08V/OFF

0.7V sleep
0.9V

Power Gates
• Retention Register - preserve
status while the logic is turned off
• Coarse Grain - Power Gates
(switch cells)

Copyright © 2011 Synopsys, Inc.

Header Cells

VDDG VDDG

VDD VDD
SLEEP SLEEP

SLEEPOUT

Logic Symbol of Header Cell Logic Symbol of Header Cell(with SLEEPOUT output )

Header Cell Truth Table Header Cell (with SLEEPOUT output) Truth Table

SLEEP VDDG VDD SLEEP VDDG VDD SLEEPOUT

0 1 1 0 1 1 0

1 1 hi-z 1 1 hi-z 1

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Header Cells Physical Design

a. Header Cell b. Header Cell (with SLEEPOUT output)

Copyright © 2011 Synopsys, Inc.

Multi-Threshold Libraries

100%
FF 80%
FF
60%

40%
FF 20%
Critical
Path 0%
Low-Vth Std-Vth High-Vth
FF
FF Leakage Delay

Multi-Vth libraries

AL BL CL Low Vth

AS BS CS Std Vth

AH BH CH High Vth

Copyright © 2011 Synopsys, Inc.

DSCL: Multi Threshold Versions of Cells

• For implementation of Multi-Vth technique the

whole DSCL is available in 3 versions (1020
cells)
 All cells with Low– threshold voltage
 All cells with Standard – threshold voltage
 All cells with High– threshold voltage

Copyright © 2011 Synopsys, Inc.

Characterization

• Characterization computes cell parameter (e.g. delay, output

current) depending on input variables: output load, input slew, etc.
• Characterization is preformed for various combinations of operating
conditions: process, voltage, temperature (also called PVT corners).

slew
Input Slew 0.7
slew
0.7 0.5 Process: Fast
slew Temp: 125o
0.7 0.5 Voltage: 1.32v
0.2
Iout 0.5 0.2 Process: Slow
0.1
Temp: -40o
0.2 0.1 .023 .047 .065 .078 .091 Voltage: 1.08v
Cchar output cap
0.1 .023 .047 .065 .078 .091 Process: Typical
output cap
Temp: 25o
.023 .047 .065 .078 .091 Voltage: 1.2v
output cap

Copyright © 2011 Synopsys, Inc.

DSCL: Characterization Corners

Process
Corner
(NMOS proc. – Temperature (T) Power Supply (V) Notes
Name
PMOS proc.)
TTNT1p20v Typical - Typical 25 1.2 Typical corner
SSHT1p08v Slow - Slow 125 1.08 Slow corner
FFLT1p32v Fast - Fast -40 1.32 Fast corner
High leakage
FFHT1p32v Fast - Fast 125 1.32
corner
SSLT1p32v Slow - Slow -40 1.32 Low temperature
SSLT1p08v Slow - Slow -40 1.08 corners
Low Voltage Operating Conditions
TTNT0p80v Typical - Typical 25 0.80 Typical corner
SSHT0p70v Slow - Slow 125 0.70 Slow corner
FFLT0p90v Fast - Fast -40 0.90 Fast corner
High leakage
FFHT0p90v Fast - Fast 125 0.90
corner
SSLT0p90v Slow - Slow -40 0.90 Low temperature
SSLT0p70v Slow - Slow -40 0.70 corners

Copyright © 2011 Synopsys, Inc.

DSCL: Additional Data
• Power / ground (PG) pin
definitions are required for pg_pin(VDD) {
all cells in a library std_cell_main_rail : true ;
 Defined as attributes in .lib
voltage_name : VDD;
 Allows accurate definition of
multiple power / ground pin pg_type : primary_power;
information }
• Benefits pg_pin(VSS) {
 Power domain driven voltage_name : VSS;
synthesis pg_type : primary_ground;
 Automatic power net }
connections
 PST-based optimization
 Verification of PG netlist vs.
power domains
 Power switch verification

Copyright © 2011 Synopsys, Inc.

 DSCL: Power Verilog Models
module AND2X1 (IN1,IN2,Q,VDD,VSS);
output Q;
input IN1,IN2; Modeling output
inout VDD; state dependence
• Power Verilog models inout VSS; on power
 Separate verilog models with power_down iQ (Q, Qint, VDD, VSS);
power modeling and (Qint,IN1,IN2);
endmodule

primitive power_down (Q, Qint, vdd, vss);

output Q;
input Qint, vdd, vss;
module AND2X1(IN1,IN2,Q); table
0 1 0 : 0 ;
output Q;
1 1 0 : 1 ;
input IN1,IN2; ? 0 0 : x ;
? 0 1 : x ;
and (Q,IN2,IN1); ? 1 1 : x ;
? x ? : x ;
endmodule ? ? x : x ;
endtable
endprimitive

Copyright © 2011 Synopsys, Inc.

DSCL: Special Cells for Low Power
Techniques (1)
• Power Gatings VDDG VDDG

 5 cells with different loads VDD IN Q

AOn

• Always on SLEEP

 10 cells: 3 inverters, 3 buffers and VSS

4 DFFs
• Retention cells
VDD VDDG

 44 cells negedge/posedge, scan RETN Q D

ISO
Q
D
• Isolation cells CLK QN
ISO

 8 cells with different logic, load

VSS

Copyright © 2011 Synopsys, Inc.

DSCL: Special Cells for Low Power
Techniques (2)
• Level shifters VDDL VDDH

 16 cells Low/High, High/Low, with

or without enable, with different D
LSUP
Q
loads
• Clock gatings:
 11 cells with different loads, edges, VSS

and control (post/pre) SE

ENL
• HVT Cells EN
L
OBS
A
 All logical cells are designed using T
C
HVT, LVT CLK
H GCLK

Copyright © 2011 Synopsys, Inc.

DSCL: Special Cells for Low Power
Techniques (3)
Power Gates Isolation Level Shifters Retention Always On
(MTCMOS) Cells Registers Logic
Multiple Power
0.9V Domains
0.9V 0.9V
Single Voltage
Multiple Voltage
0.9V
0.7V 0.9V
(MV)
Domains
+
Power Gating
OFF
(shut down)
0.9V
0.9V 0.9V
Single Voltage
No State
+ + +
Retention
MV Domains
OFF
Power Gating
0.9V
0.7V 0.9V No State + + + +
Retention
OFF MV Domains
S 0.9V
R
0.7V 0.9V
Power Gating
State Retention
+ + + + +
Copyright © 2011 Synopsys, Inc.
Low Power Design of ChipTop Developed
with DSCL: DC view

Copyright © 2011 Synopsys, Inc.

Low Power Design of ChipTop Developed
with DSCL: ICC View

Copyright © 2011 Synopsys, Inc.

Conclusion

• Low Power Design requires significant design flow modifications

 UPF enables LPD flow automation
• Low Power design techniques have their huge impact on libraries
• SAED 90nm EDK DSCL includes all special cells needed for low
power design techniques
• This 90nm EDK is currently in use in 235 universities of 37 countries
• This 90nm EDK is used inside Synopsys for education of customers

• Currently similar EDK is being developed for 32/28nm technology,

initial release is planned in June 2011

Copyright © 2011 Synopsys, Inc.