Professional Documents
Culture Documents
OPEN = Q1 Q0
Vending Machine:
One-hot encoding (con’t) One-hot encoded transition table
◆ Often the best/convenient approach for FPGAs present state inputs next state output
■ FPGAs have many flip-flops Q3Q2Q1Q0 D N D3 D2D1D0 open Reset
D' N'
0 0 0 1 0 0 0 0 0 1 0
◆ Draw FSM directly from the state diagram
0 1 0 0 1 0 0 0¢
■ + One product term per incoming arc 1 0 0 1 0 0 0
■ - Complex state diagram ⇒ complex design D' N' N
1 1 – – – – –
■ - Many states ⇒ many flip flops 0 0 1 0 0 0 0 0 1 0 0 5¢ D
0 1 0 1 0 0 0
1 0 1 0 0 0 0 N
1 1 – – – – – D 10¢ D' N'
0 1 0 0 0 0 0 1 0 0 0
0 1 1 0 0 0 0 N+D
1 0 1 0 0 0 0 15¢
[open] 1
1 1 – – – – –
1 0 0 0 – – 1 0 0 0 1
Vending machine
FSM partitioning
--- already in output encoding form
◆ Break a large FSM into two or more smaller FSMs
Reset D0 = Q0D’N’
D' N' D1 = Q0N + Q1D’N’ ◆ Rationale
0¢ D2 = Q0D + Q1N + Q2D’N’ ■ Less states in each partition
µ Simpler minimization and state assignment
D' N' N D3 = Q1D + Q2D + Q2N + Q3
µ Smaller combinational logic
D OPEN = Q3 µ Shorter critical path
5¢
■ But more logic overall
N
Example: Partition the machine Introduce idle states for each partition
C1 S2 C3 S5
S1 S6
C2
S3 C4 C5 S4
C3
S2 S5
S1 C1 S6
C1•S1
(C2•S6)’
C2•S6 C2
S3 C4 C5 S4 (C1•S1+
C3•S2+ C3•S2+
S2 C3+C5 SA SB C4•S3
S5
C4•S3+
C5•S2)’
S3 C4 C5•S2 S4
Rule #1: Source-state transformation Rule #3: Multiple transitions with same source or destination
Replace by transition to idle state (SA) Source ⇒ Replace by transitions to idle state (SA)
Destination ⇒ Replace with exit transitions from idle state
C1 C1 C3
S1 S6 S1 SA S2 C3+C5 C3•S2 + S5
S2 S5 C4•S3
SA SB
C4 C5 C4
Rule #2: Destination state transformation S3 S4 S3 C5•S2 S4
Replace with exit transition from idle state
Rule #4: Hold condition for idle state
C2 C2•S6 “OR exit conditions and invert”
S1 S6 S1 SA
C2•S6
C2•S6
S1 SA
◆ Break into 2 parts ◆ Count sequence S0, S1, S2, S3, S4, S5
■ S2 goes to SA and holds, leaves after S5
U ≡ count up ■ S5 goes to SB and holds, leaves after S2
D ≡ count down ■ Down sequence is similar
U
S0 S5
U U
D
D D S0 S5
U U•S5 U U
S1 S4
D D D D (D•S3 + (D•S0+ D•S0 D
U D S1 SA U•S5)’ U•S2)’ SB S4
U D•S3
S2 S3 D D D
U U U U•S2 U
S2 S3
Compare behavior U ◆ 4-state machines need 2 state bits each – total 4 state bits
S0 S5 Enough to represent 16 states, though the combination of the two
on UUUUUU: U U ■
D FSMs has only 6 different configurations
D D
S1 S4 ◆ Why do this?
D D ■ Each FSM may be much simpler to think about (and design logic for)
U D than the original FSM (not here, though)
U
S2 S3 ■ Essential to do this partitioning for large FSMs
U
S0 S5 S0 S5
U U•S5 U U U•S5 U
U U
D D (D•S3 + D•S0 D D D (D•S3 + D•S0 D
(D•S0+ (D•S0+
S1 SA U•S5)’ U•S2)’ SB S4 S1 SA U•S5)’ U•S2)’ SB S4
D•S3 D•S3
D D D D D D
U U U•S2 U U U U•S2 U
S2 S3 S2 S3
◆ Ideal world: Two machines handoff control ◆ Mealy machine partitioning is undesirable
■ Separate I/O, states, etc. ■ Inputs can affect outputs immediately
µ “output” can be a handoff to another machine!!!
◆ Real world: Minimize handoffs and common I/O
■ Minimize number of state bits that cross boundary ◆ Moore machine partitioning is desirable
■ Merge common outputs ■ Input-to-output path always broken by a flip-flop
■ But…may take several clock cycles for input to propagate to
output