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cost of the product meanwhile increase the reliability and
performance. Nevertheless the complexity of embedded
system is continually increased. The number of states in
software is very large and complex description of a system
making system analysis very hard.
I. INTRODUCTION
The embedded systems are implemented as System-
on-Chip, which is referred to as a SoC design or SoC
embedded system. In this lab, SOPC Builder, Quartus II, and
Nios II IDE software is used in the Altera SOPC (System -on-
Programmable Chip) Builder to develop a Nios II-based
Embedded System.
This lab aims to design the software and hardware
partition of an embedded system. It will also perform the
design-space exploration between the hardware and software
partition when performing specific computation. The
performance metric is measured in logic cost and computation
cycle count.
In this experiment, a 32-bit Modular Multiplication
(mod_mul) function is being developed. The function can
generate 25 sets of 32-bit random number input operands (r, ,

), to perform the 32-bit modular multiplication (mod_mul)
consecutively. The modular multiplication algorithm is given.
The performance of the hardware and software partition is
being compared.
System on chip (SoC) refers to integrating all
components of a computer or other electronic system into a
single integrated circuit (chip). It may include digital,
analogue, mixed-signal, and often radio-frequency
functions on one single chip. A typical purpose of SoC is
for embedded systems. The major advantages of SoC
device is greatly reduce the size, cost, and power
consumption of a system. SoC device used in handheld
digital product has replaced bulkier and higher power
consuming digital systems into a board with several chips.
A system on chip may include a configurable logic unit.
The configurable logic unit includes a processor, interface,
and a programmable logic on the same device. As
technology advances, integration of various units included
in a SoC design becomes increasingly complicated. A SoC
device integrates into a single chip might have many of the
components of a complex electronic system, such as a
wireless receiver. This problem required good software
hardware co design process.
The common description for hardware/software
(HW/SW) co design is the meeting of system-level
II. ÷ITERATURE STUDY
An embedded system is the essence of every modern
electronic device, from toys to traffic lights to power plant
controllers. It covers all aspects of modern life and there are
many examples of their use. Watches, microwaves, and
phones make the most of embedded systems. An embedded
system is a specialized computer system which contained
hardware and software customized to perform one or few
particular tasks in real-time restrictions. They are generally
a part of larger system or machine (e.g., industrial
controllers) housed on a single microprocessor board with
the programs stored in ROM. Embedded systems are
controlled by one or more main processing cores that are
normally either microcontrollers or digital signal processors
(DSP).
Since the embedded system is dedicated to specific
tasks, design engineer can optimize it to reduce the size and
objectives by taking advantage of the trade-offs between
HW and SW in a system through their parallel design.
Interaction between HW and SW was developed at the
same time on parallel path to produce design that meets
performance and functional specs. The two key concepts
involved in co design are concurrent development of HW
and SW and integrated design. Integrated design allows
interaction between the design of HW and SW. Co design
techniques using these two key concepts take advantage of
design flexibility to create systems that can meet strict
performance requirements with a shorter design cycle. The
main reason motivating the need for HW/SW co design is
the fact that most systems today include both dedicated
hardware and software units on microcontrollers or general
purpose processors. Meanwhile, the increasing use of
programmable processors, available of cheap
microcontrollers, increased efficiency of higher level
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By increasing logic cost by 1.17 times, the execution time is
shortened by 33.64 times. Therefore, this trade off is
acceptable.
Running frequency( 100000000 Hz
Time taken(Software)( 503716 ticks
Time taken(Hardware)( 14971 ticks
1932757444*1812851329 mod 4294967295=142185736
786279284*481968937 mod 4160749567=890607585
1699140529*368211428 mod 3187671039=2547598544
1619701602*850790193 mod 4294967295=740490066
1642638206*810407642 mod 4294443007=4023211626
199959575*1030935169 mod 4294967295=1966239155
237895031*590249699 mod 4294967295=131936119
1997930855*53546138 mod 2147483647=670880292
668396581*1839177873 mod 4294967295=1633499898
638216208*1670124393 mod 4294967295=2273883489
332713197*1035074448 mod 4294836191=2738433170
V. CONC÷USION
In conclusion, the algorithm and the functionality of the
hardware are being verified while the timing for both
software and hardware executions show that the full
software implementation is slower than the hardware
implementation.
6
ACKNOW÷ED MENT
The authors would like to express their gratitude to
Universiti Teknologi Malaysia (UTM) for supporting this
laboratory.
REFERENCES
[1] Mohamed Khalil-Hani, PhD ,Irwansyah,A & Hau,Y.W.(2006). veCAD
1985900155*725370578 mod 4294967295=2373844565
Technical Report( NiosII Tutorial( Avalon Memory-Mapped (Avalon-
1302741285*134650351 mod 4278190079=3480589006
MM) Bus Interface Design of User-Designed ÷ogic in Slave Transfer
638160306*565314516 mod 4294967295=425204706
(VHD÷ Version)
1889387775*1286302809 mod 4294967295=570708015
598279984*371398014 mod 4294967295=2305680216 [2] ECAD PB÷ ÷aboratory, STUDENT PACK, HW/SW Co-design of a
1765157118*627747827 mod 4294967231=2726428706 Nios II-based Embedded System (2009)
2093973672*1774683490 mod 4294967295=3010521705 [3] ECAD PB÷ ÷aboratory, PROB÷EM PACK 7, HW/SW Co-design of a
1234867862*900890657 mod 4294963199=2671521229 Nios II-based Embedded System (2009).
282741182*1140457973 mod 4294967295=3174557551 [4] Mohamed Khalil-Hani, PhD.(2008). Digital system VHD÷ & Verilog
426936334*993029438 mod 4294967295=2955747092 Design(2 nd Edition).
714291992*22021730 mod 4294967295=1333203325 [5] http(//www.cplusplus.com/reference/clibrary/cstdlib/srand/
375146338*397206613 mod 4294967295=1646288869
2088659870*125417311 mod 4294967295=3307767680 [6] http(//soc.eurecom.fr/EDC/des_cop2/
217963178*957649779 mod 4261412863=751583278 [7] http(//www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html#_Toc52606
1364
[8] http(//www.velocityreviews.com/forums/t23789 -while-loop.html
Result Verification( [9] http(//www.freeinfosociety.com/site.php?postnum=485
1932757444 x 1812851329 [10] http(//en.wikipedia.org/wiki/Embedded_system
= 3503801900990043076 [11] http(//en.wikipedia.org/wiki/System -on-a-chip
3503801900990043076 ÷4294967295 [12] http(//www.npd-solutions.com/swcodesign.html
= 815792452.03310519643898708662926
Multiply the decimal point with divider to get the
remainder,
0.03310519643898708662926 x 4294967295
= 142185736

c5

Running frequency( 100000000 Hz

Time taken( 12359 ticks
1932757444*1812851329 mod 4294705143=344120785
481968937*1699140529 mod 4255121407=2627761612
1619701602*850790193 mod 4294967295=3119638564
810407642*199959575 mod 4294967295=740490066
237895031*590249699 mod 4293918719=3818040340
53546138*668396581 mod 4294967291=3387772582
638216208*1670124393 mod 4026531839=2934738067
1035074448*1985900155 mod 4294967295=679815706
1302741285*134650351 mod 4227857407=4194470430
565314516*1889387775 mod 4294967295=2228820368
598279984*371398014 mod 4294967287=51824115
627747827*2093973672 mod 4294967295=2719559960
1234867862*900890657 mod 4294967295=3015005904
1140457973*426936334 mod 2013265772=2582953174
714291992*22021730 mod 4293916671=574899538
397206613*2088659870 mod 3976200191=1802861821
217963178*957649779 mod 4294705023=2926194162
1714510321*1894596297 mod 4294959103=1911865590
762000468*989767529 mod 2147483643=2616249845
1299598477*1277489890 mod 4294967295=1813901745
1953573275*608438773 mod 4260364287=3987417940
1600570223*1112997517 mod 4289724415=2312138027
1880702872*471094094 mod 4294967279=3171707931
1806439037*1060615205 mod 4294705151=3224758328
1236269356*1695691943 mod 4294967231=636010679

Result obtained for hardware/software co-design

without delay
 V#$% <stdio.h>
V#$% <unistd.h>
V#$% "altera_avalon_pio_regs.h"
V#$% "system.h"
V#$% <stdlib.h>
V#$% "sys/alt_timestamp.h"
V#$% "alt_types.h"

alt_u32 mod_mul(alt_u64 V,alt_u64 A,alt_u32 P) {

alt_u64 U = 0;
.+#% (A != 0) {
7
# (A&0x01) { U = U V; }
# (U >= P) { U = U - P; }
A>>=1;
V<<=1;
# (V>=P) { V = V - P; }
}
!! U;
}

# seed=10;
)# generate_random(alt_u32 p[],alt_u32 x[],alt_u32 y[]) {
# i;
srand(seed);
77
! (i = 0;i<25;i ) {
.+#% (p[i] <= 1) p[i] = (rand())%((2^32) -1);
 {
x[i] = rand()%(p[i]);
}.+#% (x[i] == 0);
 {
y[i] = rand()%(p[i]);
}.+#% (y[i] == 0);
seed=i;
}}

# main () {
&#' # start,end;
alt_u32 p[25];
alt_u32 x[25];
alt_u32 y[25];
alt_u32 result[25];
# i;
generate_random(p,x,y);

#(alt_timestamp_start() < 0) printf("No timestamp device available \n");

%& {
printf("Running frequency( %u Hz \n", (&#' #)(alt_timestamp_freq()));
start = alt_timestamp();
77
! (i = 0;i<25;i ) {
result[i] = mod_mul(x[i],y[i],p[i]);
//result[i] = (x[i]*y[i])%p[i];
}
end = alt_timestamp();
printf("Time taken( %u ticks \n",(&#' #)(end - start));
}
77
! (i = 0;i<25;i ) {
printf("%lu*%lu mod %lu=%lu \n",x[i],y[i],p[i],result[i]);}
.+#%(1);
!! 0;
}

Source Code for Software Design

 V#$% <stdio.h>
V#$% <unistd.h>
V#$% <stdlib.h>
V#$% <time.h>
V#$% <pthread.h>
V#$% "altera_avalon_pio_regs.h"
V#$% "system.h"
V#$% "sys/alt_timestamp.h"
V#$% "alt_types.h"

V# dataX 0x00

V# dataY 0x01 Hardware Partition
V#
Delay dataZfor
added 0x02
correct result to be ready
V# start_pin 0x03
V# resultData 0x05
V# done_pin 0x04
alt_u32 mod_mul(alt_u32 V,alt_u32 A,alt_u32 P) {
alt_u8 done = 0;
alt_u32 U = 0;
IOWR(A÷U_AVA÷ON_0_BASE,dataX,V); // write dataX=V;
IOWR(A÷U_AVA÷ON_0_BASE,dataY,A); // write dataY=A;
IOWR(A÷U_AVA÷ON_0_BASE,dataZ,P); // write dataZ=P;
IOWR(A÷U_AVA÷ON_0_BASE,start_pin,0x01); // write dataZ=P;
 {
done = IORD(A÷U_AVA÷ON_0_BASE,done_pin); // loop & wait for done signal
}.+#% (!done);
# d=0;
.+#%(d<1)
88
{d ;}
U = IORD(A÷U_AVA÷ON_0_BASE,resultData); // store result into U
!! U;
}
# seed=10;
)# generate_random(alt_u32 p[],alt_u32 x[],alt_u32 y[]) {
# i;
srand(seed);
88
! (i = 0;i<25;i ) {
.+#% (p[i] <= 1) p[i] = (rand())%((2^32) -1);
 {
x[i] = rand()%(p[i]);
}.+#% (x[i] == 0);
 {
y[i] = rand()%(p[i]);
}.+#% (y[i] == 0);
seed=rand();
}}
# main () {
&#' # start,end;
alt_u32 p[25];
alt_u32 x[25];
alt_u32 y[25];
alt_u32 result[25];
# i;
generate_random(p,x,y);
#(alt_timestamp_start() < 0) printf("No timestamp device available \n");
%& {
printf("Running frequenc y( %u Hz\n", (&#' #)(alt_timestamp_freq()));
start = alt_timestamp();
88
! (i = 0;i<25;i ) {
result[i] = mod_mul(x[i],y[i],p[i]);
}
end = alt_timestamp();
printf("Time taken( %u ticks \n",(&#' #)(end - start));
}
88
! (i = 0;i<25;i ) {
printf("%lu*%lu mod %lu=%lu \n",x[i],y[i],p[i],result[i]);
}
.+#%(1);
!! 0;}

Source Code for Hardware/Software Co-Design

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     .++!&>@
      !   2/7.=4C>!&%6 
      
    $ &6
   #6
  #6
 !$&&6
c !$+6

VHD÷ code for A÷U_interface