Display,

Sensor actuators,
Input Processing Output
signals,
control

ADC Testing
Part 7 in a series of tutorials in
instrumentation and measurement

Thomas E. Linnenbrink, Jerome Blair, Sergio Rapuano, Pasquale Daponte,

Eulalia Balestrieri, Luca De Vito, Solomon Max, and Steven J. Tilden

nalog-to-digital converters (ADCs) are test- The following sections address general test setups,

A ed for several reasons. Manufacturers need

to measure the ADC’s performance so that
they can guarantee to their users what per-
formance to expect of the ADC (usually via a specifica-
tion sheet) and to assure the quality of the ADCs they
produce. Users need to measure the ADC’s performance
relative to its specification as well as for its intend-
ed use. Both static and dynamic performance
parameters may be assessed. It is impor-
tant for those measuring ADC perfor-
mance to communicate their findings
clearly. To that end, the IEEE
Instrumentation and Measurement
Society’s Waveform Generation,
Measurement, and Analysis
Committee (TC-10) developed the
IEEE Standard for Terminology and
Test Methods for Analog-to-Digital
Converters (IEEE Std 1241-2000) [1]. This
standard presents a wide range of terms and
test methods to serve as a common technical lan-
guage among users and manufacturers.
Since it would be prohibitively expensive for both
manufacturers and users to perform all possible tests,
only parameters critical to an application are generally
assessed. Table 1 suggests parameters critical to common
applications. These suggestions are intended to provide
a starting point from which to select a set of parameters
for a particular application.
common test methods, and the assessment of uncertainty
in measurements. The same tests are also performed on
digital waveform recorders, but the test setups are differ-
ent and are described in IEEE Std 1057-1994. See “ADC
Versus Waveform Recorder—What’s the Difference?” for
more information.
Test Setups
A few general test setups can be used
to perform most of the ADC tests. We
discuss several primary types below.
Sine Wave Test Setup
Sine waves are commonly used in
ADC testing because appropriate
sine wave sources are readily avail-
able and because it is relatively easy to
establish the quality of sine wave (e.g.,
with a spectrum analyzer). The sine wave
test setup, shown in Figure 1, comprises a
sine wave generator providing the test signal and a
clock generator providing the clock (or conversion) signal.
If frequency synthesizers are used to generate the test and
clock signals, the synthesizers can often be phase locked to
maintain precise phase relationships between the signal and
the sampling clock. Phase locking of synthesizers facilitates
testing and simplifies subsequent digital signal processing,
by preventing clock/signal walkthrough (beat patterns),
which may artificially increase or reduce measured spurious

April 2006 IEEE Instrumentation & Measurement Magazine 39

1094-6969/06/$20.00©2006IEEE
output. The type of circuitry used to capture the digital data
samples produced by the ADC is determined largely by the data
rate. Slower ADCs may be interfaced directly to the computer.
Faster ADCs often require a buffer memory to acquire data at
the ADC sample rate and then download stored samples to the
computer at a slower rate. Even faster ADCs may require latch-
es or demultiplexers between the ADC and the buffer memory
and perhaps data decimation. A logic analyzer might be used as
a buffer memory to capture data for some tests.
Both the clock and the test signals must be suitable for the
test being performed. Filters may be required in either the
clock or signal paths to reduce noise or harmonic distortion.
For example, subharmonics in the clock path will degrade
ADC performance, so the clock signal may require filtering
to smooth edges that might otherwise feed through to the
signal path. Also, low-pass or band-pass filters may be
required in the signal path to eliminate noise or other unde-
sirable signals (e.g., harmonics).
Arbitrary Waveform Test Setup
The arbitrary waveform test setup of Figure 2 can be used
for arbitrary test signals, such as ramps, chirps, and steps.

Table 1. Critical ADC parameters [1].

Typical Applications Critical ADC Parameters Performance Issues
Audio SINAD, THD Power consumption
Crosstalk and gain matching
Automatic control Monotonicity Transfer function
Short-term settling, long-term stability Crosstalk and gain matching
Temperature stability
Digital oscilloscope/ SINAD, ENOB SINAD for wide bandwidth amplitude
waveform recorder Bandwidth resolution/low thermal noise for
Out-of-range recovery repeatability
Word error rate Bit error rate
Geophysical THD, SINAD, long-term stability Millihertz response
Image processing DNL, INL, SINAD, ENOB DNL for sharp-edge detection
Out-of-range recovery High-resolution at switching rate
Full-scale step response Recovery for blooming
Radar and sonar SINAD, IMD, ENOB SINAD and IMD for clutter cancellation
SFDR and Doppler processing
Out-of-range recovery
Spectrum analysis SINAD,ENOB SINAD and SFDR for high linear
SFDR dynamic range measurements
Spread spectrum SINAD, IMD, ENOB IMD for quantization of small signals
communication SFDR, NPR in a strong interference environment
Noise-to-distortion ratio SFDR for spatial filtering
NPR for interchannel crosstalk
Telecommunication SINAD, NPR, SFDR, IMD Wide input bandwidth channel bank
Personal communications Bit error rate Interchannel crosstalk
Word error rate Compression/power consumption
Video DNL, SINAD, SFDR, DG, DP Differential gain and phase errors
Frequency response
Wideband digital receivers SFDR, IMD Linear dynamic range for detection of
SIGINT, ELINT, COMINT SINAD low-level signals in a strong
interference environment
Sampling frequency
Instrumentation INL, DNL, gain, offset Long term stability, traceability

Notes:
COMINT: communications intelligence SIGINT = signal intelligence
DNL: differential nonlinearity SINAD: signal-to-noise and distortion ratio
ENOB: effective number of bits THD: total harmonic distortion
ELINT: electronic intelligence IMD: intermodulation distortion
NPR: noise power ratio SFDR: spurious free dynamic range
INL: integral nonlinearity DP: differential phase error
DG: differential gain error

40 IEEE Instrumentation & Measurement Magazine April 2006

 Display,
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In this setup, the test signal is generated digitally then Common Static Test Methods
converted to analog. You must quantify the performance Static parameters describe the ADCs fundamental perfor-
of the digital-to-analog converter (DAC) and filter to mance with essentially nonvarying or slowly varying input
assess (or remove) its impact on the measured perfor- signals. The ADC’s static performance is often regarded as a
mance of the ADC under test. baseline since the ADC’s performance tends to degrade as
the input signal’s frequency increases.
Step Waveform Test Setup
You can use the step waveform test setup, shown in
Figure 3, for testing with precision step signals that are
not digitally generated. Precision pulses and step signals
ADC Versus Waveform Recorder—
can be used to measure both time domain parameters
What’s the Difference?
here are two IEEE standards, IEEE Standard for
(such as impulse response, transition duration, over-
shoot, and settling time) and frequency domain parame-
T Terminology and Test Methods for Analog-to-
Digital Converters (IEEE Std 1241-2000) and IEEE
ters (such as frequency response amplitude and phase,
Standard for Digitizing Waveform Recorders (IEEE
bandwidth, and gain flatness). If the optional pulse repe-
Std 1057-1994), that cover very similar material. In
tition generator is phase locked to the sampling clock,
fact, all of the figures of merit introduced in the
then you can use equivalent time sampling and simplify
previous article (i.e., Part 6 in this series of tutorials
certain data analysis tasks. You must pay careful atten-
[3]) are essentially identical in the two standards,
tion to the phase linearity of any filters placed in the
and the test methods are the same at the highest
pulse or step signal path.
level. So why are there two standards? A digital
waveform recorder is a complete instrument, such
Feedback Loop Test Setup (Servo Test)
as a digital oscilloscope, that uses one or more
A widely used test method for determining transition lev-
ADCs as an important element, whereas an ADC is
els is based on a feedback loop. In this method, you apply
a single component. Most of the tests in this article
an input to the ADC, trigger the converter, and compare
are easier to perform on a waveform recorder than
the results of the conversion to a desired value. If the
on an ADC, because much of the test setup (e.g.,
ADC output is below the desired value, the input is raised
power supplies, buffer amplifiers, clocks, and
by a fixed amount. If the ADC output is equal to or above
memory) is built into the waveform recorder but
the desired value, the input is lowered by a fixed amount.
has to be supplied by the tester when testing an
You repeat this process until the ADC input has settled to
ADC. So the test setups in the waveform recorder
a stable average value that can be measured by the volt-
standard are generally less complex than those in
meter. After the loop has settled, the input value can
this article and in the ADC standard.
either be measured or, if the input source is well calibrat-
Information about both of these standards
ed, computed from its transfer function. Figure 4 illus-
and other activities of the IEEE Instrumentation
trates a block diagram for the Servo Test. In this diagram,
and Measurement Society’s TC-10 can be found
a DAC generates the feedback signal, but other implemen-
at http://grouper.ieee.org/groups/1057/.
tations are possible, including the classic analog one,
which is shown in Figure 5.

Clock Generator
(Frequency Filter Required
Generator) Optional

Sine Wave
ADC
Generator Latch/ Buffer
∑ Filter Under Computer
(Frequency Demux Memory
Test
Synthesizer)
Programable
Delay
Signal
Generator
(Frequency
Synthesizer)

Fig. 1. Sine wave test setup.

April 2006 IEEE Instrumentation & Measurement Magazine 41

 An ADC has four parameters that describe the nature of
the static transfer characteristics: gain, offset, integral nonlin-
earity (INL), and differential nonlinearity (DNL). One of the
simpler approaches to testing involves a single test process,
ramp testing, which can be used to extract these parameters
(with some caveats).
Figure 6 describes the transfer characteristics of an
ideal 3-bit ADC with a voltage input. There are several
properties that are demonstrated in the figure that are
worth noting.
◗ The code edges, described by the array T[k], where
1 ≤ k ≤ 2N − 1, describe the transfer characteristic of an
ADC.
◗ T[1], the lower edge of the output code 0012 , is also the
upper edge of the code 0002 .
◗ The full scale range (FSR) of the ADC is, by convention,
defined as V max −V min , where V max is the center of a vir-
tual code one greater than the maximum code that can
be generated by the ADC, and V min is the center of the
zero code. As an example, in the 3-bit ADC shown in
the figure, V max could be 8 V and V min could be 0 V. The
FSR would then be 8 V, T[1] would be 0.5 V, and T[7]
would be 6.5 V.
◗ Figure 6(b) shows the difference between the output code
translated into input units and the input signal. Note
that, at all points other than the center of the codes, the
ideal ADC will not exactly describe the input signal. This
deviation is called the quantization error.
◗ The center of the codes cannot be directly measured;
only the code transitions can be measured.
The gain of an ADC is nominally defined as 1.0. It is cal-
culated from (1). The values corresponding to the ADC
described in Figure 6 are given in brackets
G × T[k] +V os + ε[k] = Q × (k − 1) + T1 , (1)
where T[k] is the input value corresponding to the transition
between codes k and k − 1; T1 is the ideal value corresponding
to T[1], [0.5]; V os is the output offset in units of the input quanti-
ty, nominally equal to zero, [0.0]; G is the gain, nominally equal
to unity, [1.0]; Q is the ideal width of a code bin, i.e., the FSR
divided by the total number of codes, [1.0]; and ε[k] is the resid-
ual error corresponding to the kth code transition.
The values of G and V os , which cause ε[1] and ε[2N − 1] to
be zero, are the terminal-based gain and offset. Once the val-
ues of T[k] are known, the value of G can be computed as
FSR N
(2 − 2)
2N
G= . (2)
T[2N − 1] − T[1]

Clock Generator Programable

Filter Required
(Frequency Generator) Delay
Optional

ADC
Control and Latch/ Buffer
DAC Filter Under Computer
Local Memory Demux Memory
Test

Fig. 2. Arbitrary waveform test setup.

Clock Generator
Filter
(Frequency Generator)

Pulse Repetition Required

(Frequency Synthesizer) Optional

ADC
Latch/ Buffer
Pulse Generator Filter Under Computer
Demux Memory
Test

Fig. 3. Step waveform test setup.

42 IEEE Instrumentation & Measurement Magazine April 2006

 Display,
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Input Processing Output
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control

The offset V OS can be computed from The values of the two end-point transitions can be com-
puted from the following expressions:
V OS = T1 − G · T[1]. (3)

N VP −VM
The values of G and V os , which cause 2k=1−1 ε[k]2 to be a T[1] = VM + Hc [0] (7)
S
minimum, are the independently based gain and offset. VP −VM
T[2N − 1] = VM + Hc [2N − 2]. (8)
The INL can be determined after the gain and offset have S
been determined by
The parameters A and C can then be computed from the end
ε[k]
INL[k] = . (4) point values with the following expressions:
FSR

INL can be expressed either in units of least significant

(T[2N − 1] − T[1])
bits (LSBs) or as a fraction of FSR [parts per million (ppm) A= (9)
(Hc [2N − 2] − Hc [0])
or percent].  
H[0] · (T[2N − 1] − T[1])
The DNL can be determined after the gain and offset C = T[1] − . (10)
(Hc [2 − 2] − Hc [0])
N
have been determined in units of LSBs by

 
T[k + 1] − T[k] The gain and the offset of the ADC under test based on the end-
DNL[k] = −1 . (5)
Q points can be computed once the values of T[k] are known.
The independently based gain and offsets are computed
Determining Transition Levels T[k]— with a least mean squares algorithm, which is described in
Ramp-Based Method IEEE Std 1241-2000.
Apply a ramp to the ADC under
test. The ramp should start at a
known voltage VM, which is Clock
less than V min . The ramp should k
Word
terminate at a voltage VP, which ADC
Reference
Comparator Code
is greater than V max . An example Under A B
kin
of such an input is shown in Test
A<B
Figure 7. Voltmeter
Triggers are applied to the
ADC while the slow ramp is mov- Trig 1
N1 N2
ing from its initial position to its
final position. The total number of
triggers needed should be enough
to trigger the ADC many times at SUB N1 ADD N2
DAC
each step. A count is kept of the
Adder
number of times each code of the
NDAC
ADC is observed. The resultant
histogram of the code hits is
Fig. 4. Feedback loop test setup.
stored in the array H[k], where
0 ≤ k ≤ 2N − 1. The array of the
threshold values can be computed from the histogram with Potential Problems—Ramp-Based Method
There are several concerns that may arise when the ramp-
T[k] = C + A · Hc [k − 1] for k = 1, 2, . . . , (2N − 1), (6) based method is used.
◗ The linearity of the applied ramp directly affects the
where A is a gain factor and C is an offset factor; accuracy of the INL data.
 j ◗ The precision of the starting level and the stopping level
Hc [ j] = H[i] , of the ramp (VM and VP) will directly influence the
i=0 gain and offset calculations.
where H[i], is the number of histogram samples received in ◗ The presence of ADC input noise will affect the accura-
code bin i; and cy of the measurement. Generally, the uncertainty of the
2
N
−1 evaluation of the code transition levels will vary as the
S= H[i] = Hc [2N − 1], square root of the number of conversions that occur at
i=0 each code. This topic is discussed in greater detail in
where S is the total number of samples taken. IEEE Std 1241-2000.

April 2006 IEEE Instrumentation & Measurement Magazine 43

Determining Transition Levels T[k]— The ADC is triggered at a rate near its maximum spec-
Servo-Based Method ified trigger frequency. After every conversion, you com-
A classic method for determining ADC threshold levels is pare the output to the reference code word. If the ADC
known as the servo method. A feedback system is set up to output is greater than the reference code, then the polari-
compare the ADC output code with a desired code. With ty of the integrator input current is reversed and the inte-
proper algorithms, the input to the ADC will average out to grator output decreases. You can measure the average
be the value that defines the code edge. A block diagram of value of the ADC input with a voltmeter; the measured
the classic implementation of the servo is shown in Figure 5. voltage corresponds to the lower transition level corre-
sponding to the reference code
word. Newer implementations
of the servo are described in
Clock IEEE Std 1241-2000.
Word Reference
ADC k Comparator Code
Other Methods
Under A B kin
Test of Determining
A>B Transition Levels T[k]
Voltmeter
c The code transition levels can be
I1 measured using several other
algorithms.
s1
◗ The ac histogram method. This is
—
useful when the ADC input is
s2 ac coupled. It is also useful in
I2 evaluating how the transition
levels change with the frequen-
Fig. 5. Block diagram of analog servo for determining ADC code transitions. cy of the applied input.
◗ The manual method. A voltage source is slowly varied
until a code transition is observed. The value of the
input is then recorded as the transition level. This is
3Q/2 generally a throwback to days when computers were
Q not as readily available as they are today.
111 ◗ The triangle histogram method. This method is a variation
T [2N−1]
on the ramp algorithm. It is useful if the ADC has some
filtering at its input.
Figures 8 and 9 are INL and DNL plots of a 9-bit ADC to
show some typical results.
100
Common Dynamic Test Methods
Dynamic tests establish the ADC’s performance with signals
Q/2 that change with time. The selection of which dynamic tests
to perform generally depends on the application (see Table
T [1] 1). The following subsections present some of the more com-
Input mon dynamic tests.
000 FSR
Vmin (Vmin + Vmax)/2 Vmax
Total Harmonic Distortion Estimation
(a)
You use the sine wave test setup to estimate the total har-
monic distortion (THD) of an ADC. Apply a test signal con-
sisting of a pure, large amplitude sine wave at frequency fi
Q/2 as the input to the ADC. This test, being based on discrete
Fourier transform (DFT) analysis of unwindowed sample
Input sets, requires knowing or controlling accurately the test fre-
quency fi so that it coincides exactly with a DFT basis fre-
−Q/2 quency. Moreover, the test and sample frequencies should
be selected such that all possible ADC states within the
(b) amplitude range of the test signal can be sampled.
For this analysis, you acquire K data records of M points
Fig. 6. The transfer characteristic of an ideal 3-bit ADC. each from the ADC under test at sample frequency fs. For

44 IEEE Instrumentation & Measurement Magazine April 2006

 Display,
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each record of sine wave data, compute the DFT. You use
the K sets of data to compute an averaged magnitude spec-
trum of the DFT bins at each basis frequency fm.
At this point, identify the set of frequencies fh that cor-
respond to the chosen set of harmonics of the input test
frequency. For a test tone at frequency fi, the harmonics
are aliased so that fh lies between zero and the sampling
frequency fs. The input frequency and each harmonic map
into two different frequencies in the DFT, one correspond-
ing to positive frequencies and one to negative frequen-
cies. The choice of harmonic components included in the
set should be done including the harmonics with a signifi-
cant portion of the distortion energy and excluding DFT
bins whose energy content is dominated by random noise.
The tradeoff suggested in IEEE Std 1241-2000 to estimate
THD includes in the set the lowest nine harmonics, second
through tenth, inclusive, of the input sine wave. Finally,
compute the THD:

|Xavm ( fi)|
SFDR = 20 log10   . (13)
max fsp , fh |Xavm ( fsp )|, |Xavm ( fh )|
You must specify the amplitude and frequency of the input
and the sample frequency for which SFDR measurement(s)
are made.
Signal-to-Noise-and-
Distortion Ratio Estimation
You again use the sine wave test setup to estimate the signal-
to-noise-and-distortion ratio (SINAD) of an ADC. Therefore,
apply a sine wave of specified frequency and amplitude to
the ADC input. A large signal (approaching full scale) is pre-
ferred. Almost any error source in the sine wave input, other
than gain accuracy and dc offset, can affect the test result. So,
we recommend that you use a sine wave source with good
short-term stability and that the sine wave input be highly

1 
(Xavm ( fh ))2
M h
THD = , (11) Vmax
VP
Arms

where Xavm ( fh ) is the averaged magnitude of the component

at the hth harmonic of the DFT of the ADC output data
record and M is the number of samples in the data record.


1  2  2
Arms = Xavm ( fi) + Xavm ( fs − fi) (12)
M
Vmin
VM
is the rms of the output fundamental component at the
signal test frequency, fi = Jfs/M. Triggers

Spurious-Free-Dynamic-Range Estimation
To estimate the spurious free dynamic range (SFDR) of an Fig. 7. Ramp waveform applied to ADC for evaluating transition levels.
ADC, the procedure for THD is
used, considering also a set of
spurious frequencies fsp. A spuri-
ous frequency is the frequency of Plot of INL of 9-bit ADC
0.8
a persistent spectral output com-
ponent that is neither the funda- 0.6
mental nor a harmonic distortion
component. You determine the set 0.4
by inspection of the ADC output
Error(LSB)

spectrum, so there are no direct 0.2

equations to determine it. For a
pure sine wave input, the SFDR is 0
0 64 128 192 256 320 384 448 512
the ratio of the amplitude of the
averaged DFT value at the funda- −0.2
mental frequency fi, to the ampli-
tude of the averaged DFT value of −0.4
the largest magnitude harmonic
−0.6
or spurious signal component Code
observed over the full Nyquist
band, max{Xavm ( fh ), Xavm ( fsp )} Fig. 8. Plot of 9-bit ADC INL results based on terminal value gain computation.

April 2006 IEEE Instrumentation & Measurement Magazine 45

 Signal-to-Noise
Ratio Estimation
9-bit ADC DNL Plot The signal-to-noise ratio is called
0.2
SNR; it is called signal-to-nonhar-
0.1 monic ratio (SNHR) in [1], but the
0 name will be changed to SNR in the
0 128 255 384 512
next revision. To estimate the SNR,
−0.1
use the sine wave test setup. The test
−0.2
Error(LSB)

procedure is the same followed for

−0.3 the THD test. The SNR is obtained
−0.4 from the DFT by excising the signal
harmonic frequencies identified
−0.5
from the test signal spectrum.
−0.6 The rms signal, Arms (in LSB’s), is
−0.7 the same as reported in (12). After
the components bins corresponding
−0.8
Code to dc, the test frequencies fi and
( fs − fi), and the specified harmonic
Fig. 9. Plot of 9-bit ADC DNL results based on terminal value gain computation. frequencies are all set to zero, the rms
noise is found from the sum of all the
remaining Fourier components as:
filtered to remove distortion and random noise from the


input signal. M−1
1 
After applying a sine wave, a record of data is acquired. A rms noise =  Navm ( fm )2, (16)
sine wave function is fitted to the record by varying the phase, M m=0
amplitude, dc value, and (if needed) frequency of the fit func-
tion to minimize the sum of the squared difference between the where Navm is the averaged DFT spectrum after setting the
function and the data. IEEE Std 1241-2000 suggests two algo- bins to zero.
rithms for least squared fitting, one for known frequency solu- SNR is then computed by
tions, when the ratio between the sample frequency and the
input frequency is known and stable, and one for other cases. rms signal
SNR = . (17)
The SINAD is computed as rms noise

rms signal Effective Number of Bits Estimation

SINAD =
rms noise To estimate the effective number of bits (ENOB) of an ADC,
√
sine wave peak amplitude/ 2 the sine wave test setup is used. For an input sine wave of
=
, (14)
 specified frequency and amplitude, after correction for gain
1  M
 
 yn − yn
2
and offset, the ENOB is
M n=1
 
rms noise
where yn is the sample data set and yn
is the data set of the ENOB = N − log2
ideal rms quantization error
best sine wave fit.  
full scale range
SINAD can be determined equivalently from the fre- = log2 √ , (18)
Q/ 12
quency domain. You must follow the procedure for the THD
test. You can determine the rms input signal and the rms
noise and distortion from the DFT of data records. The rms where N is the number of digitized bits and Q is the ideal
signal, Arms (in LSBs), is the same reported in (2). code bin width, expressed in input units. ENOB generally
To determine the rms noise, set the dc and frequency depend on the amplitude and frequency of the applied sine
bins, fi and ( fs − fi), to zero. Then, the rms noise is found wave. You must specify the amplitude and frequency at
from the sum of all the remaining Fourier components as which the measurement is made.

Bandwidth Estimation
M−1
1 
rms noise =  Eavm ( fm )2, (15) To estimate the bandwidth of an ADC, use the sine wave test
M m=0 setup and add an ac voltmeter. Use a large signal sine wave
(the signal must span at least 90% of the full-scale range of
where Eavm is the residual spectrum of Xavm . the ADC under test), unless the small-signal bandwidth is to

46 IEEE Instrumentation & Measurement Magazine April 2006


be determined. When small-signal bandwidth is to be deter-
mined, the peak-to-peak input amplitude used is less than
one-tenth of full scale.
The input sine wave source should produce sinusoids of
high spectral purity (i.e., harmonic distortion lower than
that of the ADC under test) and should have stable output
during the measurement time. The tested input frequencies
should not be subharmonics of the ADC sampling rate
since such frequencies can produce incorrect results in this
test. An input frequency at which the ADC’s dynamic gain
is equal to or near its peak value in the pass band is select-
ed as a reference frequency. After connecting the sine gen-
erator to the ADC input, you set its frequency to the
reference frequency fref and acquire a sufficient number of
data records from the ADC output to determine the maxi-
mum peak-to-peak range of the signal using a three-
parameter or four-parameter sine fit. The input amplitude
measurement must be done with care if high accuracy is
required. If the measured input amplitude parameter is the
rms amplitude, Arms , you must convert it to peak-to-peak
√
amplitude by multiplying it by 2 2. Divide the peak-to-
peak ADC output amplitude by the measured peak-to-
peak input amplitude to determine the reference gain. If
the chosen fref is zero, the reference gain is the static gain.
Alternatively, to determine the static gain, you can use a
precision dc signal source to provide a constant input sig-
nal. The dc gain is approximated by the constant output
signal level minus the measured static dc offset divided by
the input dc level.
Once the reference gain is determined, you change the
input frequency to another value that is not a sampling-rate
subharmonic. You then measure the maximum peak-to-peak
range of the recorded data and divide it by the input ampli-
tude measured by the ac voltmeter to find the gain at this
frequency. You repeat as necessary to find the upper (and, if
it exists, lower) frequency, closest to the reference frequency,
at which the gain is 3 dB below the reference gain. If no
lower −3 dB frequency exists, the upper −3 dB frequency is
the bandwidth. If a lower −3 dB frequency exists, the differ-
ence between the upper and lower −3 dB frequencies is the
bandwidth of the ADC.
This test uses sine wave inputs and can be done very
quickly if the reference frequency and the approximate
limit frequencies are known. The disadvantage is the typ-
ically low accuracy of estimates of the analog input
amplitudes, which reduces the accuracy of the band-
width result as well.
IEEE Std 1241-2000 proposes an alternative bandwidth
test method, which is generally more useful for ADCs that
contain analog bandwidth limiting circuitry before the
quantizer(s). You use the step signal test setup to deter-
mine the ADC frequency response. It is desirable to have
as many samples in the record as possible, to increase the
resolution with which the bandwidth can be resolved from
the DFT of the derivative of the step response. The sam-
pling rate, or equivalent-time sampling rate, should be
April 2006 IEEE Instrumentation & Measurement Magazine
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control
high enough to make aliasing errors negligible. The fref is
chosen from the DFT bins. It must be one within the pass
band such that the dynamic gain is at or near the peak gain
of the pass band.
You analyze the DFT bins to find the upper and, if appli-
cable, the lower frequency samples closest to the reference
frequency at which the gain is 3 dB below the reference gain.
The bandwidth is the difference between these upper and
lower −3 dB sample frequencies (or, if a lower −3-dB fre-
quency does not exist, the bandwidth is simply the upper
−3-dB frequency value). To improve the bandwidth esti-
mate, interpolate between the frequency samples above and
below −3 dB in amplitude to better estimate the actual −3-
dB frequency.
The disadvantages of this test are high noise at higher
frequencies and aliasing and first-differencing errors result-
ing from the frequency response estimation. The results of
using the step response method are invalid in the presence
of slew rate induced errors.
Gain Error Estimation
To estimate the gain error of an ADC, the sine wave based
methods or the differentiated step response method can be
used. Gain error, also known as gain flatness, is the differ-
ence between the dynamic gain, G(f), of the ADC at a
given frequency and its gain at a specified reference fre-
quency, divided by its gain at the reference frequency. The
dynamic gain of the ADC under test at a frequency f is the
magnitude of the frequency response at that frequency.
The reference frequency is chosen to be a frequency whose
gain is at or near the peak gain of the ADC pass band; typ-
ically, it is the same frequency as the one used in the band-
width test. For dc-coupled ADCs, the reference frequency
is typically dc ( f = 0).
Aperture Delay Estimation
To estimate the aperture delay of an ADC, apply a ramp to
the analog input and apply a clock signal to the clock
input of the ADC adapting the arbitrary signal test setup.
Instead of a ramp signal at the analog input, you can use a
portion of another waveform (e.g., a sine wave) provided
that the slew rate of the waveform does not vary substan-
tially over the aperture width of the ADC (e.g., a sine
wave of frequency less than half the analog bandwidth of
the ADC). The ramp signal slew rate should be as high as
possible without exceeding the slew rate limit of the ADC
or causing excessive dynamic errors. The ramp and the
clock must be synchronized such that the ADC samples
the ramp at the center of the ADC full-scale range. Using a
time-interval meter or oscilloscope with sufficient resolu-
tion and accuracy, the time delay is measured from the
time instant the clock input crosses its threshold to the
instant the analog input crosses the dc value correspond-
ing to the center of the ADC full-scale range. For ADCs
with very high sample rate, where the aperture delay may
be similar in magnitude to the clock period, extra care
47
must be taken to measure the correct clock edge. This can
be done by repeating the measurement at various clock
frequencies. The aperture delay as a function of clock peri-
od should be roughly flat.
Aperture Uncertainty
To measure the aperture uncertainty of an ADC, couple
the output of a stable signal generator to both the analog
input and the clock input of the ADC, using appropriate
signal splitters, attenuators, dc blocks, frequency multipli-
ers/ dividers, and delay circuits, to ensure that the signal
amplitude, offset, and frequency at each input are appro-
priate. When possible, no active component should be
used for coupling, as any jitter in those components
would contribute to the overall measured aperture uncer-
tainty. The slew rate of the signal at the analog input port
should be as high as possible without exceeding the slew
rate limit of the ADC input or causing excessive dynamic
errors. The delay of the path is adjusted from the signal
generator to the analog input port to be longer than the
delay to the clock input port by the amount of the aper-
ture delay, such that each active clock edge is sampling
itself at its midpoint. The connection between the signal
generator and the analog input port are broken, and both
ends of the broken connection are terminated appropriate-
ly to prevent reflections.
The aperture uncertainty is then given by


σA2 − σB2
σT = , (19)
slew rate
where σA2 is the measured noise variance with clock signal
applied to the analog input port, σB2 is the measured noise
variance without the clock signal applied to the analog input
port, and slew rate is magnitude of the slope of the clock sig-
nal at the analog input port at the sampling instant.
Measurement Uncertainty
The objective of a measurement is to determine the value of
the measurand that is the specific quantity subject to mea-
surement. In general, no measurement or test is perfect and
the imperfections give rise to errors in the result.
Consequently, the result of a measurement is only an
approximation to the value of the measurand and is only
complete when accompanied by a statement of the uncer-
tainty of that approximation. The International Vocabulary of
Basic and General Terms in Metrology defines uncertainty as “a
parameter associated with the result of a measurement, that
characterizes the dispersion of the values that could reason-
ably be attributed to the measurand” [2].
Tutorial 8, to be published in an upcoming issue, will
cover measurement uncertainty in detail.
Conclusion
ADCs provide an important function in a wide range of
modern equipment. The impact of the ADC’s performance
48 IEEE Instrumentation & Measurement Magazine
on that of a complete system can be critical. Therefore, it is
important to use commonly understood terms and test
methods to describe the ADC’s performance. Finally, it is
important to understand the confidence with which the mea-
surement data are stated. (Tutorial 8 will go into detail about
measurement uncertainty.)
References
[1] IEEE Standard for Terminology and Test Methods for Analog-to-
Digital Converters, IEEE Std 1241-2000.
[2] International Vocabulary of Basic and General Terms in Metrology
(VIM), ISO, 1993.
[3] S. Rapuano, P. Daponte, E. Balestrieri, L. DeVito, S.J. Tilden, S.
Max, and J. Blair, “ADC parameters and characteristics,” IEEE
Instrum. Meas. Mag., vol. 8, no. 5, pp. 44–54, Dec. 2005.
Thomas E. Linnenbrink (toml@hittite.com) received a B.S.
degree in electrical engineering in 1967 from the Illinois
Institute of Technology and a M.S. degree in engineering sci-
ence with emphasis in automatic control from the Rensselaer
Polytechnic Institute in 1971. He cofounded Q-DOT, Inc. in
1977. He is currently a business development manager for
Hittite Microwave, which acquired Q-DOT in 2005. He has
been active in the IEEE Instrumentation and Measurement
Society’s Waveform Generation, Measurement, and Analysis
Committee (TC-10) since its inception and has served as its
chair since 1997.
Jerome Blair received a B.S. degree in engineering physics in
1966 and a Ph.D. in applied mathematics in 1970, both from
the University of California, Berkeley. He has worked since
1966 on the design and analysis of complex instrumentation
systems and has been a Member of IEEE I&M TC-10 since
1989 and is an IEEE Fellow.
Sergio Rapuano achieved the master’s degree cum laude
in electronic engineering from the University of Salerno in
1999. In 2002, he joined the Faculty of Engineering of the
University of Sannio as assistant professor of electric and
electronic measurement. In 2003, he obtained the Ph.D.
degree in computer science, telecommunications, and
applied electromagnetism. He is an IEEE I&M TC-10
member and secretary of the IEEE TC-23 Working Group
on e-tools for Education in Instrumentation and
Measurement.
Pasquale Daponte obtained his master’s degree cum
laude in electrical engineering in 1981 from the University
of Naples. He is a full professor of digital signal process-
ing and measurement information at the University of
Sannio, Benevento. He is a Senior Member of the IEEE
I&M Society and a Member of IEEE I&M TC-10. He is
coordinator of the IMEKO Working Group on ADC and
DAC Metrology and deputy of the International Relations
for the University of Sannio.
April 2006
 Display,
Sensor actuators,
Input Processing Output
signals,
control

Eulalia Balestrieri achieved the master’s degree in 2003 in
software engineering from the University of Sannio. She
joined the research activities carried out at the Laboratory of
Signal Processing and Measurement Information of the
University of Sannio, Benevento. In 2004, she began a Ph.D.
course in information technology. She is a member of the
IEEE I&M TC-10.
1961, respectively. He has two patents involving mixed-sig-
nal technology. He is currently a staff scientist and LTX
Fellow at LTX corporation where he was one of the founders
of the company in 1976. At LTX, he developed many of the
test instruments used in ATE systems. He is a Senior
Member of the IEEE and a member of Eta Kappa Nu, Tau
Beta Pi, and Sigma Xi.

Luca De Vito achieved the master’s degree cum laude in
2001 in software engineering from the University of Sannio.
Then, he joined the research activities carried out at the
Laboratory of Signal Processing and Measurement
Information of the University of Sannio, Benevento. He
achieved the Ph.D. in information engineering in 2005 from
the University of Sannio. Currently, he is a software design-
er at Telsey telecommunications. He is a member of the IEEE
I&M TC-10.
Solomon Max has worked in the mixed-signal field for
almost 50 years. He received his B.E.E. degree from City
College of New York in 1957, and S.M. and E.E. degrees
from the Massachusetts Institute of Technology in 1959 and
Steven J. Tilden has more than 33 years electronics experi-
ence, six in the U.S. Air Force and the last 27 in Tucson,
Arizona, at Burr-Brown, which became Texas Instruments in
2000. He has worked in nearly every area from wafer fabrica-
tion through final test in several engineering disciplines. He
a Senior Member of the IEEE and a senior member technical
staff at Texas Instruments. He is chair of the IEEE TC-10
subcommittee that published ADC test methods and termi-
nology standard 1241, is chair of the IEEE TC-10 subcommit-
tee on digital-to-analog converters, and is a U.S. national
delegate to the International Electrotechnical Commission
for semiconductor, integrated circuits, which are publishing
IEC-level ADC and DAC test and terminology standards
through TC47/SC47A/WG4.

Call for Papers

2007 IEEE Sensors Applications Symposium
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San Diego, California, USA
www.sensorapps.org

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April 2006 IEEE Instrumentation & Measurement Magazine 49